BUK9E8R5-40E N-channel TrenchMOS logic level FET 11 September 2012 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in a SOT226 package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 1.2 Features and benefits • AEC Q101 compliant • Repetitive avalanche rated • Suitable for thermally demanding environments due to 175 °C rating • True logic level gate with Vgst(th) rating of greater than 0.5V at 175 °C 1.3 Applications • 12 V Automotive systems • Motors, lamps and solenoid control • Start-Stop micro-hybrid applications • Transmission control • Ultra high performance power switching 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 40 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 1 - - 75 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 96 W VGS = 5 V; ID = 20 A; Tj = 25 °C; Fig. 11 - 6.4 8.1 mΩ VGS = 5 V; ID = 20 A; VDS = 32 V; - 7.3 - nC [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge Fig. 13; Fig. 14 [1] Continuous current is limited by package. Scan or click this QR code to view the latest information for this product BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb G S mbb076 1 2 3 I2PAK (SOT226) 3. Ordering information Table 3. Ordering information Type number Package BUK9E8R5-40E Name Description Version I2PAK plastic single-ended package (I2PAK); TO-262 SOT226 4. Marking Table 4. Marking codes Type number Marking code BUK9E8R5-40E BUK9E8R5-40E 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 40 V VDGR drain-gate voltage RGS = 20 kΩ - 40 V VGS gate-source voltage Tj ≤ 175 °C; DC -10 10 V ID drain current Tj ≤ 175 °C; Pulsed [1][2] -15 15 V Tmb = 25 °C; VGS = 5 V; Fig. 1 [3] - 75 A Tmb = 100 °C; VGS = 5 V; Fig. 1 - 56 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 315 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 96 W BUK9E8R5-40E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 2 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Tstg Tj Conditions Min Max Unit storage temperature -55 175 °C junction temperature -55 175 °C - 75 A - 315 A - 44 mJ Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C [3] Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 75 A; Vsup ≤ 40 V; RGS = 50 Ω; [4][5] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 3 [1] [2] [3] [4] [5] Accumulated pulse duration up to 50 hours delivers zero defect ppm Significantly longer life times are achieved by lowering Tj and or VGS Continuous current is limited by package. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 003aah405 100 03aa16 120 ID (A) Pder (%) 75 (1) 80 50 40 25 0 0 50 100 150 T mb (° C) 0 200 (1) Capped at 75A due to package Fig. 1. Continuous drain current as a function of mounting base temperature BUK9E8R5-40E Product data sheet Fig. 2. 0 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 11 September 2012 50 © NXP B.V. 2012. All rights reserved 3 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah406 102 IAL (A) 10 (1) (2) 1 (3) 10-1 10-3 Fig. 3. 10-2 10-1 1 t (ms) 10 AL Single pulse avalanche rating; avalanche current as a function of avalanche time 003aah407 103 ID (A) Limit RDSon= V DS / ID 10 2 tp =10 µ s 100 µ s 10 DC 1 ms 1 10 ms 100 ms 10-1 10-1 Fig. 4. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 1.56 K/W Rth(j-a) thermal resistance from junction to ambient vertical in still air - 65 - K/W BUK9E8R5-40E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 4 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah408 10 Zth(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0.05 10-1 0.02 single shot P tp T δ= 10-2 tp 10 -3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 t T 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 7. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.4 1.7 2.1 V - - 2.45 V 0.5 - - V VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 40 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 20 A; Tj = 25 °C; Fig. 11 - 6.4 8.1 mΩ VGS = 10 V; ID = 20 A; Tj = 25 °C; - 5.3 6.6 mΩ - - 15.6 mΩ Static characteristics V(BR)DSS VGS(th) Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 9 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11 VGS = 5 V; ID = 20 A; Tj = 175 °C; Fig. 12; Fig. 11 Dynamic characteristics QG(tot) QGS total gate charge ID = 20 A; VDS = 32 V; VGS = 5 V; - 20.9 - nC gate-source charge Fig. 13; Fig. 14 - 4.9 - nC BUK9E8R5-40E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 5 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Typ Max Unit QGD gate-drain charge - 7.3 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 1936 2600 pF Tj = 25 °C; Fig. 15 Coss output capacitance - 260 310 pF Crss reverse transfer capacitance - 142 190 pF td(on) turn-on delay time VDS = 30 V; RL = 1.5 Ω; VGS = 5 V; - 19 - ns tr rise time RG(ext) = 5 Ω - 27 - ns td(off) turn-off delay time - 36 - ns tf fall time - 21 - ns LD internal drain inductance from upper edge of drain mounting base to center of die - 2.5 - nH LS internal source inductance from source lead to source bonding pad - 7.5 - nH Source-drain diode VSD source-drain voltage IS = 20 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.85 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 20.8 - ns Qr recovered charge VDS = 25 V - 13.6 - nC 003aah364 180 5 VGS (V) =10 003aah260 15 4.5 RDSon (mΩ ) ID (A) 10 120 3.5 60 5 3 2.8 0 2.6 2.4 0 0.5 1 0 1.5 V (V) 2 DS Tj = 25 °C; tp = 300 μs Fig. 6. Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values BUK9E8R5-40E Product data sheet 0 5 7.5 VGS (V) 10 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 11 September 2012 2.5 © NXP B.V. 2012. All rights reserved 6 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah367 150 003aah025 3 VGS(th) (V) 2.5 ID (A) max 100 2 typ 1.5 Tj = 175 °C 50 min 1 Tj = 25 ° C 0.5 0 Fig. 8. 0 1 2 3 0 -60 4 V (V) 5 GS Transfer characteristics; drain current as a function of gate-source voltage; typical values 003aah026 10-1 Fig. 9. 120 2.6 2.8 3.5 3 min typ max 10 4.5 -4 5 5 10-5 10-6 180 15 10-3 10 Tj (° C) 003aah265 RDSon (mΩ ) 10-2 60 Gate-source threshold voltage as a function of junction temperature 20 ID (A) 0 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage BUK9E8R5-40E Product data sheet VGS (V) = 10 0 40 80 120 ID (A) 160 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 7 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 003aag820 2 VDS a ID 1.5 VGS(pl) VGS(th) 1 VGS QGS1 0.5 QGS2 QGS QGD QG(tot) 003aaa508 0 -60 0 60 120 Tj (°C) Fig. 13. Gate charge waveform definitions 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aah372 10 003aah268 104 V GS (V) C (pF) 8 14 V Ciss 6 103 4 VDS = 32 V Coss 2 Crss 0 0 10 20 30 QG (nC) 10 40 Fig. 14. Gate-source voltage as a function of gate charge; typical values BUK9E8R5-40E Product data sheet 2 10-1 1 10 V DS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 8 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 003aah374 160 IS (A) 120 80 0 Tj = 25 °C Tj = 175° C 40 0 0.5 1 VSD (V) 1.5 Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK9E8R5-40E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 9 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 8. Package outline Plastic single-ended package (I2PAK); low-profile 3-lead TO-262 SOT226 A A1 E D1 mounting base D L1 Q b1 L 1 2 3 b e c e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D max D1 E e L L1 Q mm 4.5 4.1 1.40 1.27 0.85 0.60 1.3 1.0 0.7 0.4 11 1.6 1.2 10.3 9.7 2.54 15.0 13.5 3.30 2.79 2.6 2.2 OUTLINE VERSION SOT226 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 06-02-14 09-08-25 TO-262 Fig. 17. Package outline I2PAK (SOT226) BUK9E8R5-40E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 10 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 9. Legal information 9.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Preview — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. 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NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. BUK9E8R5-40E Product data sheet Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 11 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK9E8R5-40E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 12 / 13 BUK9E8R5-40E NXP Semiconductors N-channel TrenchMOS logic level FET 10. Contents 1 1.1 1.2 1.3 1.4 Product profile ....................................................... 1 General description .............................................. 1 Features and benefits ...........................................1 Applications .......................................................... 1 Quick reference data ............................................ 1 2 Pinning information ............................................... 2 3 Ordering information ............................................. 2 4 Marking ................................................................... 2 5 Limiting values .......................................................2 6 Thermal characteristics .........................................4 7 Characteristics ....................................................... 5 8 Package outline ................................................... 10 9 9.1 9.2 9.3 9.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP B.V. 2012. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 September 2012 BUK9E8R5-40E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 13 / 13