Large-scale (512kbit) integration of Multilayer-ready Access-Devices based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield G. W. Burr, K. Virwani, R. S. Shenoy, A. Padilla, M. BrightSky† , E. A. Joseph† , M. Lofaro† , A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, C. T. Rettner, B. Jackson, D. S. Bethune, R. M. Shelby, T. Topuria, N. Arellano, P. M. Rice, B. N. Kurdi, and K. Gopalakrishnan IBM Almaden Research Center, 650 Harry Road, San Jose, CA 95120 († IBM T. J. Watson Research Center, Yorktown Heights, NY 10598) Tel: (408) 927–1512, Fax: (408) 927–2100, E-mail: [email protected] Abstract BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials[1-4] are integrated in large (512×1024) arrays at 100% yield, and are successfully co-integrated together with Phase Change Memory (PCM). Numerous desirable attributes are demonstrated: the large currents (>200µA) needed for PCM, the bipolar operation required for high-performance RRAM, the single-target sputter deposition essential for high-volume manufacturing, and the ultra-low leakage (< 10 pA) and high voltage margin (1.5V) needed to enable large crosspoint arrays. Keywords: Access device, MIEC, PCM, NVM, RRAM, MRAM ory devices (Fig.2(d)), fabricated using the keyhole-transfer method [5]. When tested in small arrays (5×10) immediately after completion of M1 wiring (Fig.7(a)), the large resistance change of PCM is readily evident above ∼500mV. While three of the 50 MIEC ADs have higher leakage, the three associated PCM devices could be placed in a permanent high-resistance state (Fig.7(b)) using reverse polarity pulses [6]. Thus singleton AD failures need not devastate future crosspoint array yield, at least with PCM. As shown in Fig. 8, endurance of integrated PCM+MIEC device pairs can exceed 100,000 cycles, despite the repeated application of RESET pulses >200µA and 5µs long SET pulses at ∼90µA. Introduction Large MIEC device arrays at 100% yield For PCM, RRAM, MRAM, or any other nonvolatile memory (NVM) to be as cost-effective as NAND FLASH (≤4F2 /3), 3Dstacking of large crosspoint arrays in the BEOL will be essential. Previously [1,2], we have shown that MIEC-based ADs exhibit the large ON/OFF ratios that enable these large crosspoint arrays (Fig. 1), with high voltage margin Vm (for which leakage stays below 10 nA), ultra-low leakage (< 10 pA), and high enough current densities even for PCM. In addition, these devices show bipolar diode-like characteristics, making them uniquely suited for stacking high-density MRAM and RRAM in the BEOL. MIEC AD demonstrations shown to date have been encouraging but at research-scale, with small (5×10) arrays of ADs integrated without any NVM. In this paper, we show that MIEC ADs support both processing temperatures up to 500◦ C and the singletarget sputter deposition needed in manufacturing, and demonstrate process improvements that provide both lower leakage and wider voltage margins. Furthermore, we demonstrate small device arrays with co-integrated MIEC and PCM devices, as well as large-scale (512kbit) arrays of integrated MIEC ADs at 100% yield. BEOL processing conditions (including temperatures and dielectrics) and AD electrodes were optimized for high array-yield and tight distributions. After optimized Cu-damascene M2 wiring (Fig.2(d)), bi-directional Array Diagnostic Monitor (ADM) arrays up to 512×1024 integrated MIEC ADs could be tested using integrated 1-bit sense-amplifiers and a fast electrical tester (Magnum 2EV, Fig. 9). Cumulative distribution functions (CDFs) of the bitline voltage VBL needed to produce various device currents Id can be combined to show the tightly distributed array I-V characteristics (Fig. 10). All 524,288 MIEC devices — 100% — had Vm > 1.1V, and 99.955% of ADs fell within ±150mV of the median voltage margin Vm =1.36V at 10nA (Fig. 11); these characteristics were uniform across the entire array (Fig. 12). In contrast, with the original, unoptimized electrode process, MIEC AD yield was significantly lower (91%), with numerous leaky devices and pronounced “edge effects” (Fig.13). MIEC device fabrication and process improvements All MIEC-based ADs presented here (Fig.2) are integrated on 8” wafers, using sputter-deposition of Cu-containing MIEC material into vias followed by an optimized CMP process [2] and a confined, non-ionizable TEC (Fig. 2(a)). Short-loop devices (Fig. 2(b)) have minimal wiring and are tested with ConductiveAFM. While our multi-target-capable PVD tool has allowed us to easily fabricate different MIEC materials [2], short-loop devices deposited from a single target, as required for volume manufacturing, show near-identical device characteristics (Fig.3). Cumulative post-fabrication anneals up to 500◦ C are also shown to have minimal effect on device yield, as measured over >1000 short-loop devices (Fig.4), providing a wide processing window. Process improvements developed in short-loop devices can be transferred to integrated 8” wafers containing small arrays of 180nm-node FETs (Fig. 2(c)). Fig. 5 illustrates the improvement in per-device leakage on an all-good array of 5×10 MIEC-based ADs after electrode optimization. While voltage margin Vm as measured at 10nA is effectively unchanged, the voltage windows at both 10pA and 100pA are markedly improved. Further process improvements have led to much larger voltage margins (Vm =1.5V), sufficient for PCM, RRAM, and MRAM (Fig.6). MIEC devices integrated with PCM MIEC-based ADs were also integrated immediately above ring-electrode mushroom-cell (CD∼35nm) Phase-Change Mem- 978-1-4673-0847-2/12/$31.00 ©2012 IEEE MIEC and RRAM While some RRAM devices can be made unipolar, large readwrite voltage margins and high endurance has required bipolar operation. Being inherently bipolar-capable, MIEC-based ADs offer the best of a very few paths for combining high-performance bipolar RRAM with Multi-Layer stacking. Conclusions BEOL-friendly access devices (AD) based on copper-containing MIEC materials [1-4] uniquely enable Multi-Layer CrosspointMemory Arrays, offering the large currents (>200µA) needed for PCM, the bipolar operation required for high-performance RRAM, the single-target sputter deposition essential to high-volume manufacturing, and the ultra-low leakage (< 10 pA) and high voltage margin (1.5V) needed for large crosspoint arrays. MIEC ADs were co-integrated successfully in small arrays with PCM, and were integrated in large (512×1024) arrays with 100% yield. Acknowledgements Expert analytical and processing support from D. Pearson, E. Delenia, L. Krupp, A. Friz, and the Microelectronics Research Laboratory (YKT) is gratefully acknowledged. References [1] K. Gopalakrishnan, VLSI 2010, T19-4 (2010). [2] R. Shenoy, VLSI 2011, T5B-1 (2011). [3] I. Yokota, J. Phys. Soc. Japan, 8(5), 595 (1953). [4] I. Riess, Solid State Ionics, 157, 1 (2003). [5] M. Breitwisch, VLSI 2007, T6B-3 (2007). [6] A. Padilla, J. Appl. Phys., 110(5), 054501, (2011). 2012 Symposium on VLSI Technology Digest of Technical Papers 41 a) Log Current IPROG/ERASE Selected Cell A ~10-100’s A N-1 VAD Diode AD VPROG/ERASE PCM NVM A V1 C Memory Required Element Vm [V] N-1 D V2 0 Voltage Margin @10nA PCM 1.4 – 1.6 MRAM 1.0 – 1.3 RRAM 1.4 – 1.7 1uA 1nA 100pA 100pA -0.2 0 0.2 0.4 0.6 0.8 0 -1 -0.2 -0.2 0 0.2 0.2 0.4 0.6 0.8 Fig. 3 Short-loop ADs show that Cu-containing MIEC material deposited from a single-target has identical (or even improved) I-V characteristics to our POR ADs (deposited from multiple targets). -0.2 0.2 TEC voltage [V] -0.6 -0.2 after 0.2 0.6 1.0 TEC voltage [V] 0 -1 -0.6 -0.2 0.2 10nA RESET 1nA 10pA 0.4 0.6 0.8 1 RESET 10nA 1nA Voltage [V] 100pA -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 -1.5 0.6 0.8 1mA 100 0 1 SET 50 0 2 4 Pulses RESET 1uA SET 100nA 10nA DC reads (660mV) DC leakage (±100mV) 1nA 100pA 10pA 10 100 Cycle 1k Sense Amplifier 0 0.5 1.0 10k 100k 1e-6 ID > Iref YES or NO? .99999 .99 .9 .5 .1 .01 30nA Row address selects one wordline 10nA -1.5 Sense .001 1e-4 1.6 300 400 median Vm = 1.36 V 1.4 Voltage Margin Vm 1.1 1.3 1.2 1.2 1.3 1.4 1.5 1.6 Fig. 11 Within this same 512×1024 array, there were no leaky devices; 100% of the array showed Vm > 1.1V. 99.955% of MIEC ADs had voltage margins Vm at 10nA within ±150mV of the median of 1.36V. 978-1-4673-0847-2/12/$31.00 ©2012 IEEE 0.001 0.0001 0.01 0.1 0.5 0.9 .99 .999 .99999 .9999 .999999 Voltage [V] -1 -0.5 0 0.5 1 1.5 0 Vm 100 1.6 1.5 300 400 1.4 1.3 600 700 1.2 800 900 1e-6 1e-5 500 800 1000 0 0.6 200 1.5 700 1e-5 1 Vm 600 Vm > 1.1V 0.4 Fig. 10 Array level I-V results across a 512×1024 array of integrated MIEC ADs show tight distributions. Cumulative distribution functions (CDFs) across bitline voltage VBL at various device currents Id are combined; by using 1024×1024 addresses, all 512×1024 MIEC ADs can be addressed in both polarities. 500 100% 0.2 100nA MIEC AD or AD + PCM 200 within ±150mV of median Vm .999 Voltage [V] 0 Current 100 99.955% .9999 -0.2 300nA 0 Occurrence -0.4 1uA Master Bitline (MBL) routed by column address Fig. 8 Endurance of an integrated PCM+MIEC deviceAmplifier pair to >100k cycles, with RESET currents >200µA Fig. 9 Integrated 1-bit sense-amplifiers and 5µs-long SET pulses (∼90µA). No AD degrada- allow a fast electrical tester (Magnum 2EV) tion had occurred at the time testing was terminated. to bi-directionally query ADM devices. .999999 1.5 Voltage [V] Device current ID 100uA 10uA -0.5 Bitline clamp voltage VBL 6 Time [us] -1.0 Reference current Iref Pulses 150 1.5 RESET 1nA RESET 200 1.0 R > 1M 100pA 250 SET DC reads Current [uA] 1uA 100nA 0.5 -0.6 Fig. 7 a) I-V characteristics for a 5×10 macro of MIEC ADs stacked on PCM. Switching between SET and RESET does not degrade the ADs, but three ADs are noticeably leaky. Leaky ADs would adversely affect all device-pairs on the same row and column in any future crosspoint array; even a handful would greatly decrease array-yield. Reverse polarity pulses can intentionally damage only the PCM devices in series with leaky ADs [6], leaving those PCM+MIEC device pairs in an high resistance state (b) and eliminating the amplification effect of singleton AD failures. Leaky ADs + high-R PCM 10nA Fig. 6 I-V characteristics show voltage margins Vm =1.50V (at 10nA) for short-loop ADs fabricated with extensive process improvements. 0 Iread ~ 100x 100nA Voltage [V] 0.2 -0.5 SET 1uA 0 1.0 Optimized BEC Fig. 5 Slow measurements on entire all–good arrays of ∼50 integrated MIEC ADs reveal that already-low leakage currents can be further suppressed through electrode optimization. Iread ~ 100x -1.0 b) Current -0.2 1pA Voltage [V] -1.5 100pA -0.4 10pA R > 1M Leaky ADs 100pA 1nA -0.6 0.6 Original BEC [2] 1nA 100pA 100fA Fig. 4 Cumulative distributions of Vm over >1000 short-loop MIEC-based ADs after successive high-temperature anneals. SET 10nA 100nA 1pA via 100nA anneal 600 200 Vm = 1.50V -0.8 1.0 500oC 800 200 Current a) 1uA -1 0.6 # devices anneal 10nA Current -0.6 1000 400oC 0 -1 TEC voltage [V] 0 -1 400 1uA Current 1.0 400 Current 100nA 0.6 after 800 Voltage [V] -0.4 200 TEC voltage [V] -0.6 600 -0.6 400 Va # devices Vm=1.25V @ 10nA -0.8 ILD 1uA anneal 600 Vm= Va + |Vb| Vb 200 after 450oC 800 anneal 600 10pA 1pA PCM # devices 350oC 1000 Current 1nA BEC via FET via 1000 after 800 Single-target deposition 100nA 10nA -0.4 TEC MIEC oxide # devices 400 -0.6 M1 via Vm=1.14V @ 10nA -0.8 BEC FET Fig. 2 MIEC-based ADs are integrated on 8” wafers, with MIEC material sputter-deposited into vias followed by an optimized CMP process[2] and a confined, non-ionizable TEC (a). Short-loop devices (b) have minimal wiring and are tested with Conductive-AFM, while integrated 180nm FETs allow (c) small (5×10) arrays of MIEC ADs to be tested. Mushroom-cell PCM devices with ∼35nm CD heater electrodes (d) were integrated with the keyhole-transfer method [5], followed by the MIEC AD. Completion of (d) dual-damascene copper M2 wiring allowed testing of large Array Diagnostic Monitor (ADM) arrays up to 512×1024 in size, either with or without PCM. Voltage [V] 1uA V1 Si wafer 1000 10pA 1pA via M2 MIEC VAD Multi-target (POR) deposition Current 10nA via BEC d) TEC ILD MIEC ILD BEC Fig. 1 In an NVM crosspoint array, the Access Device (AD) must supply high current for program/erase of a selected cell yet low-leakage for all other cells, including those half-selected. A voltage margin Vm of 1.5V would be sufficient for PCM, RRAM, and MRAM. 100nA M1 TEC MIEC B C Half-selected cells Vm Non-selected cells D TEC B c) C-AFM tip Current [per device] V TOT VTOT b) 100 200 300 400 500 1.1 900 1.0 1000 0 Fig. 12 After the BEOL processing conditions and AD electrodes were optimized, voltage margins Vm were uniformly distributed across the entire 512×1024 array of MIEC ADs, with no “edge effects.” 1.1 50 100 150 200 250 1.0 Fig. 13 In contrast, with the original, unoptimized process (on a 256×1024 array), MIEC AD yield was significantly lower (91%), with numerous leaky devices and pronounced “edge effects.” The non-responsive bitlines seen here are not related to the MIEC process. 2012 Symposium on VLSI Technology Digest of Technical Papers 42