MIEC* Access Device for 3D-Crosspoint Nonvolatile Memory Arrays IBM Almaden Research Center, San Jose, CA * Mixed-Ionic-Electronic-Conduction © 2012 IBM Corporation Storage Class Memory (SCM) • Solid-state no moving parts • Nonvolatile retains data on power-off • Fast access speed approaching DRAM • High endurance many program/erase cycles • Low cost per bit approaching hard disk A new class of storage/memory devices that blurs the distinction between … Memory (fast, expensive, volatile) and Storage (slow, cheap, nonvolatile) (Wilcke, USENIX FAST tutorial, 2009) 2 © 2012 IBM Corporation 3D multi-layer crosspoint memory array As a result of the cost-basis of semiconductor manufacturing, memory cost is inversely related to bit density (adapted from Burr, EIPBN 2008) Stack ‘L’ layers in 3D Effective cell size: 4F2 F = minimum litho. feature size Effective cell size: 4F2/L Since they effectively store more bits per 4F2 footprint, 3D crosspoint (XPT) arrays path to low cost memory 3 © 2012 IBM Corporation Nonvolatile Memory (NVM) candidates • NAND Flash - very dense ( low bit cost) - currently at sub-20nm, but - endurance/retention get worse as scaling limits approached • Phase Change Memory (PCM) • Magnetic RAM (MRAM) - Spin-Torque-Transfer (STTRAM) arrays - Racetrack • Resistive RAM (RRAM) - Oxide-based, or - Solid-electrolyte Conductive-Bridge RAM Several NVM technology options for SCM 4 © 2012 IBM Corporation Phase Change Memory (PCM) SET (heat to crystallize) Top Electrode (TE) crystalline amorphous Bottom Electrode (BE) Dielectric RESET state High Resistance Top Electrode (TE) crystalline RESET (melt + quench) (Burr et al, JVST B 2010) SET state Low Resistance • Mature (for emerging NVM) • Multiple-Level Cell capable • Scalable • Resistance drift • High reset current (density) ~10 MA/cm2 needed even for scaled PCM 5 © 2012 IBM Corporation Resistive RAM (RRAM) “Forming” step Top electrode insulator (Burr: CMOS ET 2011) Bot. electrode Conductive filament RESET High resistance V and I-driven creation & removal of conducting regions in insulator • Simple cell structure, usually fab-friendly • Low programming current (~10-100uA) • Good high temperature retention • High speed switching (sub-ns shown) • High endurance • Less mature (limited large array studies) • Intra- and inter-device variability 6 Based on O-vacancy motion • TiN / HfOx/TiOx / TiN H.Y. Lee et al, IEDM 2008, 2009, 2010 (ITRI) • Pt / TaOx/ Pt SET Low resistance RRAM examples Z. Wei et al, IEDM 2008 (Panasonic) Based on metal ion motion • W / AgGeS / Ag M.N. Kozicki et al, NVMTS 2005 (Arizona State Univ.) Typically, the best RRAM devices have SET and RESET voltages of opposite polarity The best RRAM candidates require bipolar operation © 2012 IBM Corporation Need for access device V Memory Element (PCM, RRAM etc.) Access Device (Selector) Sense I Current ‘sneak path’ problem Access device needed in series with memory element • Cut off current ‘sneak paths’ that lead to incorrect sensing and wasted power • Typically diodes (rectifiers) used as access devices • Could also use devices with highly non-linear I-V curves 7 © 2012 IBM Corporation Access device wish list - 3D XPT memory • High ON-state current density >10 MA/cm2 for PCM RESET Slightly lower (~MA/cm2) for RRAM • Low OFF-state leakage current >107 ON/OFF ratio, and wide low-leakage voltage zone to accommodate half-selected cells in large arrays • Back-End process compatible <400C processing to allow 3D stacking • Bipolar operation needed for optimum RRAM operation IBM’s MIEC-based access device satisfies all these criteria 8 © 2012 IBM Corporation • Basic characteristics • Switching speed • Cycling endurance • Scalability 9 © 2012 IBM Corporation MIEC device operation Top Electrode (TE) MIEC Cu+ Ion Motion Bottom Electrode (BE) Cu-containing Mixed Ionic-Electronic Conduction† (MIEC) materials: • Mobile Cu transport in E-field • Cu interstitials/vacancies can act as dopants relationship between mobile Cu and local electron/hole concentration Voltage applied to electrodes leads to … • transient Cu ion drift, followed by • steady-state electron/hole current Our devices: BE inert (eg. W, TiN) †Ref: I. Riess, Solid State Ionics, 157, 1 (2003) TE inert or ionizable for an overview of MIEC models MIEC can be deposited @ ~200C Exploit non-linear I-V relationship in MIEC devices for selector functionality 10 (Gopalakrishnan et al, 2010 VLSI Tech. Sym.) © 2012 IBM Corporation Wide-area TEC device – DC sweeps 10A VB |Current| 1A VA (-0.355V) (0.255V) 100nA Voltage margin 10nA |VB| + VA 1nA (0.61V) 100pA 10pA ~80 nm BEC ionizable TEC -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 Applied TEC voltage [V] Exponential DC I-V curve for negative TEC bias 11 (Gopalakrishnan et al, 2010 VLSI Tech. Sym.) © 2012 IBM Corporation Arbitrary Waveform Generator Voltage [V] 1.6 Rs ~3k 1.2 ~ 200 A 15 MA/cm2 Voltage [V] High current-density capable 0.8 DUT 0.4 ~40 nm BEC ionizable TEC 0 0 1 2 3 4 Time [sec] Turn-on speeds and their temp. dependence suggest ionic transport Time [sec] MIEC-based access device can deliver high current pulses 12 (Gopalakrishnan et al, 2010 VLSI Tech. Sym.) © 2012 IBM Corporation Bipolar I-V curves TEC MIEC (Gopalakrishnan et al, 2010 VLSI Tech. Sym.) 100A 10A 1A overlap 10A 100nA 10nA 1nA 100pA Applied Voltage 10pA 10nA 1nA 100pA -0.5 -0.3 -0.1 0.1 0.3 0.5 200nm inert TEC 10pA 80nm BEC [V] 1pA ILD 1A gap 100nA 100A |Current| |Current| W=200nm Gap=100nm Overlap=250nm W BEC poly-Si series resistor 1pA -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 Voltage [V] Lateral (bridge) device Vertical device with scaled TEC • Similar TEC and BEC areas, along with reduced MIEC volume eliminates abrupt ‘filamentary’ switching symmetric I-V curves • Suitable (desirable) for bipolar memory elements such as RRAM MIEC access devices can operate in both polarities 13 © 2012 IBM Corporation Integration into 200 mm wafer process 180 nm CMOS Front-End 1T1S (1 transistor + 1 selector) As-deposited TEM x-section Post-CMP CMP process for MIEC material with modified commercial Cu slurry self-aligned MIEC Diode-in-Via (DIV) in a 200 mm process 14 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation DIV – Low leakage current ~10 pA leakage currents near 0V & wide range with <100pA 15 (Burr et al, 2012 VLSI Tech. Sym.) (Virwani et al, 2012 IEDM) © 2012 IBM Corporation DIV – High current capable Pulse generator V t Current 50 Scope t 100’s of uA pulse currents ON/OFF ratio >107 16 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation DIV – Small array characterization 5x10 arrays of FETconnected DIVs • Voltage margin (Vm) ~1.1V • Low inter-device variability Integrated small arrays of MIEC DIVs with high yield 17 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation Large array integration 100% yield and tight distributions in 512 kbit 1T-1S array 18 (Burr et al, 2012 VLSI Tech. Sym.) © 2012 IBM Corporation MIEC + PCM integrated on 200mm process Demonstrated > 105 cycles of PCM SET/RESET through stacked MIEC access device 19 (Burr et al, 2012 VLSI Tech. Sym.) © 2012 IBM Corporation • Basic characteristics • Switching speed • Cycling endurance • Scalability 20 © 2012 IBM Corporation Switching speed at high currents (WRITE) 500 400 Current [uA] 15ns 5 ns/division 300 200 Increasing pulse amplitude a) 100 0 21 Read Current @660mV (Virwani et al, IEDM 2012) Time 1uA post-SET 300nA PostRESET 100nA 30nA 100 RESET current [uA] 150 200 300 400 MIEC access device can supply >150uA in 15ns … … sufficient to RESET PCM © 2012 IBM Corporation Switching speed at low currents (READ) MIEC 1T-1S array structures with integrated sense amplifiers (SA) (Virwani et al, IEDM 2012) Turn-on is slower at low currents …. … but pulse shaping and overvoltage can be used to accelerate NVM READ MIEC access device can drive ~5uA in <<1us 22 © 2012 IBM Corporation • Basic characteristics • Switching speed • Cycling endurance • Scalability 23 © 2012 IBM Corporation Cycling endurance – low current ON current >5A 100A sufficient for PCM-read (Rs~30k Vapplied~ -0.8V) |Current| 10A 80 nm BEC Wide-area ionizable TEC 1A Pulse duration ~2s 100nA OFF current at -0.3V 10nA 1nA OFF current at -0.2V 100pA 100 1000 104 105 106 107 108 109 1010 Testing time-limited! Pulses Low current (memory READ) endurance > 1010 cycles 24 (Gopalakrishnan et al, 2010 VLSI Tech. Sym.) © 2012 IBM Corporation Cycling endurance – high current DC I-V curves monitored in between 100uA pulses After many cycles … Leakage current rises … … and voltage margin shrinks Finite high current (memory WRITE) endurance 25 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation Cycling endurance trends Endurance depends inversely on current (exponential) and pulse duration 26 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation Cycling endurance trends (continued) >108 endurance for sub-45 nm-node PCM! ( IRESET < 150 A ) Expect even higher MIEC endurance for RRAM (IPROG/ERASE <100uA) Strong current-dependence of MIEC access device endurance persists across many different device structures 27 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation Cycling failure analysis TEM/EELS local stoichiometry Before cycling BEC CD ~ 80 nm Wide area TEC After cycling 425,000 cycles @ 325 A negative voltage on TEC MIEC endurance failure is related to Cu accumulation 28 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation Cycling failure recovery Endurance failure correctable by annealing and/or voltage pulses 29 (Shenoy et al, 2011 VLSI Tech. Sym.) © 2012 IBM Corporation • Basic characteristics • Switching speed • Cycling endurance • Scalability 30 © 2012 IBM Corporation Conductive AFM device characterization Large thermal process budget window Manufacturable deposition Short loop process flows on relevant structures Rapid learning cycles enabled by cAFM 31 (Burr et al, 2012 VLSI Tech. Sym.) Process optimization for ©higher Vm 2012 IBM Corporation Lateral scaling – BEC size Wide-area Ionizable TEC 1m 10A 1A Via height: 20nm 250nm Vbias -0.50V 40nm 80nm 10nA 1.6 1nA 100pA 10pA Voltage [V] |Current| 100nA -0.35V -0.30V -0.25V 1.2 0.8 Via height: 40nm 1000 104 19 nm 0.4 Time [ns] 0 0 105 200 2 400 600 800 106 Via area = CD [nm2] Current scales well with BEC size over several orders of magnitude Suggests non-filamentary nature of operation mechanism 32 (Gopalakrishnan et al, 2010 VLSI Tech. Sym.) © 2012 IBM Corporation Lateral scaling – TEC size (1) Voltage margin increased with smaller TEC CD (Virwani et al, 2012 IEDM) Consistent with trend seen on earlier devices (Shenoy et al, 2011 VLSI Tech. Sym.) Selector functionality is maintained in fully confined MIEC devices with reduced TEC and BEC size 33 © 2012 IBM Corporation Lateral scaling – TEC size (2) (Virwani et al, 2012 IEDM) Ultra-scaled MIEC access devices can still deliver >100uA pulse currents in both polarities 34 © 2012 IBM Corporation Lateral scaling – TEC size (3) Sub-30nm lateral CD MIEC device (Virwani et al, 2012 IEDM) No lower limit to lateral scaling has been found so far 35 © 2012 IBM Corporation Thickness scaling trends C-AFM tip TEC SiN MIEC dmin BEC oxide Si wafer Cumulative distribution plots of 10nA MIEC voltage margin MIEC devices are well behaved down to 12nm minimum inter-electrode distance (dmin) 36 (Virwani et al, 2012 IEDM) © 2012 IBM Corporation Thickness scaling – Failure Analysis (1) (Virwani et al, 2012 IEDM) 37 Start to see some failures in arrays of MIEC devices with dmin ~12nm Leakage current increases © 2012 IBM Corporation Thickness scaling – Failure Analysis (2) (Virwani et al, 2012 IEDM) Good Bad Good Use TEM to correlate device failures to MIEC thickness 38 Lower limit seen for thickness scaling of this MIEC access device © 2012 IBM Corporation Summary Symmetric MIEC access devices with “bipolar” device characteristics are uniquely suitable for crosspoint RRAM, yet have sufficient current for PCM as well ... versatile selector for non-volatile memory arrays MIEC devices can be deposited and processed at BEOL temperatures (and also survive 500C process) ...suitable for 3D multilayer stacking MIEC device functionality demonstrated down to sub-30 nm CD, and voltage margin is preserved down to at ~11 nm thickness ...scalable Ultra high current density obtained in pulsed mode for MIEC devices > 50 MA/cm2 @ 20 nm CD – ample current to drive either RRAM or PCM. MIEC devices have very low leakage ~10pA near 0V …ON/OFF ratio > 107 Turn-on speed ~15ns at WRITE-level (150uA) current and <<1us at READ-level current (5uA) … high speed operation MIEC device cycling endurance > 108 cycles shown @ sub 150 A current. Endurance improves exponentially at lower currents … high endurance MIEC process demonstrated with 100% yields and low variability on 0.5 Mbit array ... bodes well for manufacturability 39 © 2012 IBM Corporation Acknowledgements – Team members IBM Almaden Geoffrey Burr, Rohit Shenoy, Kumar Virwani, Alvaro Padilla, Andrew Kellock, Charles Rettner, Donald Bethune, Robert Shelby, Khanh Nguyen, Amy Bowers, Mark Jurich, Robin King, Dean Pearson, Noel Arellano, Alexander Friz TEM Group: Philip Rice, Teya Topuria, Leslie Krupp, Eugene Delenia IBM Yorktown Kailash Gopalakrishnan, Gloria Ho, Matthew BrightSky, Eric Joseph, Michael Lofaro, Simone Raoux, Jing Li, Ravi Dasaka IBM India (SRDC: Semiconductor Research Development Center) Karthik Venkataraman, Rajan Pandey, Kota Murali Management Support Bulent Kurdi, Chung Lam, Winfried Wilcke, Chandrasekhar Narayan, Tze-Chiang Chen IBM Yorktown MRL Fabrication Line support 40 © 2012 IBM Corporation References K. Virwani, G. W. Burr, R. S. Shenoy, C. T. Rettner, A. Padilla, T. Topuria, P. M. Rice, G. Ho, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and K. Gopalakrishnan, "Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on Mixed-Ionic-ElectronicConduction (MIEC) Materials," 2012 IEEE International Electron Devices Meeting (IEDM 2012), T2.7, Dec 2012. G. W. Burr, K. Virwani, R. S. Shenoy, A. Padilla, M. BrightSky, E. A. Joseph, M. Lofaro, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, C. T. Rettner, B. Jackson, D. S. Bethune, R. M. Shelby, T. Topuria, N. Arellano, P. M. Rice, B. N. Kurdi, and K. Gopalakrishnan, "Large-scale (512kbit) integration of Multilayer-ready Access-Devices based on Mixed-Ionic-ElectronicConduction (MIEC) at 100% yield," 2012 Symposium on VLSI Technology, T5-4, June 2012. R. S. Shenoy, K. Gopalakrishnan, B. Jackson, K. Virwani, G. W. Burr, C. T. Rettner, A. Padilla, D. S. Bethune, R. M. Shelby, A. J. Kellock, M. Breitwisch, E. A. Joseph, R. Dasaka, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, "Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint-Memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials," 2011 Symposium on VLSI Technology, T5B-1, June 2011. G. W. Burr, "Storage Class Memory," 2011 CMOS Emerging Technologies, June 2011. K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, K. Virwani, D. S. Bethune, R. M. Shelby, G. W. Burr, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, "Highly-Scalable Novel Access Device based on Mixed Ionic Electronic Conduction (MIEC) Materials for High Density Phase Change Memory (PCM) Arrays," 2010 Symposium on VLSI Technology, 19.4, June 2010. G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, B. Rajendran, S. Raoux, and R. Shenoy, “Phase change memory technology," Journal of Vacuum Science & Technology B, 28(2), 223-262 (2010). Richard Freitas, Winfried Wilcke, Bülent Kurdi, and Geoffrey Burr, “Storage Class Memory, Technology, and Uses,” Tutorial T3, 7th USENIX Conference on File and Storage Technologies (FAST’09), February 2009. G. W. Burr, K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, and B. N. Kurdi, “Storage Class Memory,” EIPBN 2008 --- The 52nd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, May 2008. 41 © 2012 IBM Corporation