SCMandMIEC_overview_12Feb2013

Towards Storage
Class Memory:
3-D crosspoint access devices
using Mixed-Ionic-ElectronicConduction (MIEC)
Geoffrey W. Burr
Research – Almaden
February 12, 2013
[email protected]
Towards SCM: 3-D crosspoint access devices using MIEC
Computational
Electromagnetics
2013
2012
2011
2010
2009
2008
2007
2006
2005
2004
2003
2002
RSM
Joined IBM
Almaden
2001
Phase-change
& Storage class
memory
photon
echoes
Geoffrey W. Burr
2000
1999
1998
1997
Caltech
1996
1995
1994
Holographic
Data Storage
1993
1992
1991
2
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Outline
 Motivation
• future server-room power & space demands may require
a new technology – Storage Class Memory (SCM) – combining…
 the benefits of a solid-state memory (high performance and robustness)
 the archival capabilities and low cost of conventional HDD
 3-D Crosspoint memory
• High-density, high-performance Non-Volatile Memory (NVM)
 STT-MRAM, RRAM, PCM
• Back-End-Of-the-Line (BEOL)-compatible access device
 High ON-state current for writing (>10MA/cm2)
 Low OFF-state leakage (<100pA  >107 ON/OFF ratio)
 Bipolar operation (for RRAM or STT-MRAM)
 Access Device based on Mixed-Ionic-Electronic-Conduction
 Conclusion
• With its combination of low-cost and high-performance,
SCM could impact much more than just the server-room...
3
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Power & space in the server room
The cache/memory/storage hierarchy is rapidly becoming the bottleneck for large systems.
We know how to create MIPS & MFLOPS cheaply and in abundance,
but feeding them with data has become
the performance-limiting and most-expensive part of a system (in both $ and Watts).
Extrapolation to 2020
(at 70% CGR  need
2 GIOP/sec)
•5
million HDD
 16,500 sq. ft. !!
 22 Megawatts
R. Freitas and W. Wilcke, Storage Class Memory: the next storage
system technology –"Storage Technologies & Systems" special issue
of the IBM Journal of R&D (2008)
4
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
…yet critical applications are also undergoing a paradigm shift
Compute-centric
Data-centric
paradigm
paradigm
Main Focus: Solve differential equations
Analyze petabytes of data
Bottleneck: CPU / Memory
Storage & I/O
Typical Examples:
Computational Fluid Dynamics
Search and Mining
Finite Element Analysis
Analyses of social/terrorist networks
Multi-body Simulations
Sensor network processing
Digital media creation/transmission
Environmental & economic modeling
Extrapolation
to 2020
[Freitas:2008]
5
(at 90% CGR  need 1.7 PB/sec)
(at 90% CGR  need 8.4G SIO/sec)
• 5.6 million HDD
 19,000 sq. ft. !!
 25 Megawatts
Geoffrey W. Burr
IBM Research – Almaden
• 21 million HDD
 70,000 sq. ft. !!
 93 Megawatts
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Problem (& opportunity): The access-time gap between memory & storage
...(in human
perspective)
(T x 109)
Access time...
(in ns)
Decreasing
co$t
ON-chip
memory
1
10
CPU operations (1ns)
Get data from L2 cache (<5ns)
Get data from DRAM/SCM (60ns)
second
minute
OFF-chip
memory
100
ON-line
storage
104
105
day
OFF-line
storage
106
week
103
107
CPU
RAM
hour
Read or write to DISK (5ms)
month
year
108
DISK
decade
109
1010
Yesteryear
century
Get data from TAPE (40s)
millenium
TAPE
• Modern computer systems have long had to be designed around hiding the access gap
between memory and storage  caching, threads, predictive branching, etc.
• “Human perspective” – if a CPU instruction is analogous to a 1-second decision by a human,
retrieval of data from off-line tape represents an analogous delay of 1250 years
6
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Problem (& opportunity): The access-time gap between memory & storage
Access time...
(in ns)
Decreasing
co$t
ON-chip
memory
1
10
OFF-chip
memory
100
ON-line
storage
104
OFF-line
storage
106
103
Yesteryear
CPU operations (1ns)
Get data from L2 cache (<5ns)
Get data from DRAM/SCM (60ns)
Memory/storage gap
CPU
RAM
Read a FLASH device (20 us)
107
108
CPU
RAM
FLASH
SSD
105
Write to FLASH, random (1ms)
Read or write to DISK (5ms)
Today
DISK
DISK
TAPE
TAPE
109
1010
Get data from TAPE (40s)
• Today, Solid-State Disks based on NAND Flash can offer fast ON-line storage,
and storage capacities are increasing as devices scale down to smaller dimensions…
…but while prices are dropping, the performance gap between memory and storage
remains significant, and the already-poor device endurance of Flash is getting worse.
7
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Problem (& opportunity): The access-time gap between memory & storage
Access time...
(in ns)
Decreasing
co$t
ON-chip
memory
1
10
OFF-chip
memory
100
ON-line
storage
104
OFF-line
storage
106
103
Near-future
CPU operations (1ns)
Get data from L2 cache (<5ns)
Get data from DRAM/SCM (60ns)
Memory/storage gap
Read a FLASH device (20 us)
105
107
Write to FLASH, random (1ms)
Read or write to DISK (5ms)
108
CPU
RAM
SCM
DISK
109
1010
Get data from TAPE (40s)
TAPE
Research into new solid-state non-volatile memory candidates
– originally motivated by finding a “successor” for NAND Flash –
has opened up several interesting ways to change the memory/storage hierarchy…
1) Embedded Non-Volatile Memory – low-density, fast ON-chip NVM
2) Embedded Storage – low density, slower ON-chip storage
3) M-type Storage Class Memory – high-density, fast OFF- (or ON*)-chip NVM
4) S-type Storage Class Memory – high-density, very-near-ON-line storage
* ON-chip using 3-D packaging
8
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
M-type: Synchronous
S-type vs. M-type SCM
CPU
I/O
Controller
Internal
DRAM
Memory
Controller
Hardware managed
Low overhead
Processor waits
New NVM  not Flash
Cached or pooled memory
Persistence (data survives despite
requires
redundancy in system architecture
component failure or loss of power)
SCM
~1us read latency
SCM
Storage
Controller
External
9
•
•
•
•
•
•
Geoffrey W. Burr
SCM
Disk
S-type: Asynchronous
• Software managed
• High overhead
• Processor doesn’t wait,
(process-, thread-switching)
• Flash or new NVM
• Paging or storage
• Persistence  RAID
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Storage-type vs. memory-type Storage Class Memory
Speed (Latency & Bandwidth)
Read Latency
100ms
10ms
NAND Storage-type
uses
Cost/bit
1ms
Memory-type
uses
Power!
(Write)
Endurance
2
4F
FF
DRAM
100ns
10ns
Cell size [F2]
2
4
low co$t
6
8
10
The cost basis of semiconductor processing is well understood – the paths to higher density are
1) shrinking the minimum lithographic pitch F, and 2) storing more bits PER 4F2
10
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Cost structure of silicon-based technology
$100k / GB
Co$t determined by
 cost per wafer
 # of dies/wafer
 memory area
per die [sq. mm]
 memory density
[bits per
4F2]
$10k / GB
NAND
$1k / GB
DRAM
$100 / GB
$10 / GB
Desktop
HDD
$1 / GB
 patterning density $0.10 / GB
Enterprise
HDD
[sq. mm per 4F2]
$0.01 / GB
1990
11
Geoffrey W. Burr
1995
2000
2005
2010
2015
Chart courtesy of Dr. Chung Lam, IBM Research
IBM Research – Almaden
February
12,
IBM Journal
R&D2013
article
updated version of plot from 2008
Towards SCM: 3-D crosspoint access devices using MIEC
Storage Class Memory  need 3-D crosspoint arrays
Cost
SRAM
DRAM
NOR FLASH
NAND FLASH
HDD
STORAGE
CLASS
MEMORY
Performance
12
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Outline
 Motivation
• future server-room power & space demands may require
a new technology – Storage Class Memory (SCM) – combining…
 the benefits of a solid-state memory (high performance and robustness)
 the archival capabilities and low cost of conventional HDD
 3-D Crosspoint memory
• High-density, high-performance Non-Volatile Memory (NVM)
 STT-MRAM, RRAM, PCM
• Back-End-Of-the-Line (BEOL)-compatible access device
 High ON-state current for writing (>10MA/cm2)
 Low OFF-state leakage (<100pA  >107 ON/OFF ratio)
 Bipolar operation (for RRAM or STT-MRAM)
 Access Device based on Mixed-Ionic-Electronic-Conduction
 Conclusion
• With its combination of low-cost and high-performance,
SCM could impact much more than just the server-room...
13
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Storage Class Memory at IBM Almaden
2004
IEDM
IBM/Macronix/
2006
Qimonda
Joint Project 2005
begins
2006
IEDM 2007
2007
2008
VLSI 2007
2009
IEDM 2010
2010
Science 2009
JAP 2012
(MRS 2013)
2011
2012
14
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Storage Class Memory at IBM Almaden
2004
IEDM
IBM/Macronix/
2006
Qimonda
Joint Project 2005
begins
2006
IEDM 2007
2007
2008
VLSI 2007
2009
IEDM 2010
2010 VLSI 2012
VLSI 2010
2011
VLSI 2011
2012
IEDM
2012
15
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Ingredients of crosspoint memory
1) NVM element
• Improved FLASH
• Magnetic Spin Torque Transfer
 STT-RAM
 Magnetic Racetrack
• Phase Change RAM
• Resistive RAM
2) High-density access device (A.D.)
• 2-D – silicon transistor or diode
• 3-D  higher density per 4F2
• polysilicon diode (but <400oC processing?)
• MIEC A.D. (Mixed Ionic-Electronic Conduction)
• OTS A.D. (Ovonic Threshold Switch)
NVM memory element
plus access device
Generic SCM Array
• Conductive oxide tunnel barrier A.D.
16
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Limitations of Flash
100000
Asymmetric performance
Writes much slower than reads
IOPS
10000
Program/erase cycle
Block-based, no write-in-place
10000
3000
2000
52000
17000
1000
49
100
Data retention and Non-volatility
Retention gets worse as Flash scales down
10
USB disk
LapTop
Maximum Random Read IOPs
Enterprise
Maximum Random Write IOPs
Endurance
• Single level cell (SLC)  105 writes/cell
1000
• Multi level cell (MLC)  104 writes/cell
Future outlook
60
100
MB/s
• Triple level cell (TLC)  ~300 writes/cell
200
100
40
17
10
7
• Scaling focussed solely on density
• 3-D schemes exist but are complex
1
USB disk
Sustained Read Bandwidth
17
Geoffrey W. Burr
IBM Research – Almaden
LapTop
Enterprise
Sustained Write Bandwidth
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
STT (Spin-Torque-Transfer) RAM
• Controlled switching of free magnetic layer in a
magnetic tunnel junction using current, leading to
two distinct resistance states
Plate Line
Strengths
Word Line
• Inherently very fast  almost as fast as DRAM
• Much better endurance than Flash or PCM
• Radiation-tolerant
• Materials are Back-End-Of-the-Line compatible
• Simple cell structure  reduced processing costs
Bit Line
Weaknesses
•
•
•
•
•
Achieving low switching current/power is not easy
BEOL temperatures can affect STT-MRAM device stack
Resistance contrast is quite low (2-3x)  achieving tight distributions is ultra-critical
High-temperature retention strongly affected by scaling below F~50nm
Tradeoff between fastest switching and switching reliability
Outlook:
Strong outlook for an Embedded Non-Volatile Memory to replace/augment DRAM.
While near-term prospects for high-density SCM with
STT-RAM may seem dim, Racetrack Memory offers hope
for using STT concepts to create vertical “shift-register” of
domain walls  potential densities of 10-100 bits/F2
18
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Phase-change RAM
Phase Change Material
• Switching between low-resistance crystalline,
and high-resistance amorphous phases, controlled
through power & duration of electrical pulses
Strengths
word line
insulator
‘heater’
wire
• Very mature (large-scale demos & products)
bit
• Industry consensus on material  GeSbTe or GST
access device
line
• Large resistance contrast  analog states for MLC
• Offers much better endurance than Flash
• Shown to be highly scalable (still works at ultra-small F) and Back-End-Of-the-Line compatible
• Can be very fast (depending on material & doping)
Weaknesses
• RESET step to high resistance requires melting  power-hungry, thermal crosstalk?
To keep switching power down  sub-lithographic feature and high-current Access Device
To fill small feature  ALD or CVD  difficult now to replace GST with a better material
Variability in small features broadens resistance distributions
• 10-year retention at elevated temperatures can be an issue  recrystallization
• Device characteristics change over time due to elemental segregation  device failure
• MLC strongly affected by relaxation of amorphous phase  “resistance drift”
Outlook:
19
NOR-replacement products now shipping  if yield-learning successful and MLC
drift-mitigation and/or 3-D Access Devices can offer high-density (=low-cost), then
opportunity
for NAND
S-type,– and
then finally M-typeFebruary
SCM may
follow
Geoffrey
W. Burrreplacement,
IBM Research
Almaden
12,
2013
Towards SCM: 3-D crosspoint access devices using MIEC
Resistive RAM
Strengths
•
•
•
•
•
•
•
•
Voltage-controlled formation & dissipation of an oxygen-vacancy
(or metallic) filament through an otherwise insulating layer
Good retention at elevated-temperatures
Simple cell structure  reduced processing costs
Both fast and ultra-low-current switching have been demonstrated
Some RRAM materials are Back-End-Of-the-Line compatible
Relatively new field  high hopes for improved material concepts
Less “gating” Intellectual Property to license
Some RRAM concepts offer co-integrated NVM & Access Device
Numerous ongoing development efforts
Top electrode
“Forming”
step
oxide
Bottom electrode
RESET
Conductive
filament
SET
Weaknesses
•
•
•
•
•
•
Highly immature technology – wide variation in materials hampers cross-industry learning
Demonstrated endurance is slightly better than Flash, but lower than PCM or STT-RAM
Switching reliability an issue, even within single devices, and read disturb can be an issue
An initial high-voltage “forming” step is often required
To attain low RESET switching currents, circuit must constrain current during previous SET
Unipolar and bipolar versions – bipolar typically better in both write margins & endurance,
but then requires an unconventional bipolar-capable Access Device (transistor or diode is out)
• High array yield with minimal “outlier” devices not yet demonstrated
• Tradeoff between switching speed, long-term retention, and reliability not yet explored
Outlook:
20
Outlook is unclear. Emergence of a strong material candidate offering high array
yield & reliability could focus industry efforts considerably. Absent that, many
uncertainties
remain
about prospects
for reliable
storage & memory
products.
Geoffrey
W. Burr
IBM Research
– Almaden
February
12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Ingredients of crosspoint memory
1) NVM element
• Improved FLASH
• Magnetic Spin Torque Transfer
 STT-RAM
 Magnetic Racetrack
• Phase Change RAM
• Resistive RAM
2) High-density access device (A.D.)
• 2-D – silicon transistor or diode
• 3-D  higher density per 4F2
• polysilicon diode (but <400oC processing?)
• MIEC A.D. (Mixed Ionic-Electronic Conduction)
• OTS A.D. (Ovonic Threshold Switch)
NVM memory element
plus access device
Generic SCM Array
• Conductive oxide tunnel barrier A.D.
21
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
High density  3D Multilayer Crosspoint Memory Array
As a result of the cost-basis of semiconductor manufacturing,
memory cost is inversely related to bit density
(adapted from Burr, EIPBN 2008)
Stack ‘L’ layers in 3D
Effective cell size: 4F2
Effective cell size: 4F2/L
F = minimum litho. feature size
Since they effectively
store more bits per 4F2 footprint,
3D crosspoint arrays  a route to low cost memory
22
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Large arrays require an Access Device at each element
Apply V
Memory Element (PCM, RRAM etc.)
Access Device (Selector)
Sense I
Current ‘sneak path’problem
Access device needed in series with memory element
• Cut off current ‘sneak paths’ that lead to
incorrect sensing and wasted power
• Typically diodes used as access devices
• Could also use devices with highly non-linear I-V curves
23
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Requirements for an Access Device for 3D Crosspoint Memory
• High ON-state current density
>10 MA/cm2 for PCM / RRAM RESET
• Low OFF-state leakage current
>107 ON/OFF ratio, and
wide low-leakage (< 100pA) voltage zone to
accommodate half-selected cells in large
arrays
• Back-End process compatible
<400C processing to allow 3D stacking
• Bipolar operation
needed for optimum RRAM operation
PCM or RRAM
Access
Device
IBM’s MIEC-based access device satisfies all these criteria
24
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC access devices offer highly nonlinear & Bipolar I-V Curves
TEC
MIEC
100A
W
10A
1A
100A
gap
100nA
10nA
1nA
100pA
Applied
Voltage
10pA
10nA
1nA
100pA
-0.5
-0.3
-0.1
0.1
0.3
0.5
200nm
inert TEC
10pA
[V]
1pA
ILD
1A
overlap
100nA
BEC
poly-Si series resistor
10A
|Current|
|Current|
W=200nm
Gap=100nm
Overlap=250nm
80nm BEC
1pA
-1
-0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
Voltage [V]
Lateral (bridge) device
Vertical device (scaled TEC)
• Devices fabricated on 4inch wafers
• Voltage margin @ 10nA of 0.85V
• Suitable (desirable) for bipolar memory elements such as RRAM
MIEC access devices can operate in both polarities
(Gopalakrishnan et al, 2010 VLSI Tech. Sym.)
25
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC device operation

Top Electrode (TE)
MIEC
Cu+ Ion Motion
Bottom Electrode (BE)

Our devices:
BE  inert (eg. W, TiN)
TE  inert or ionizable
MIEC can be deposited @ ~200C
Cu-containing Mixed Ionic-Electronic
Conduction† (MIEC) materials:
• Mobile Cu  transport in E-field
• Cu interstitials/vacancies can act as dopants
 relationship between mobile Cu and
local electron/hole
concentration
Voltage applied to electrodes leads to …
• transient Cu ion drift, followed by
• steady-state electron/hole current
†Ref:
I. Riess, Solid State Ionics, 157, 1 (2003) for an
overview of MIEC models
Exploit non-linear I-V relationship in MIEC devices
for access device functionality
(Gopalakrishnan et al, 2010 VLSI Tech. Sym.)
26
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC devices – 200mm wafer integration demonstrated
180 nm CMOS
Front-End
 1T-1MIEC
(1 transistor + 1 MIEC
access device)
As-deposited
TEM x-section
Post-CMP
CMP process for MIEC material with modified commercial Cu slurry 
self-aligned MIEC Diode-in-Via (DIV) in a 200 mm wafer process
(Shenoy et al, 2011 VLSI Tech. Sym.)
27
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC devices support ultra-low leakage currents
(needed for successful half- and un-select within large arrays)
Voltage margin @ 10nA of 1.1V
~10 pA leakage currents near 0V & wide range with <100pA
28
(Burr et al, 2012 VLSI Tech. Sym.)
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC devices can supply LARGE driving currents
(needed for successful write of power-hungry NVM candidates)
Pulse
generator
V
t
Current
50W Scope
t
100’s of uA pulse currents  ON/OFF ratio >107
(Shenoy et al, 2011 VLSI Tech. Sym.)
29
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Requirements for an Access Device for 3D Crosspoint Memory
 High ON-state current density
>10 MA/cm2 for PCM / RRAM RESET
 Low OFF-state leakage current
>107 ON/OFF ratio, and
wide low-leakage (< 100pA) voltage zone to
accommodate half-selected cells in large arrays
 Back-End process compatible
<400C processing to allow 3D stacking
 Bipolar operation
PCM or RRAM
needed for optimum RRAM operation
•
•
•
•
•
•
•
30
variability?
yield?
co-integration with NVM?
turn-ON speed for write?
endurance?
manufacturability?
scalability?
Geoffrey W. Burr
• long-term leakage?
• turn-OFF speed?
• turn-ON speed for read?
IBM Research – Almaden
Access
Device
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Multiple MIEC devices can be made with similar characteristics
(essential for reading, especially if SNR from the NVM is low)
5x10 arrays of FETconnected DIVs
• Voltage margin (Vm) ~1.1V
• Low inter-device variability
Integrated small arrays of
MIEC DIVs with high yield
(Shenoy et al, 2011 VLSI Tech. Sym.)
31
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Large Arrays of MIEC have been integrated at 100% yield
100% yield and tight distributions in 512 kbit 1T-1MIEC array
(Burr et al, 2012 VLSI Tech. Sym.)
32
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC has been integrated together with PCM in 200mm process
Demonstrated > 105 cycles of PCM SET/RESET
through stacked MIEC access device
(Burr et al, 2012 VLSI Tech. Sym.)
33
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC supports 15ns writes of PCM  suitable for M-class SCM
15ns
500
5 ns/division
400 Current
[uA]
300
200
Increasing
pulse
amplitude
a)
100
0
Read Current @660mV
(Virwani et al, IEDM 2012)
Time
1uA
post-SET
300nA
PostRESET
100nA
30nA
RESET current [uA]
100
150 200
300 400
MIEC access device can supply >150uA in 15ns …
sufficient to RESET PCM
34
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC endurance at low current  >> 1e10 cycles
ON current >5A
100A
sufficient for PCM-read
(Rs~30k Vapplied~ -0.8V)
|Current|
10A
80 nm BEC
Wide-area
ionizable TEC
1A
Pulse duration ~2s
100nA
OFF current at -0.3V
10nA
1nA
OFF current at -0.2V
100pA
100
1000
104
105
106
107
108
109
Pulses
1010
Testing
timelimited!
Low current (memory READ) endurance > 1010 cycles
(Gopalakrishnan et al, 2010 VLSI Tech. Sym.)
35
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC endurance at high current is finite  leakage increases
DC I-V curves
monitored in between
100uA pulses
After many cycles …
Leakage current rises …
… and voltage margin
shrinks
High current (memory WRITE) endurance is finite.
(Shenoy et al, 2011 VLSI Tech. Sym.)
36
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC endurance scales sharply with current (NOT current density)
Endurance depends inversely on current
(exponential) and pulse duration
(Shenoy et al, 2011 VLSI Tech. Sym.)
37
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC endurance at modest write currents > 1e8
>108 endurance
for sub-45nmnode PCM!
( IRESET < 150 A )
Expect even higher
MIEC endurance for
RRAM
(IPROG/ERASE <100uA)
Strong current-dependence of MIEC access device endurance
persists across many different device structures
(Shenoy et al, 2011 VLSI Tech. Sym.)
38
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
MIEC cycling failure associated with Copper agglomeration
Before cycling
TEM/EELS local
stoichiometry
BEC CD ~ 80 nm
Wide area TEC
After cycling
425,000 cycles
@ 325 A
negative
voltage on
TEC
Endurance failure correctable by
annealing and/or voltage pulses
(Shenoy et al, 2011 VLSI Tech. Sym.)
39
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Requirements for an Access Device for 3D Crosspoint Memory
 High ON-state current density
>10 MA/cm2 for PCM / RRAM RESET
 Low OFF-state leakage current
>107 ON/OFF ratio, and
wide low-leakage (< 100pA) voltage zone to
accommodate half-selected cells in large arrays
 Back-End process compatible
<400C processing to allow 3D stacking
 Bipolar operation
PCM or RRAM
needed for optimum RRAM operation
 variability?
 yield?
 co-integration with NVM?
 turn-ON speed for write?
 endurance?
• manufacturability?
• scalability?
40
Geoffrey W. Burr
• long-term leakage?
• turn-OFF speed?
• turn-ON speed for read?
IBM Research – Almaden
Access
Device
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Conductive AFM  rapid exploration of processes & materials
Large thermal process budget window
Manufacturable deposition
Short loop process flows
on relevant structures
Rapid learning cycles
enabled by cAFM
(Burr et al, 2012 VLSI Tech. Sym.)
41
Geoffrey W. Burr
Process optimization for higher Vm
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Lateral scaling of just BEC size
Wide-area Ionizable TEC
1m
10A
1A
Via height:
20nm
250nm
Vbias
-0.50V 40nm
80nm
10nA
1.6
1nA
100pA
10pA
Voltage [V]
|Current|
100nA
-0.35V
-0.30V
-0.25V
1.2
0.8
Via height: 40nm
1000
104
19 nm
0.4
Time [ns]
0
0
105
200
2
400
600
800
106
Via area = CD [nm2]
Current scales well with BEC size over several orders of magnitude
Suggests non-filamentary nature of operation mechanism
(Gopalakrishnan et al, 2010 VLSI Tech. Sym.)
42
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Correction to 2012 IEDM
Lateral scaling of TEC size (slide 1 of 3)
139nm
139nm
89nm
48nm
Voltage margin
increased with
smaller TEC CD
Consistent
with trend
seen on earlier
devices
(Virwani et al, 2012 IEDM)
(Shenoy et al, 2011 VLSI Tech. Sym.)
43
Selector functionality is maintained in fully confined
MIEC devices with reduced TEC and BEC size
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Lateral scaling of TEC size (slide 2 of 3)
(Virwani et al, 2012 IEDM)
Ultra-scaled MIEC access devices can still deliver
>100uA pulse currents in both polarities
44
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Lateral scaling of TEC size (slide 3 of 3)
Sub-30nm lateral CD MIEC device
(Virwani et al, 2012 IEDM)
No lower limit to lateral scaling has been found so far
45
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Thickness scaling trends
C-AFM
tip
TEC
SiN
MIEC
dmin
BEC
oxide
Si wafer
Cumulative
distribution
plots of 10nA
MIEC voltage
margin
MIEC devices are well behaved down to 12nm minimum
inter-electrode distance (dmin)
(Virwani et al, 2012 IEDM)
46
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Thickness scaling trends – failure analysis (slide 1 of 2)
(Virwani et al,
2012 IEDM)
47
Start to see some failures in arrays of MIEC devices with
dmin ~12nm  Leakage current increases
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Thickness scaling trends – failure analysis (slide 2 of 2)
Good
(Virwani et al, 2012 IEDM)
Ba
d
Good
Use TEM to correlate
device failures to
MIEC thickness
Lower limit seen for thickness scaling of
this MIEC access device
48
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Requirements for an Access Device for 3D Crosspoint Memory
 High ON-state current density
>10 MA/cm2 for PCM / RRAM RESET
 Low OFF-state leakage current
>107 ON/OFF ratio, and
wide low-leakage (< 100pA) voltage zone to
accommodate half-selected cells in large arrays
 Back-End process compatible
<400C processing to allow 3D stacking
 Bipolar operation
PCM or RRAM
needed for optimum RRAM operation







49
variability?
yield?
co-integration with NVM?
turn-ON speed for write?
endurance?
manufacturability?
scalability?
Geoffrey W. Burr
• long-term leakage?
• turn-OFF speed?
• turn-ON speed for read?
IBM Research – Almaden
Access
Device
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Novel Mixed-Ionic-Electronic-Conduction (MIEC) Access Device
Strengths
• High enough ON currents for PCM –
cycling of PCM has been demonstrated
• Low enough OFF current for large arrays
• Very large (>>1e10) endurance for typical
5uA read currents
• Voltage margins > 1.5V with tight
distributions  sufficient for large arrays
• CMP process demonstrated
• 512kBit arrays demonstrated w/ 100% yield
• Scalable to <30nm CD, <12nm thickness
• Capable of 15ns write, <<1us read
Weaknesses
• Maximum voltage across companion
NVM during switching must be low
(1-2V)  influences half-select condition
and thus achievable array size
• Endurance during NVM
programming is strongly dependent on
programming current
50
Geoffrey W. Burr
Gopalakrishnan, VLSI 2010
Shenoy, VLSI 2011
IBM Research – Almaden
Burr, VLSI 2012
Virwani, IEDM 2012
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Competitive Outlook among emerging NVMs
Future NAND applications
(consumer devices, etc.)
Future NOR applications
(program code, etc.)
conventional NAND may require >50 layers!)
• PCM (but market disappearing)
High Speed
Embedded Storage
(low density, slower ON-chip storage)
• NAND? (but complicated process)
• RRAM?/PCM?
• 3-D NAND (but crossover to succeed 20nm
• PCM?/RRAM?
S-type Storage Class Memory
(high-density, very-near-ON-line storage)
1) PCM?/RRAM?
2) Racetrack? (future?)
M-type Storage Class Memory
(high-density, fast OFF- (or ON*)-chip NVM)
Embedded Non-Volatile Memory
(low-density, fast ON-chip NVM)
• CBRAM? STT-RAM?
• PCM?/RRAM?
• Racetrack? (future?)
• STT-RAM? CBRAM?
Low co$t
51
Geoffrey W. Burr
IBM Research – Almaden
* ON-chip using 3-D packaging
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
Device
Availability
Paths towards SCM
Capital
investment
NAND
3-D NAND
Future NAND applications
(consumer devices, etc.)
unlikely, but
possible path
1-10us
emerging NVM
Embedded Storage
(low density,
slower ON-chip storage)
RRAM? PCM?
CBRAM?
<<1us
emerging NVM
STT-RAM? CBRAM?
PCM??/RRAM??
Embedded
Non-Volatile Memory
S-type SCM
(high-density,
near-ON-line storage)
M-type SCM
(high-density,
fast OFF-(or ON*)
-chip NVM)
(low-density, fast ON-chip NVM)
* ON-chip using 3-D packaging
Future DRAM
DRAM
52
Co$t

Applications
(working memory, etc.)
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
What does the future hold?
• Consumer disk and enterprise tape will persist for the foreseeable future
• Flash will come into its own (in enterprise systems)
• Flash may drive out enterprise disk, and if it doesn’t, SCM will
• When will SCM arrive?
That will depend on the path the NAND industry takes after the 16-20nm node…
• 3-D NAND succeeds  new NVMs (such as PCM, RRAM, STT-RAM) will develop
slowly, driven only by SCM/embedded market
• 3-D NAND fails or is late  one new NVM will be driven rapidly by NAND market
• If the latter, SCM could become the dominant storage technology by 2020
• The application software stack will be redesigned to utilize
SCM-enabled persistent memory
53
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013
Towards SCM: 3-D crosspoint access devices using MIEC
For more information & acknowledgements
[email protected]
• K. Virwani, G. W. Burr, Rohit S. Shenoy, C. T. Rettner, A. Padilla, T. Topuria, P. M. Rice, G. Ho, R. S. King, K. Nguyen, A. N.
Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and Kailash Gopalakrishnan, “Sub-30nm
scaling and high-speed operation of fully-confined Access-Devices for 3-D crosspoint memory based on Mixed-Ionic-Electronic-Conduction
(MIEC) Materials,” IEDM Technical Digest, 2.7, (2012).
• Geoffrey W. Burr, Kumar Virwani, R. S. Shenoy, Alvaro Padilla, M. BrightSky, E. A. Joseph, M. Lofaro, A. J. Kellock, R. S.
King, K. Nguyen, A. N. Bowers, M. Jurich, C. T. Rettner, B. Jackson, D. S. Bethune, R. M. Shelby, T. Topuria, N. Arellano, P. M. Rice,
Bulent N. Kurdi, and K. Gopalakrishnan, “Large-scale (512kbit) integration of Multilayer-ready Access-Devices based on Mixed-Ionic-
Electronic-Conduction (MIEC) at 100% yield,” Symposium on VLSI Technology, T5.4, (2012).
• R. S. Shenoy, K. Gopalakrishnan, Bryan Jackson, K. Virwani, G. W. Burr, C. T. Rettner, A. Padilla, Don S. Bethune, R. M.
Shelby, A. J. Kellock, M. Breitwisch, E. A. Joseph, R. Dasaka, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, A. M. Friz, T. Topuria,
P. M. Rice, and B. N. Kurdi, “Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint Memory based on Mixed Ionic
Electronic Conduction (MIEC) Materials,” Symposium on VLSI Technology, T5B-1, (2011).
• K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, K. Virwani, Don S. Bethune, R. M. Shelby, G. W. Burr, A. J. Kellock, R. S. King, K.
Nguyen, A. N. Bowers, M. Jurich, B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, "Highly-Scalable Novel Access Device
based on Mixed Ionic Electronic Conduction (MIEC) Materials for High Density Phase Change Memory (PCM) Arrays," Symposium on VLSI
Technology, 19.4, (2010).
• G. W. Burr, Matt J. Breitwisch, Michele Franceschini, Davide Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, Luis
A. Lastras, A. Padilla, Bipin Rajendran, S. Raoux, and R. Shenoy, "Phase change memory technology," Journal of Vacuum
Science & Technology B, 28(2), 223-262, (2010).
• G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, "An overview of candidate device technologies for
Storage-Class Memory," IBM Journal of Research and Development, 52(4/5), 449 (2008).
• S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y. Chen, R. M. Shelby, M. Salinga, D. Krebs, S. Chen, H. L. Lung, and C. H.
Lam, "Phase-change random access memory — a scalable technology," IBM Journal of Research and Development, 52(4/5), 465,,
(2008).
• Rich Freitas and Winfried Wilcke, “Storage Class Memory, the next storage system technology,” IBM Journal of Research
and Development, 52(4/5), 439, (2008).
• Yi-Chou Chen, Charlie T. Rettner, Simone Raoux, G. W. Burr, S. H. Chen, R. M. (Bob) Shelby, M. Salinga, W. P. Risk, T. D.
Happ, G. M. McClelland, M. Breitwisch, A. Schrott, J. B. Philipp, M. H. Lee, R. Cheek, T. Nirschl, M. Lamorey, C. F. Chen, E. Joseph,
S. Zaidi, B. Yee, H. L. Lung, R. Bergmann, and Chung Lam, "Ultra-Thin Phase-Change Bridge Memory Device Using GeSb," IEDM
Technical Digest, paper S30P3, (2006).
http://researcher.ibm.com, search for “Burr” or “Storage Class Memory”
54
Geoffrey W. Burr
IBM Research – Almaden
February 12, 2013