6-4 Recovery dynamics and fast (sub-50ns) read operation with Access Devices for 3D Crosspoint Memory based on Mixed-Ionic-Electronic-Conduction (MIEC) G. W. Burr, K. Virwani, R. S. Shenoy, G. Fraczak† , C. T. Rettner, A. Padilla, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky† , E. A. Joseph† , A. J. Kellock, N. Arellano, B. N. Kurdi and K. Gopalakrishnan† IBM Almaden Research Center, 650 Harry Road, San Jose, CA 95120 († IBM T. J. Watson Research Center, Yorktown Heights, NY 10598) Tel: (408) 927–1512, Fax: (408) 927–2100, E-mail: [email protected] Abstract BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials[1-4] are shown to be capable of both maintaining and moving rapidly between all the roles necessary for 3D crosspoint memory (un-selected, half-selected, selected(read), and selected(write)). Ultra-low leakage is maintained over hours, recovery dynamics after both write (30-50uA) and read (3-6uA) operations are explored, and read operations fast enough for use with MRAM (sub-50ns) at low voltages are demonstrated. Keywords: Access device, MIEC, PCM, NVM, RRAM, MRAM Introduction 3D-stacking of large crosspoint arrays in the BEOL can allow a nonvolatile memory (NVM) to be as cost-effective as 2D NAND FLASH (≤4F2 /3). MIEC-based ADs exhibit the large ON/OFF ratios needed for such arrays (Fig. 1), with high voltage margin Vm (for which leakage is ≤10nA), ultra-low leakage (<10pA), high enough write currents (>100uA) even for PCM, and the bidirectional nonlinearity needed for stacking high-density MRAM and RRAM in the BEOL [1-4]. In addition, we have shown both scalability to <30nm CD and <15nm thickness [4], and tight distributions and 100% yield in large (512kBit) arrays[3]. In a crosspoint array, each AD must fill multiple roles: holding ultra-low (∼10pA) leakage at low un-selected bias for hours; maintaining modest (∼10nA) leakage at half-selected bias for seconds; and occasionally being selected to pass either read-level (3-6uA) or write-level (30-60uA) currents through its NVM (Fig. 2). The AD must maintain low leakage over very long periods, yet switch into a current-passing role and back to low leakage, quickly and seamlessly. To date, we have shown fast turn-ON speeds (15ns) of MIEC-based ADs, mostly in the PCM write regime (≥100uA)[4]. In this paper, we show that MIEC-based ADs maintain half- and un-selected states with ultra-low leakage over hours. We explore the time to recover low-leakage after both NVM-write (30-50uA) and NVM-read (3-6uA) operations, demonstrate fast NVM-reads (<50ns) suitable for MRAM, and show similarly fast turn-ON in thinner ADs with less overvoltage (thus minimal read disturb). Stability of low-leakage in MIEC ADs MIEC-based ADs are integrated on 8” wafers, using sputterdeposition of Cu-containing MIEC material into vias followed by an optimized CMP process[2] and a confined, non-ionizable TEC. Small “1T-1AD” device arrays are integrated with 180nm-node FETs (Fig. 3(a)) [2-4]; “short-loop” devices (Fig. 3(b)) are tested with Conductive-AFM [3-4], using a proximate bottom contact with low series resistance made by removing nearby devices. The long-term, low-bias stability of large 1T-1AD devices (Vm ∼ 1.05V [2-3]) was tested with VWL ∼ 3.5V (all applied voltage VDUT appears across the AD). Fig. 4 shows that MIEC ADs maintain low-leakage over hours of exposure, whether in a deep (±230mV) or shallow un-select (±350mV) condition (inset). Repeated exposure to the half-select (±530mV) condition (Fig. 5, t<70s) has no appreciable effect on any of the leakage conditions, and even prolonged exposure to higher currents (Fig. 5, t>70s) induces only subtle effects on subsequent leakage. Recovery of low-leakage in MIEC ADs While Figs. 4, 5 show excellent stability, the SMU is too slow to gauge MIEC AD recovery. With a low VWL , a large first AFG “over-voltage” pulse can force a rapid turn-on (Fig.6) of a 1T-1AD T66 978-4-86348-347-7 to a given current level; a second pulse can then probe AD recovery dynamics under read or lower bias conditions (Figs. 7–11). Fig. 7 shows that after a strong write pulse (50uA for 1us), MIEC AD response is in fact affected. For a read following a write (Fig.7, top), the MIEC AD simply supplies the usual expected current (∼10uA) instantly, without needing overvoltage acceleration. At much lower bias, however, (Fig. 7, bottom) significantly larger currents than the expected low leakage can persist. Assumably, turn-ON involves shifting Cu (slowly under modest bias, rapidly under overvoltage). Once large currents have been passed, some Cu may remain “latched” in place, altering device response. However, even brief (1us) exposure to 0V restores much of the original low-leakage response (Fig.8), and negative voltages accelerate this significantly (Fig.9). Post-write effects are also greatly suppressed if write duration is limited (Fig. 10). Despite this, some sort of explicit post-write recovery sequence is likely to be necessary. In contrast, recovery after read-level currents is much faster. Fig.11 shows a 3-pulse sequence, in which two long (4ms) pulses at 600mV surround a brief (1us) pulse at 2V. Since VWL is significantly lower, the maximum current is limited to 6uA per-device (to obtain sufficient SNR here, ten devices along a single column were pulsed in parallel). Before the read pulse and without overvoltage, the current at 600mV slowly builds up to ∼300nA. After the read pulse, leakage has increased by no more than 50%, and exposure to 0V (for even 500ns) completely restores the original leakage characteristics. Fig. 12 quantifies the recovery dynamics after write and read events. Role of thickness in MIEC AD turn-ON speed Since these 1T-1AD MIEC ADs are fairly thick (dmin ∼ 75nm), rapid turn-ON requires significant overvoltage (Fig.13(a)). Despite the slow native response, turn-ON from half-select to 10uA read currents can be sub-50ns (Fig. 13(b)). However, such large overvoltages in the presence of bitline capacitance could lead to read disturbs. “Short loop” devices with proximate BEC contacts allow testing of thinner MIEC ADs [4]. Fig.14(a) shows that native turn-ON (without overvoltage) speeds up considerably as MIEC ADs get thinner, Even modest pulse-shaping in thin MIEC ADs can readily deliver 100ns read-level (10uA) turn-ON (Fig.14(b)). Conclusions BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-4] can sustain and move rapidly between unselected, half-selected, selected(read), and selected(write) states. Ultra-low leakage can be maintained over hours, leakage recovery after write (30-50uA) operations requires ∼1us (with read (3-6uA) recovery even faster), read operations can be fast enough for use with MRAM (sub-50ns), and inherently-fast thin MIEC ADs offer similar speeds at modest overvoltages (for minimal read disturb). Acknowledgements Expert analytical and processing support from T. Topuria, P. Rice, E. Delenia, L. Krupp, D. Hepner, D. Erpelding and the Microelectronics Research Laboratory (YKT) is gratefully acknowledged. References [1] K. Gopalakrishnan et. al., VLSI 2010, T19-4 (2010). [2] R. Shenoy et. al., VLSI 2011, T5B-1 (2011). [3] G. W. Burr et. al., VLSI Tech. Symp., T5.4 (2012). [4] K. Virwani et. al., IEDM Tech. Digest, 2.7 (2012). 2013 Symposium on VLSI Technology Digest of Technical Papers (300ns) 1uA 100nA 1e-5 0.001 0.0001 0.01 0.1 Current 0.9 0.5 Vm~1.53V 1nA 100pA a) 10pA 300nA V1 100nA via 1pA DC IV -1.5 -1.0 -0.5 0 0.5 1.0 30nA 1.5 .99999 .9999 .999999 BEC via b) -1 -0.5 ~½Vm + 350mV + … 0 Voltage [V] 0.5 1 1.5 b) SMU/AFG dmin MIEC SCOPE 196: 100nm BEC 0us No overvoltage Time 1us 2us 3us 4us 25uA 5us Vc ½Vm (= 520mV) un-select 0uA 0 25uA 50 … + 750mV 25 Time [hours] then 0 50 0uA 0 0ns 250ns 500ns 25uA Time 750s 0uA 1us Fig. 6 Turn-ON delay—as induced by RC-delay in establishing a given voltage across a 1T-1AD, followed by the response of the MIEC AD to that voltage—can be greatly reduced by overvoltage. 40 20 0 10us @ 50uA 40 20 0 3us @ 50uA 40 20 0 1us 0V for 100ns, then 0.9V for 1us 0V for 100ns, then 0.9V for 1us 0V for 100ns, then 0.9V for 1us @ 50uA 300ns 40 20 0 0V for 100ns, then 0.9V for 1us @ 50uA 100ns 40 20 0 @ 50uA -1us 0V for 100ns, then 0.9V for 1us Time 1us 0us Fig. 10 Post-write effects can also be greatly suppressed by reducing the duration of the 50uA write pulse. Current (a)10uA 5uA 0uA 0us No overvoltage Time 10us 20us 30us 40us 50us 10uA Current 5uA then 100ns @0V @ 0.9V 1us @ 0.9V 5us 10us 0 1us 0ns @0V 0 1us @0V 1us @ 0.7V @ 0.7V 1ms 2ms 0 1us 2us 0ns @0V 2us 100ns 1us Native response 0 2us @ 0.7V 0 1us 2us 100ns @0V 1us Native response 0 1us @ 0.5V @ 0.5V 5ms 10ms 0 1us Time 2us @ 0.5V 0 1us 2us 800 600 400 200 0 800 600 400 200 0 800 600 400 200 0 1us 1us 2V for 1us Æ 6uA then 1us @0V 50ns 25ns 0ns 500ns 1us 1.5us 2us 0.6V for 3us @ 50uA 0us 1us 2us 3us 4us 2ms (a) 0.6V for 4ms Time dmin = 10uA 4ms Fig. 11 After a 1us read pulse at 6uA (perdevice over 10 ADs), leakage is never more 450nA, or 1.5× the expected static leakage level that would build up over ∼1ms anyway. 100ns 0ns 100ns 0ns 100ns 0.9V for 1us @ 50uA 0us 50 1us 25 Time 2us 500ns at 0V 1us 0.9V for 1us @ 50uA 0 50 500ns at <0V 1us 25 @ 50uA 0 0.9V for 1us Leakage Post write (50uA) current recovery (Fig. 8) (at 600mV) 3uA Dotted fits are guide-to-the-eye only Post read (6uA) recovery (Fig. 11) 1uA 300nA 0 Static leakage at 600mV 0 500ns 1us 1.5us Recovery time at 0V Fig. 12 Restoration of the static IV characteristics (at 600mV) after write (50uA) events takes longer than after a read (6uA). 100ns shaped pulse (max. overvoltage: 350mV) 10uA Current 36nm 5uA 47nm 0uA 0ns 200ns at <0V 1us 25 (b) 11nm 28nm 5uA Time Time Time Time Fig. 13 (a) Despite their slow native response, thick (dmin ∼75 nm) MIEC 1T-1AD devices can be turned ON rapidly with large overvoltage, allowing (b) the transition from half-select to 10uA read currents to occur in <50ns. 0.9V for 1us @ 50uA 0 50 0 200ns at 0V 1us 25 0us 1us 2us Time Fig. 9 Exposure to negative voltages accelerates the recovery after a 1us write (50uA) pulse. Time Current 10uA 5us 50 5uA 0.6V for 4ms 0uA … + 1.15V 5uA 0.6V for 3us 1us 0.6V for 4ms (b) 15uA 100ns Current 300ns @0V 1us @0V 2V for 1us Æ 6uA then 500ns @0V 0 0.6V for 3us @ 50uA 0.6V for 4ms -2ms 100ns @0V @ 50uA 0.6V for 4ms 0uA 10uA 0uA 1us 2V for 1us Æ 6uA then 200ns @0V -4ms 0.6V for 3us 30ns @0V @ 50uA 5uA … + 600mV 5uA @ 50uA 0.6V for 4ms 0.6V for 4ms 800 600 400 200 0 0.6V for 3us 0.6V for 4ms 2V for 1us Æ 6uA then 100ns @0V 0.6V for 4ms 0ns @0V 1us Fig. 8 Even brief (1us) exposure to 0V after a 1us write (50uA) pulse restores much of the original lowleakage response. 2V for 1us Æ 6uA then 50ns @0V 0.6V for 4ms 800 600 400 200 0 … + 300mV 0uA 10uA 15 10 5 0 15 10 5 0 15 10 5 0 15 10 5 0 15 10 5 0 Fig. 7 After a strong write pulse (50uA for 1us), MIEC AD response is affected: devices remain ON, don’t require overvoltage acceleration to turn back ON, and at lower voltages where leakage should be undetectable, measurable currents can persist. Measured current PER DEVICE [nA] … + 1.0V 1us @ 50uA 1us @ 0.9V 50uA 25 0ns @0V Native response 0 Time [seconds] Fig. 5 Repeated 2sec exposures to half-select (±530mV) and even higher bias conditions has minimal impact on subsequent leakage. Fig. 4 MIEC ADs maintain low-leakage over hours of exposure, whether in a deep (±230mV) or shallow un-select (±350mV) condition. 50uA … + 350mV 25 @ 50uA 50uA Measured current [uA] 50 Current [uA] 0 Vc Current ½Vm + 120mV ½Vm + 60mV Measured current [uA] 1us Current 0 Measured current [uA] ~10pA un-select leakage (across half-selected ADs of same row) Proximate BEC contact Fig. 3 A Source-Measure Unit (SMU), or an Arbitrary Function Generator (AFG) and oscilloscope, address either small “1T-1AD” MIEC arrays [2-4] or “short-loop” MIEC ADs tested with Conductive-AFM and a nearby BEC contact. 25 Vr ½Vm – 180mV un-select ½Vm – 300mV Voltage [V] MIEC (DC) 50 (across un-selected ADs biased NEGATIVE) ~10nA half-select leakage ~½Vm (deep) TEC dmin VWL Vc ~½Vm – 200mV Vr V Fig. 2 Voltage on a selected NVM+AD affects 3 other sets of ADs: those in the same row, in the same column (both half-selected), and all others (un-selected). Each AD must hold ultra-low (∼10pA) leakage for hours, maintain modest (∼10nA) leakage for seconds, and occasionally pass either read-level (3-6uA) or write-level (30-60uA) currents. half-select (shallow) C-AFM tip Vr ~½Vm (across half-selected ADs of same column) Measured current [uA] a) uProbe & pad ~3-60uA Read or Write current + Required NVM voltage + … …+ voltage drop across wiring (across selected diode) …but also should not exceed sum of: via FET V …has to provide: ILD Fig. 1 MIEC-based ADs exhibit the large ON/OFF ratios needed for large crosspoint arrays, showing (a) high voltage margin Vm (for which leakage stays below 10 nA) [34], high ON current densities [1,4], ultra-low leakage (< 10 pA) [2-4], good scalability (<30nm CD, <12nm thickness) [4], and (b) tight margins (as well as 100% yield) when integrated on 8" CMOS wafers in large (512kBit) arrays[3]. Current VDUT V across selected cell… 0Volts TEC MIEC 10nA -1.5 Voltage [V] .999 M2 M1 10nA .99 Log(I) pulsed IV 10uA Current [uA] 1uA Log(I) 1e-6 100uA 0ns 500ns 0uA Time 1us -100ns 0ns 100ns Time 200ns Fig. 14 Thinner MIEC ADs are measurably faster, both in terms of (a) the un-accelerated native turn-ON as well as (b) when accelerated with modest (+350mV) overvoltage. 2013 Symposium on VLSI Technology Digest of Technical Papers T67