BUK7E3R5-60E N-channel TrenchMOS standard level FET 11 September 2012 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in a SOT226 package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 1.2 Features and benefits • AEC Q101 compliant • Repetitive avalanche rated • Suitable for thermally demanding environments due to 175 °C rating • True standard level gate with VGS(th) rating of greater than 1V at 175 °C 1.3 Applications • 12 V Automotive systems • Motors, lamps and solenoid control • Start-Stop micro-hybrid applications • Transmission control • Ultra high performance power switching 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 60 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 1 - - 120 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 293 W VGS = 10 V; ID = 25 A; Tj = 25 °C; - 2.6 3.5 mΩ - 34.8 - nC [1] Static characteristics RDSon drain-source on-state resistance Fig. 11 Dynamic characteristics QGD gate-drain charge ID = 25 A; VDS = 48 V; VGS = 10 V; Fig. 13; Fig. 14 [1] Continuous current is limited by package. Scan or click this QR code to view the latest information for this product BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb G S mbb076 1 2 3 I2PAK (SOT226) 3. Ordering information Table 3. Ordering information Type number Package BUK7E3R5-60E Name Description Version I2PAK plastic single-ended package (I2PAK); TO-262 SOT226 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 60 V VDGR drain-gate voltage RGS = 20 kΩ - 60 V VGS gate-source voltage Tj ≤ 175 °C; DC -20 20 V ID drain current Tmb = 25 °C; VGS = 10 V; Fig. 1 [1] - 120 A Tmb = 100 °C; VGS = 10 V; Fig. 1 [1] - 120 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4 - 785 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 293 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C - 120 A - 785 A Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 [1] © NXP B.V. 2012. All rights reserved 2 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET Symbol Parameter Conditions Min Max Unit - 404 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 120 A; Vsup ≤ 60 V; RGS = 50 Ω; [2][3] VGS = 60 V; Tj(init) = 25 °C; unclamped; Fig. 3 [1] [2] [3] Continuous current is limited by package. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 003aah795 240 03aa16 120 ID (A) Pder (%) 160 80 (1) 80 0 40 0 50 100 150 Tmb (° C) 0 200 (1) Capped at 120A due to package Fig. 1. Continuous drain current as a function of mounting base temperature Fig. 2. 0 50 100 150 Tmb (°C) 200 Normalized total power dissipation as a function of mounting base temperature 003aah796 103 IAL (A) 102 (1) 10 (2) 1 (3) 10-1 10-3 Fig. 3. 10-2 10-1 1 t (ms) 10 AL Single pulse avalanche rating; avalanche current as a function of avalanche time BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 3 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET 003aah797 103 ID (A) Limit RDSon= V DS / ID tp =10 µ s 102 100 µ s 10 DC 1 ms 10 ms 1 100 ms 10-1 10-1 Fig. 4. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 0.51 K/W Rth(j-a) thermal resistance from junction to ambient vertical in still air - 65 - K/W 003aaj702 1 Z th(j-mb) (K/W) 10-1 δ = 0.5 0.2 0.1 0.05 0.02 10 P -2 δ= single shot tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 tp T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 4 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 60 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 54 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 2.4 3 4 V 1 - - V - - 4.5 V VDS = 60 V; VGS = 0 V; Tj = 25 °C - 0.09 1 µA VDS = 60 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; - 2.6 3.5 mΩ - - 7.6 mΩ Static characteristics V(BR)DSS VGS(th) Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 9 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11 VGS = 10 V; ID = 25 A; Tj = 175 °C; Fig. 11; Fig. 12 Dynamic characteristics QG(tot) total gate charge ID = 25 A; VDS = 48 V; VGS = 10 V; - 114 - nC QGS gate-source charge Fig. 13; Fig. 14 - 24.6 - nC QGD gate-drain charge - 34.8 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 6685 8920 pF Coss output capacitance Tj = 25 °C; Fig. 15 - 851 1025 pF Crss reverse transfer capacitance - 502 690 pF td(on) turn-on delay time VDS = 45 V; RL = 1.8 Ω; VGS = 10 V; - 28 - ns tr rise time RG(ext) = 5 Ω - 45 - ns td(off) turn-off delay time - 68 - ns tf fall time - 49 - ns LD internal drain inductance from upper edge of mounting base to centre of die ; Tj = 25 °C - 2.5 - nH Tj = 25 °C; from drain lead 6mm from - 4.5 - nH - 7.5 - nH package to centre of die LS internal source inductance BUK7E3R5-60E Product data sheet measured from source lead to source bond pad ; Tj = 25 °C All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 5 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET Symbol Parameter Conditions Min Typ Max Unit Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.8 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 42.1 - ns Qr recovered charge VDS = 25 V - 59.3 - nC 003aaj703 360 VGS (V) = 10 ID (A) 8 003aah440 15 6 RDSon (mΩ ) 5.5 240 10 5 120 5 4.5 0 4 0 1 2 VDS(V) 0 3 Tj = 25 °C; tp = 300 μs Fig. 6. Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values 003aaj706 480 0 5 10 15 V (V) 20 GS Drain-source on-state resistance as a function of gate-source voltage; typical values 003aah027 5 VGS(th) (V) ID (A) max 4 360 3 typ 2 min 240 Tj = 175 °C 120 1 Tj = 25 °C 0 Fig. 8. 0 2 4 6 VGS (V) 0 -60 8 Transfer characteristics; drain current as a function of gate-source voltage; typical values BUK7E3R5-60E Product data sheet Fig. 9. 60 120 T j (°C) 180 Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. 11 September 2012 0 © NXP B.V. 2012. All rights reserved 6 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET 003aah028 10-1 003aah445 15 ID (A) RDSon (mΩ ) 10-2 typ min 10-3 max 5.5 5 10 6 10-4 5 8 10-5 VGS (V) = 10 10-6 0 2 4 VGS (V) 0 6 Fig. 10. Sub-threshold drain current as a function of gate-source voltage 0 120 240 ID (A) 360 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values 003aag814 2.4 VDS a ID 1.8 VGS(pl) VGS(th) 1.2 VGS QGS1 0.6 QGS2 QGS QGD QG(tot) 003aaa508 0 -60 0 60 120 Tj (°C) Fig. 13. Gate charge waveform definitions 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 7 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET 003aaj711 10 003aaj712 104 VGS (V) Ciss C (pF) 8 14 V 6 103 VDS = 48V 4 Coss Crss 2 0 0 40 80 Q G (nC) 102 10-1 120 Fig. 14. Gate-source voltage as a function of gate charge; typical values 1 10 VDS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aaj713 360 IS (A) 240 Tj = 175° C 120 Tj = 25 ° C 0 0 0.3 0.6 0.9 V (V) 1.2 SD Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 8 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET 7. Package outline Plastic single-ended package (I2PAK); low-profile 3-lead TO-262 SOT226 A A1 E D1 mounting base D L1 Q b1 L 1 2 3 b e c e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D max D1 E e L L1 Q mm 4.5 4.1 1.40 1.27 0.85 0.60 1.3 1.0 0.7 0.4 11 1.6 1.2 10.3 9.7 2.54 15.0 13.5 3.30 2.79 2.6 2.2 OUTLINE VERSION SOT226 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 06-02-14 09-08-25 TO-262 Fig. 17. Package outline I2PAK (SOT226) BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 9 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 8. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 10 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 8.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 11 / 12 BUK7E3R5-60E NXP Semiconductors N-channel TrenchMOS standard level FET 9. Contents 1 1.1 1.2 1.3 1.4 Product profile ....................................................... 1 General description .............................................. 1 Features and benefits ...........................................1 Applications .......................................................... 1 Quick reference data ............................................ 1 2 Pinning information ............................................... 2 3 Ordering information ............................................. 2 4 Limiting values .......................................................2 5 Thermal characteristics .........................................4 6 Characteristics ....................................................... 5 7 Package outline ..................................................... 9 8 8.1 8.2 8.3 8.4 Legal information .................................................10 Data sheet status ............................................... 10 Definitions ...........................................................10 Disclaimers .........................................................10 Trademarks ........................................................ 11 © NXP B.V. 2012. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 September 2012 BUK7E3R5-60E Product data sheet All information provided in this document is subject to legal disclaimers. 11 September 2012 © NXP B.V. 2012. All rights reserved 12 / 12