CD4009UBMS Data Sheet November 1994 CMOS Hex Buffers/Converter Features CD4009UBMS Hex Buffer/Converter may be used as a CMOS to TTL or DTL logic-level converter or a CMOS highsink-current driver. • Inverting Type The CD4049UB is the preferred hex buffer replacement for the CD4009UBMS in all applications except multiplexers. For applications not requiring high sink current or voltage conversion, the CD4069UB Hex Inverter is recommended. File Number 3293 • High-Voltage Type (20V Rating) • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; - 10nA at 18V and +25oC The CD4009UBMS is supplied in these 16 lead outline packages: • 5V, 10V and 15V Parametric Ratings Braze Seal DIP H4S Frit Seal DIP H1E Ceramic Flatpack H3X Applications • CMOS To DTL/TTL Hex Converter • CMOS Current “Sink” or “Source” Driver • CMOS High-to-Low Logic-Level Converter • Multiplexer - 1 to 6 or 6 to 1 Pinout Functional Diagram CD4009UBMS TOP VIEW 3 2 G=A A VCC 1 16 VDD G=A 2 15 L = F 5 4 B H=B 14 F A 3 13 NC H=B 4 7 6 C B 5 I=C 12 K = E 11 E I=C 6 9 10 J = D C 7 9 D VSS 8 NC 13 1 VCC NC = NO CONNECTION 10 D J=D 11 12 E K=E 8 VSS 16 VDD 14 F 15 L=F NC = NO CONNECTION 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4009UBMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance. . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD TEMPERATURE MIN MAX UNITS 1 +25oC - 2 µA 2 +125oC - 200 µA 3 -55oC - 2 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current Input Leakage Current IIL IIH VIN = VDD or GND VIN = VDD or GND LIMITS GROUP A SUBGROUPS VDD = 20 VDD = 18V Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V 1 +25oC 3.0 - mA 1 +25oC 8.0 - mA Output Current (Sink) Output Current (Sink) IOL5 IOL10 VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 24.0 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.2 mA 1 +25oC - -0.8 mA 1 +25oC - -0.45 mA Output Current (Source) Output Current (Source) IOH5B IOH10 VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -1.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V 7 +25oC P Threshold Voltage Functional VPTH F VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.0 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 4.0 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 2.5 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 12.5 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs 2 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. CD4009UBMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Propagation Delay Transition Time Transition Time SYMBOL TPHL TPLH TTHL TTLH CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9 +25oC - 60 ns 10, 11 +125oC, -55oC - 81 ns 9 +25oC - 140 ns 10, 11 +125oC, -55oC - 189 ns 9 +25oC - 70 ns 10, 11 +125oC, -55oC - 95 ns 9 +25oC - 350 ns 10, 11 +125oC, -55oC - 473 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 2 -55oC, +25oC - 1 µA +125oC - 30 µA -55oC, +25oC - 2 µA +125oC - 60 µA -55oC, +25oC - 2 µA +125oC 1, 2 1, 2 - 120 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, 55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC 9.95 - V Output Current (Sink) IOL4 VDD = 4.5V, VOUT = 0.4V 1, 2 +25oC 2.6 - mA +125oC 1.8 - mA -55oC 3.2 - mA +125oC 2.1 - mA -55oC 3.75 - mA +125oC 5.6 - mA -55oC 10.0 - mA Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL 3 VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 +125oC 16.0 - mA -55oC 30.0 - mA +125oC - -0.15 mA -55oC - -0.25 mA +125oC - -0.58 mA -55oC - -1.0 mA +125oC - -0.33 mA -55oC - -0.55 mA +125oC - -1.1 mA -55oC - -1.65 mA +25oC, +125oC, 55oC - 2 V CD4009UBMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 55oC 8 - V Propagation Delay TPHL VDD = 10V, VCC = 10V 1, 2, 3 +25oC - 40 ns VDD = 15V, VCC = 15V 1, 2, 3 +25oC - 30 ns VDD = 10V, VCC = 10V 1, 2, 3 +25oC - 80 ns VDD = 15V, VCC = 15V 1, 2, 3 +25oC - 60 ns VDD = 10V, VCC = 5V 1, 2, 3 +25oC - 30 ns VDD = 15V, VCC = 5V 1, 2, 3 +25oC - 20 ns VDD = 10V, VCC = 5V 1, 2, 3 +25oC - 70 ns VDD = 15V, VCC = 5V 1, 2, 3 +25oC - 60 ns VDD = 10V 1, 2, 3 +25oC - 40 ns VDD = 15V 1, 2, 3 +25oC - 30 ns VDD = 10V 1, 2, 3 +25oC - 150 ns VDD = 15V 1, 2, 3 +25oC - 110 ns 1, 2 +25oC - 22.5 pF Propagation Delay Propagation Delay Propagation Delay Transition Time Transition Time Input Capacitance TPLH TPHL TPLH TTHL TTLH CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 20V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 7.5 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VPTH VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V, VCC = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 4 CD4009UBMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD CONFORMANCE GROUP GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test 1, 7, 9 1, 7, 9, Deltas IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group B 100% 5004 100% 5004 Group D Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 2, 4, 6, 10, 12, 13, 15 3, 5, 7 - 9, 11, 14 Static Burn-In 2 Note 1 2, 4, 6, 10, 12, 13, 15 8 1, 3, 5, 7, 9, 11, 14, 16 Dynamic Burn-In Note 1 13 8 1, 16 2, 4, 6, 10, 12, 13, 15 8 1, 3, 5, 7, 9, 11, 14, 16 Irradiation Note 2 9V ± -0.5V 50kHz 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 25kHz 1, 16 NOTE: 1. Each pin except VDD and Pin 1 and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and Pin 1 and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Schematic Diagram VDD VCC *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VDD P N P * INPUT VDD GND OUTPUT N CONFIGURATION: HEX COS/MOS TO DTL OR TTL CONVERTER (INVERTING) N VSS 5 VCC GND WIRING SCHEDULE: CONNECT VCC TO DTL OR TTL SUPPLY CONNECT VDD TO COS/MOS SUPPLY VSS CD4009UBMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC VI TA = -55oC SUPPLY VOLTS (VDD) = 15V 5 TEST CONDITION: VCC = 5V 4 15V 5V 3 10V 5V 2 OUTPUT VOLTS (VO) SUPPLY VOLTS (VDD) = 15V 4 15V 15V 3 10V 5V 5V 2 1 1 10V 2 4 6 8 10 12 INPUT VOLTS (VI) 14 0 FIGURE 1. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TYPICAL TEMPERATURE COEFFICIENT FOR ID = -0.3%/oC 100 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 80 60 10V 40 20 5V 2 4 2 4 6 8 10 12 DRAIN-TO-SOURCE VOLTS (VDS) GATE-TO-SOURCE VOLTAGE (VGS) = 15V 50 40 30 10V 20 10 5V -5 -4 -3 -2 -1 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -2 -3 -4 -5 -6 -7 -8 -9 -15V -10 -11 AMBIENT TEMPERATURE (TA) = +25oC -12 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 6 15 20 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0 -1 -10V 10 FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) -6 5 DRAIN-TO-SOURCE VOLTS (VDS) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -7 12 60 14 FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISITICS 10 AMBIENT TEMPERATURE (TA) = +25oC 0 0 8 6 INPUT VOLTS (VI) FIGURE 2. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS FUNCTION OF TEMPERATURE OUTPUT LOW (SINK) CURRENT (IOL) (mA) 0 OUTPUT LOW (SINK) CURRENT (IOL) (mA) 5 -7 -6 -5 -4 -3 -2 -1 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -2 -4 -10V -15V -6 -8 -10 AMBIENT TEMPERATURE (TA) = +25oC -12 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) OUTPUT VOLTS (VO) TA = +125oC MAX MIN VO FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME tPHL (ns) LOW-TO-HIGH PROPAGATION DELAY TIME (tPLH) (ns) CD4009UBMS AMBIENT TEMPERATURE (TA) = +25oC 120 SUPPLY VOLTAGE (VDD) = 5V 100 80 60 10V 15V 40 20 AMBIENT TEMPERATURE (TA) = +25oC 60 50 SUPPLY VOLTAGE (VDD) = 5V 40 10V 30 20 15V 10 0 0 20 40 60 80 100 20 HIGH-TO-LOW TRANSITION TIME tTHL (ns) 200 10V 15V 50 20 40 60 80 100 60 70 80 90 100 60 SUPPLY VOLTAGE (VDD) = 5V 50 40 10V 30 20 15V 10 0 0 50 AMBIENT TEMPERATURE (TA) = +25oC 250 SUPPLY VOLTAGE (VDD) = 5V 100 40 FIGURE 8. TYPICAL HIGH-TO-LOW PROPAGATION DELAY TIME vs LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC 150 30 LOAD CAPACITANCE (CL) (pf) LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL LOW-TO-HIGH PROPAGATION DELAY TIME vs LOAD CAPACITANCE LOW-TO-HIGH TRANSITION TIME (tTLH) (ns) 10 120 10 20 120 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (CL) (pf) LOAD CAPACITANCE (CL) (pF) FIGURE 9. TYPICAL LOW-TO-HIGH TRANSITION TIME vs LOAD CAPACITANCE FIGURE 10. TYPICAL HIGH-TO-LOW TRANSISTION TIME vs LOAD CAPACITANCE POWER PER INVERTER/BUFFER (µW) 104 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC 2 SUPPLY VOLTAGE (VCC) = 15V 1038 6 4 10V 10V 2 102 5V 8 6 4 LOAD CAPACITANCE (CL) = 50pF CL = 15pF 2 10 10 2 4 6 8 2 4 6 8 102 103 INPUT FREQUENCY (fφ) kHz 2 4 6 8 104 FIGURE 11. TYPICAL DISSIPATION CHARACTERISTICS 7 CD4009UBMS Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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