Si2316BDS Datasheet

Si2316BDS
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
30
RDS(on) (Ω)
ID (A)a
0.050 at VGS = 10 V
4.5
0.080 at VGS = 4.5 V
3.4
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• PWM Optimized
• 100 % Rg tested
• Compliant to RoHS Directive 2002/95/EC
Qg (Typ)
3.16 nC
APPLICATIONS
• Battery Switch
• DC/DC Converter
TO-236
(SOT-23)
G
1
3
S
D
2
Top View
Si2316DS (M6)*
*Marking Code
Ordering Information: Si2316BDS-T1-E3 (Lead (Pb)-free)
Si2316BDS-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Symbol
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Pulsed Drain Current
Continuous Source-Drain Diode Current
Maximum Power Dissipation
Limit
30
± 20
4.5
3.6
3.9b, c
3.13b, c
20
1.39
1.04b, c
1.66
1.06
1.25b, c
0.8b, c
- 55 to 150
ID
IDM
TC = 25 °C
TA = 25 °C
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
IS
PD
TJ, Tstg
Unit
V
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
≤5s
Maximum Junction-to-Ambientb, d
Maximum Junction-to-Foot (Drain)
Steady State
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 moard.
c. t = 5 s.
d. Maximum under Steady State conditions is 130 °C/W.
Document Number: 70445
S09-1503-Rev. B, 10-Aug-09
Symbol
RthJA
RthJF
Typical
80
60
Maximum
100
75
Unit
°C/W
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Si2316BDS
Vishay Siliconix
MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VDS
VDS = 0 V, ID = 250 µA
30
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
ΔVDS/TJ
ΔVGS(th)/TJ
ID = 250 µA
Gate-Source Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 µA
IGSS
Gate-Source Leakage
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
Forward Transconductancea
RDS(on)
gfs
V
23.92
mV/°C
5.2
3
V
VDS = 0 V, VGS = ± 20 V
± 100
nA
VDS = 30 V, VGS = 0 V
1
VDS = 30 V, VGS = 0 V, TJ = 55 °C
10
VDS ≥ 5 V, VGS = 10 V
1
20
µA
A
VGS = 10 V, ID = 3.9 A
0.041
0.050
VGS = 4.5 V, ID = 3.3 A
0.064
0.080
VDS = 15V, ID = 3.9 A
6
Ω
S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
350
65
VDS = 15 V, VGS = 0 V, f = 1 MHz
37
VDS = 15 V, VGS = 10 V, ID = 3.9 A
6.35
9.6
3.16
4.8
VDS = 15 V, VGS = 4.5 V, ID = 3.9 A
1.56
f = 1 MHz
2.6
3.9
4.5
6.75
11
16.5
12
18
tf
7
10.5
td(on)
20
30
65
98
11
17
23
35
tr
Turn-Off Delay Time
td(off)
Fall Time
Turn-On Delay Time
Rise Time
tr
Turn-Off Delay Time
td(off)
Fall Time
nC
1.1
td(on)
Rise Time
pF
VDD = 15 V, RL = 4.8 Ω
ID ≅ 3.13 A, VGEN = 10 V, RG = 1 Ω
VDD = 15 V, RL = 6.25 Ω
ID = 2.4 A, VGEN = 4.5 V, Rg = 1 Ω
tf
Ω
ns
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
a
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
TC = 25 °C
1.39
20
IS = 2.0 A
IF = 2.0 A, dI/dt = 100 A/µs, TJ = 25 °C
A
0.8
1.2
V
10
15
ns
4
6
nC
6.6
3.5
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 70445
S09-1503-Rev. B, 10-Aug-09
Si2316BDS
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
20
3
15
I D - Drain Current (A)
I D - Drain Current (A)
VGS = 10 V thru 5 V
10
VGS = 4 V
2
1
TJ = 25 °C
5
TJ = 125 °C
VGS = 3 V
0
1
2
3
4
0
5
1
2
3
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.20
0.16
5
24
30
400
VGS = 4.5 V
0.12
0.08
300
Ciss
200
Coss
VGS = 10 V
0.04
100
0.00
Crss
0
0
4
8
12
16
20
0
6
12
18
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
1.8
10
ID = 3.9 A
VGS = 10 V, I D = 3.9 A
1.6
8
RDS(on) - On-Resistance
(Normalized)
VGS - Gate-to-Source Voltage (V)
4
500
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
TJ = - 55 °C
0
0
VDS = 16 V
6
VDS = 24 V
4
2
1.4
1.2
VGS = 4.5 V, ID = 3.3 A
1.0
0.8
0
0
2
4
6
8
0.6
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 70445
S09-1503-Rev. B, 10-Aug-09
150
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Si2316BDS
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.12
100
RDS(on) - On-Resistance (Ω)
ID = 4.1 A
I S - Source Current (A)
10
TJ = 150 °C
1
TJ = 25 °C
0.1
0.01
0.0
0.09
TA = 125 °C
0.06
0.03
TA = 25 °C
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
2
4
8
10
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
2.6
10
2.4
8
2.2
ID = 250 µA
2.0
TA = 25 °C
Single Pulse
6
Power (W)
VGS(th) (V)
6
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
4
1.8
2
1.6
1.4
- 50
- 25
0
25
50
75
100
125
0
0.01
150
1
0.1
10
100
600
Time (s)
TJ - Temperature ( C)
Threshold Voltage
Single Pulse Power
100
RDS(on) Limited*
I D - Drain Current (A)
10
10 ms
1
100 ms
1s
10 s
0.1
DC
0.01
TA = 25 °C
Single Pulse
0.001
0.1
1
*VGS
10
100
VDS - Drain-to-Source Voltage (V)
minimum VGS at which RDS(on) is specified
Safe Operating Area
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Document Number: 70445
S09-1503-Rev. B, 10-Aug-09
Si2316BDS
Vishay Siliconix
5
2.0
4
1.6
3
1.2
Power
ID - Drain Current (A)
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
0.8
1
0.4
0
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TC - Case Temperature (°C)
TC - Case Temperature (°C)
Current Derating*
Power Derating, Junction-to-Foot
*The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = R thJA = 130 °C/W
3. T JM
Single Pulse
0.01
10- 4
10- 3
TA = PDMZthJA(t)
4. Surface Mounted
10- 2
10- 1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70445.
Document Number: 70445
S09-1503-Rev. B, 10-Aug-09
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Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E1
1
E
2
e
S
e1
D
0.10 mm
C
0.004"
A2
A
C
q
Gauge Plane
Seating Plane
Seating Plane
C
A1
Dim
0.25 mm
L
L1
MILLIMETERS
Min
INCHES
Max
Min
Max
0.044
A
0.89
1.12
0.035
A1
0.01
0.10
0.0004
0.004
A2
0.88
1.02
0.0346
0.040
b
0.35
0.50
0.014
0.020
c
0.085
0.18
0.003
0.007
D
2.80
3.04
0.110
0.120
E
2.10
2.64
0.083
0.104
E1
1.20
1.40
0.047
e
0.95 BSC
e1
L
1.90 BSC
0.40
L1
q
0.0748 Ref
0.60
0.016
0.64 Ref
S
0.024
0.025 Ref
0.50 Ref
3°
0.055
0.0374 Ref
0.020 Ref
8°
3°
8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
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1
AN807
Vishay Siliconix
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1. Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
Document Number: 70739
26-Nov-03
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
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Application Note 826
Vishay Siliconix
0.049
(1.245)
0.029
0.022
(0.559)
(0.724)
0.037
(0.950)
(2.692)
0.106
RECOMMENDED MINIMUM PADS FOR SOT-23
0.053
(1.341)
0.097
(2.459)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index Return to Index
APPLICATION NOTE
Document Number: 72609
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000