HI2301 ® January 1998 Features NS ESIG D NEW at OR F D nt e r c E e D 2 C MEN e HI230upport com/ts 8-Bit, 30 MSPS, Video C OM S e ic a l S E rsil. R n i nt e . h c w N OT e A/D Converter with Amplifier/Clamp r ww ur T c t o R S IL o a t n co TE 8 - IN 1-88 Description • Resolution . . . . . . . . . . . . . . . . . . .8-Bit ±0.5 LSB (DNL) • Maximum Sampling Frequency . . . . . . . . . . . 30 MSPS • Low Power Consumption, 120mW (Including Reference Current) • Standby Function • Amplifier Functions The HI2301 is an 8-bit CMOS analog-to-digital converter for video use that features a sync clamp function and on-chip amplifier. The adoption of a 2-step parallel method realizes low power consumption and a maximum conversion speed of 30 MSPS. Ordering Information - Built-In 3x Amplifier (15MHz Band) PART NUMBER - 2-Input Selector Function Provided • Built-In Input Clamp Function (DC Restore) HI2301JCQ TEMP. RANGE ( oC) -20 to 75 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S • Clamp ON/OFF Function • Internal Voltage Reference • Three-State TTL Compatible Output • Power Supply . . . . . . . . . +5V Single or +4.75/3.3V Dual • Direct Replacement for Sony CXD2301 Applications • Desktop Video • Multimedia • Video Digitizing • Image Scanners Pinout AVDD VIN1 VIN2 ADIN AVSS OPO CCP AVSS HI2301 (MQFP) TOP VIEW ADV SEL 4 21 ADV CE 5 20 CLP CLE 6 19 TEST AVSS 7 18 CLK DVSS 8 17 9 10 11 12 13 14 15 16 VREF DVDD D0 D1 22 D2 VRT 3 D3 23 AVSS D4 2 D5 AVSS 32 31 30 29 28 27 26 25 24 D6 1 D7 VRB CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 4-1 File Number 4104.2 HI2301 Functional Block Diagram VIN2 VIN1 27 25 SEL 4 CE 5 ADV ADV AVDD 30 21 22 26 3R R TEST (DVSS) 19 OPO - R + RTS 23 VRT VBI REFERENCE SUPPLY 1 VRB D0 (LSB) 16 D1 15 LOWER DATA LATCH D2 14 D3 13 D4 12 LOWER SAMPLING COMPARATOR (4-BIT) LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) 29 ADIN 2 AVSS UPPER DATA LATCH D5 11 D6 10 D7 (MSB) LOWER ENCODER (4-BIT) 3 AVSS UPPER ENCODER (4-BIT) UPPER SAMPLING COMPARATOR (4-BIT) 7 AVSS ADV 28 AVSS 9 31 AVSS CLK 18 CLOCK GENERATOR DVDD 17 DVSS - A/D CONVERTER BLOCK 8 + 24 VREF 6 20 32 CLE CLP CCP Pin Descriptions PIN NO. SYMBOL 1 VRB 23 V RT EQUIVALENT CIRCUIT Reference voltage (bottom) connect to AVSS for normal use. When another external voltage is input, connect an external 0.1µF capacitor and retain a 1.5V differential compared to the top reference voltage. AVDD 23 RTS DESCRIPTION RREF 1 Reference voltage (top) by setting VRB to AVSS , outputs approximately 1.5V. Connect only a 0.1µF external by-pass capacitor for normal use. When another external voltage is input, it must be 2.2V or lower. AVSS 2, 3, 7, 28, 31 AVSS Analog GND. 4-2 HI2301 Pin Descriptions (Continued) PIN NO. SYMBOL 4 SEL 5 CE 19 TEST EQUIVALENT CIRCUIT DESCRIPTION Switches the input of the 3x amplifier. When SEL is at Low level, VIN1 is selected. When SEL is at High level, VIN2 is selected. AVDD 4 Standby function ON/OFF selector. In standby state when High. 5 19 Fix to VSS for normal use. DVSS AVSS 6 CLE When CLE = Low: Clamp function is enabled. When CLE = High: Clamp function is disabled, and only the normal A/D converter function is enabled. AVDD 6 18 18 CLK 20 CLP 8 DV SS 9 to 16 D7 to D 0 Clock Input. 20 AVSS Inputs the clamp pulse to Pin 20 (CLP). Clamps the High interval signal voltage. CE Digital GND. D7 (MSB) to D 0 (LSB) output. Outputs Low level in standby. In operation, the phase of D7 to D0 output is inverted against the phase of ADIN. DI 17 DVDD 21 ADV 5V or 3.3V Short Pins 21 and 22, and connect 0.1µF external capacitor. AVDD CE 21 AVSS 22 ADV AVDD 22 AVSS 24 V REF Clamp reference voltage input. Clamps so that the reference voltage and the clamp interval ADIN input signal are equal. The reference voltage is more than 0.5V. AVDD 24 AVSS 4-3 HI2301 Pin Descriptions (Continued) PIN NO. SYMBOL 25 VIN1 27 VIN2 EQUIVALENT CIRCUIT DESCRIPTION Amplifier input pin. Biased internal at 1.9V (when AVDD = 5V) or at 1.8V (when AVDD = 4.75V). When standby as well. When SEL is at Low level, VIN1 is selected for input; when SEL is at High level, VIN2 is selected for input. AVDD R11 R 200 25 27 R12 AVSS 26 AVDD 29 ADIN 5V or 4.75V A/D converter block analog input. AVDD 29 AVSS 30 OPO Amplifier Output. The phase of this output is inverted against the phase of VIN1 , 2 . In standby mode, it becomes high-impedance output condition. AVDD 30 AVSS 32 CCP Integrates the clamp control voltage. The relationship between the CCP voltage variation and the ADIN voltage is positive phase. AVDD 32 AVSS The following table shows the status of the digital output pins when the TEST pin is used with the CE and SEL pins. ADIN DIGITAL OUTPUT CODE TEST CE SEL D1 D2 D3 D4 D5 D6 D7 D8 INPUT SIGNAL VOLTAGE L L X D1 D2 D3 D4 D5 D6 D7 D8 VRT 0 L • • • • • • • L L L L L L L STEP MSB 0 0 LSB 0 0 0 0 0 0 L H X H L X H H L H L H L H L H L • • H H H L H L H L H L H • 127 0 1 1 1 1 1 1 1 • 128 1 0 0 0 0 0 0 0 • • • • • • 1 1 1 1 TEST MODE Digital Output The following table shows the correlation between the ADIN input voltage and the digital output code. Take notice that the phase of ADIN input signal voltage is inverted against the phase of the digital output. 4-4 • • V RB 255 • 1 1 1 1 HI2301 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage (VRT , VRB) . . . . . . . . . . . VDD 0.5 to VSS -0.5V Input Voltage, Analog (VIN) . . . . . . . . . . . . . . VDD 0.5 to VSS -0.5V Input Voltage, Digital (VIH , VIL) . . . . . . . . . . . VDD 0.5 to VSS -0.5V Output Voltage, Digital (V OH , VOL) . . . . . . . . VDD 0.5 to VSS -0.5V Thermal Resistance (Typical, Note 1) Operating Conditions θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (Lead Tips Only) Supply Voltage (IDVSS - AVSSI) . . . . . . . . . . . . . . . . . . 0 to 100mV Single Power Supply (AVDD , DVDD) . . . . . . . . . . . . . . . . 5.0 ±0.25V Dual Power Supply (AVDD) . . . . . . . . . . . . . . . . . . . . . . 4.75 ±0.25V (DVDD) . . . . . . . . . . . . . . . . . . . . . . . . 3.3 ±0.3V Reference Input Voltage (V RB) . . . . . . . . . . . . . . . . . . . . 0V to 2.2V (VRT) . . . . . . . . . . . . . . . . . . . . 0V to 2.2V Analog Input (ADIN) . . . . . . . . . . . . . . . . . . . . . . More than 1.2VP-P Clock Pulse width, tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . 16ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . 16ns (Min) Temperature Range (TOPR). . . . . . . . . . . . . . . . . . . . . . -20 to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Electrical Specifications; When using a single power supply (fC = 30 MSPS, AV DD = DVDD = +5V, VRB = 0V, VRT = 1.5V, TA = 25oC PARAMETER Supply Current Standby Supply Current SYMBOL TEST CONDITIONS IAD + IDD fC = 35 MSPS, NTSC Ramp Wave Input ISTB CE = DVDD TYP MAX UNITS - 27 35 mA - 130 200 µA 30 - - MSPS Max Conversion Rate fC Max Min Conversion Rate fC Min - - 0.5 MSPS BW - 20 - MHz - 8 - pF 230 330 440 Ω 1.38 1.52 1.66 V ADIN Input Band (At -1dB) ADIN Input Capacitance CADIN Reference Resistance (V RT to VRB) R REF VIN = 0V to 1.5V, fIN = 1kHz Ramp MIN VIN = 0.75V + 0.07VRMS Self Bias V RT Offset Voltage EOT -40 -20 0 mV EOB +25 +45 +65 mV V IH 3.5 - - V Digital Input Voltage VRB = AVSS VIL Digital Input Current IIH DV DD = Max IIL Digital Output Current IOH DV DD = Min IOL - - 0.5 V VIH = VDD - - 5 µA VIL = 0V - - 5 µA VOH = VDD - 0.5V -1.1 -2.5 - mA VOL = 0.4V 3.7 6.5 - mA Output Data Delay tDL With TTL 1 Gate and 10pF Load 7 13 25 ns Integral Nonlinearity Error EL fC = 30 MSPS, VIN = 0V To 1.5V - +0.5 +1.3 LSB Differential Gain Error DG NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS - 1 - % Differential Phase Error DP - 0.5 - Degrees Aperture Jitter tAJ - 30 - ps Sampling Delay tSD - 2 - ns Clamp Offset Voltage EOC VREF = 0.5V 0 +20 +40 mV VREF = 1.5V -40 -20 0 mV VADIN = DC PWS = 3µ 4-5 HI2301 Electrical Specifications Electrical Specifications; When using a single power supply (fC = 30 MSPS, AV DD = DVDD = +5V, VRB = 0V, VRT = 1.5V, TA = 25oC (Continued) PARAMETER SYMBOL Clamp Pulse Delay TEST CONDITIONS tCPD Amplifier Gain DC To 15MHz TYP MAX UNITS - 25 - ns 8.5 9.5 10.5 dB - 1.9 - V VIN1 and V IN2 Bias Voltage VBI1, 2 VIN1 and V IN2 Input Resistance RI1, 2 19 27 35 kW VIN1 and V IN2 Input Capacitance CI1, 2 - 15 - pF Electrical Specifications When Open MIN When Using a Dual Power Supply (fC = 30 MSPS, AV DD = DVDD = +5V, VRT = 1.5V, VRT = 1.5V, TA = 25oC (2) When Using A Dual Power Supply fC = 30 MSPS, AVDD = 4.75V, DVDD = 0V, VRT = 1.5V, TA = 25oC Analog Supply Current IAD fC = 30 MSPS, NTSC Ramp Wave Input - 24 32 mA Digital Supply Current IDD fC = 30 MSPS, NTSC Ramp Wave Input - 1 2 mA Standby Supply Current ISTB CE = DVDD - 130 200 µA 30 - - MSPS - - 0.5 MSPS - 20 - MHz - 8 - pF 230 330 440 Ω 1.44 1.52 1.6 V Maximum Conversion Rate fC Max Minimum Conversion Rate fC Min ADIN Input Band (at -1dB) BW ADIN Input Capacitance CADIN Referenced Resistance (VRT to VRB ) RREF VIN = 0 to 1.5V fIN = 1kHz Ramp VIN = 0.75V + 0.07VRMS Self Bias VRT Offset Voltage EOT -40 -20 0 mV EOB +25 +45 +65 mV VIH 2.5 - - V VIL - - 0.5 V VIH = DVDD - - 5 µA VIL = 0V - - 5 µA VOH = VDD -0.5V -1.1 -2.5 - mA IOL VOL = 0.4V 3.7 6.5 - mA Output Data Delay tDL With TTL 1 Gate and 10pF Load 7 13 25 ns Integral Nonlinearity Error EL fC = 30 MSPS, VIN = 0 to 1.5V - +0.5 +1.3 LSB Differential Nonlinearity Error ED fC = 30 MSPS, VIN = 0 to 1.5V - ±0.3 ±0.5 LSB Differential Gain Error DG NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS - 1 - % Differential Phase Error DP - 0.5 - deg Aperture Jitter tAJ - 30 - ps Sampling delay tSD - 2 - ns Clamp Offset Voltage E OC VREF = 0.5V 0 +20 +40 mV V REF = 1.5V -40 -20 0 mV - 25 - ns 8.5 9.5 10.5 dB - 1.8 - V Digital Input Voltage Digital Input Current IIH VRB = AVSS DVDD = Max IIL Digital Output Current Clamp Pulse Delay IOH DVDD = Min VIN = DC PWS = 3µs tCPD 3x Amplifier Gain DC to 15MHz VIN1 and V IN2 Bias Voltage VBI1, 2 VIN1 and V IN2 Input Resistance RI1, 2 19 27 35 kΩ VIN1 and V IN2 Input Capacitance CI1, 2 - 15 - pF When Open 4-6 HI2301 Timing Chart tPW1 tPW0 CLOCK 2V ADIN INPUT N N+1 N-3 DATA OUTPUT N+2 N-2 N+1 N+3 N+4 N N-1 tD Application Circuits AC04 CLOCK IN +3.3V LATCH CK (NOTE 2) Q CLAMP PULSE IN +4.75V 0.1µ 0.1µ 0.1µ VREF 20K 24 0.1µ 0.1µ VIDEO IN 75 0.1µ 10p 0.1µ 23 22 21 20 19 18 17 25 16 D0 26 15 D1 27 14 D2 28 13 D3 29 12 D4 30 11 D5 31 10 D6 32 9 D7 1 2 3 4 GND (ANALOG) 5 6 7 8 GND (DIGITAL) NOTE: 2. Although the ADC sampling clock latches the clamp pule, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small beat might be generated as VSAG . The latch circuit is valid at this time. FIGURE 1. CLAMP USAGE EXAMPLE (USING SELF BIAS, CIRCUIT WHEN USING THE INTERNAL AMPLIFIER) 4-7 HI2301 Application Circuits (Continued) +3.3V ACO4 IN CLOCK IN 0.1µ 0.1µ 0.1µ +4.75V VIDEO IN1 24 VIDEO IN2 0.1µ 0.1µ 75 0.1µ 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 1 2 3 4 5 6 7 CLAMP LEVEL SETTING DATA SUBTRACTER, COMPARATOR, ETC. 8 DAC, PWM, ETC. GND (ANALOG) GND (DIGITAL) HIGH IMPEDANCE FOR ALL INFORMATION OUTSIDE THE CLAMP INTERVAL NOTES: 3. The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is position phase. 4. ∆ADIN/∆VCCP = 3.0 (fS = 30 MSPS). FIGURE 2. DIGITAL CLAMP USAGE EXAMPLE (USING SELF BIAS), CIRCUIT WHEN USING THE INTERNAL AMPLIFIER 4-8 HI2301 Application Circuits (Continued) 0.1µ ACO4 +3.3V (DIGITAL) 0.1µ 0.1µ CLOCK IN VIDEO IN 24 0.1µ +4.75V 0.1µ 75 0.1µ 10p 23 22 21 20 19 18 17 25 16 D0 26 15 D1 27 14 D2 28 13 D3 29 12 D4 30 11 D5 31 10 D6 32 9 D7 0.1µ 1 2 3 4 5 6 7 8 GND (DIGITAL) GND (ANALOG) +3.3V (DIGITAL) FIGURE 3. WHEN NOT USING THE CLAMP, CIRCUIT WHEN USING THE INTERNAL AMPLIFIER 4-9 HI2301 Application Circuits (Continued) +4.75V 20K ACO4 0.1µ 0.1µ +3.3V (DIGITAL) CLOCK IN CLAMP PULSE IN LATCH 0.1µ CK Q (NOTE 5) 24 23 22 21 20 19 18 17 +4.75V (ANALOG) 0.1µ VIDEO IN (NOTE 6) 10µ 75 10p 0.01µ 25 16 D0 26 15 D1 27 14 D2 28 13 D3 29 12 D4 30 11 D5 31 10 D6 32 9 D7 1 2 3 4 GND (ANALOG) 5 6 7 8 GND (DIGITAL) NOTES: 5. Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small abeat might be generated as VSAG . The latch circuit is valid at this time. 6. Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to “Digital Output”.) FIGURE 4. CLAMP USAGE EXAMPLE WHEN NOT USING THE INTERNAL AMPLIFIER 4-10 HI2301 Application Circuits (Continued) 0.1µ AC04 +3.3V (DIGITAL) 0.1µ 0.1µ CLOCK IN 24 +4.75V (ANALOG) 0.1µ VIDEO IN (NOTE 9) 10µ 75 10p 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 1 2 3 4 5 6 7 CLAMP LEVEL SUBTRACTER, SETTING DATA COMPARATOR, ETC. 8 0.01µ GND (ANALOG) GND (DIGITAL) DAC, PWM, ETC. HIGH IMPEDANCE FOR ALL INFORMATION OUTSIDE THE CLAMP INTERVAL NOTES: 7. The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is positive phase. 8. ∆VADIN /∆VCCP = 3.0 (fS = 20 MSPS). 9. Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to “Digital Output.”) FIGURE 5. DIGITAL CLAMP USAGE EXAMPLE 4-11 Application Circuits (Continued) 0.1µ ACOA +3.3V (DIGITAL) 0.1µ CLOCK IN 0.1µ 24 +4.75V (ANALOG) 0.1µ VIDEO IN (NOTE 10) 23 22 21 20 19 18 17 25 16 D0 26 15 D1 27 14 D2 28 13 D3 29 12 D4 30 11 D5 31 10 D6 32 9 D7 75 10P 1 2 3 4 5 6 7 8 GND (DIGITAL) GND (ANALOG) +3.3V (DIGITAL) NOTE: 10. Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to “Digital Output”.) FIGURE 6. WHEN NOT USING THE CLAMP Typical Performance Curves -10 CROSSTALK (dB) CURRENT CONSUMPTION (mA) VDD = 4.75V VIN = 150mVRMS VIN1 = GND -20 -30 -40 -50 -60 -70 -80 1 5 10 fIN , INPUT FREQUENCY (MHz) 40 30 20 50 VDD = 5V INPUT WAVEFORM IS RAMP WAVE VIN = 150mVRMS 0.1 0.5 1 5 10 50 fIN , INPUT FREQUENCY (MHz) FIGURE 7. INPUT FREQUENCY OF VIN2 vs CROSSTALK VIN2 → VIN1 FIGURE 8. INPUT FREQUENCY vs CURRENT CONSUMPTION 4-12 CURRENT CONSUMPTION (mA) Typical Performance Curves fIN = NTSC RAMP WAVE VIN = 150mVRMS 30 20 0.1 0.5 1 5 10 fS , SAMPLING FREQUENCY (MHz) FIGURE 9. SAMPLING FREQUENCY vs CURRENT CONSUMPTION 4-13