HI5812 Semiconductor CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold August 1997 Features Description • Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µs The HI5812 is a fast, low power, 12-bit, successive approximation analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws just 1.9mA when operating at 5V. The HI5812 features a built-in track and hold. The conversion time is as low as 15µs with a 5V supply. • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .50 KSPS • Built-In Track and Hold • Guaranteed No Missing Codes Over Temperature • Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V • Maximum Power Consumption. . . . . . . . . . . . . . .25mW • Internal or External Clock The twelve data outputs feature full high speed CMOS threestate bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable: (i.e.) 12bit, 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag, and conversion-start inputs complete the digital interface. An internal clock is provided and is available as an output. The clock may also be over-driven by an external source. Applications • Remote Low Power Data Acquisition Systems Ordering Information • Digital Audio • DSP Modems PART NUMBER • General Purpose DSP Front End INL (LSB) (MAX OVER TEMP.) TEMP. RANGE (oC) PACKAGE PKG. NO. • µP Controlled Measurement System HI5812JIP ±1.5 -40 to 85 24 Ld PDIP E24.3 • Professional Audio Positioner/Fader HI5812KIP ±1.0 -40 to 85 24 Ld PDIP E24.3 HI5812JIB ±1.5 -40 to 85 24 Ld SOIC M24.3 HI5812KIB ±1.0 -40 to 85 24 Ld SOIC M24.3 HI5812JIJ ±1.5 -40 to 85 24 Ld CERDIP F24.3 HI5812KIJ ±1.0 -40 to 85 24 Ld CERDIP F24.3 Pinout HI5812 (PDIP, CERDIP, SOIC) TOP VIEW DRDY 1 (LSB) D0 2 24 VDD 23 OEL D1 3 22 CLK D2 4 21 STRT D3 5 20 VREF - D4 6 19 VREF+ D5 7 18 VIN D6 8 17 VAA+ D7 9 16 VAA- D8 10 15 OEM D9 11 14 D11 (MSB) VSS 12 13 D10 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 6-1789 File Number 3214.4 HI5812 Functional Block Diagram STRT VDD TO INTERNAL LOGIC VSS VIN CONTROL + TIMING CLOCK CLK DRDY 32C OEM VREF+ 16C D11 (MSB) 50Ω SUBSTRATE 8C D10 4C 2C D9 C D8 VAA+ VAA- 64C 63 32C D7 16C 8C P1 12-BIT SUCCESSIVE APPROXIMATION REGISTER 12-BIT EDGE TRIGGERED “D” LATCHED D6 4C D5 2C D4 C D3 C D2 D1 VREF D0 (LSB) OEL 6-1790 HI5812 Absolute Maximum Ratings Thermal Information Supply Voltage VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V) VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V Analog and Reference Inputs VIN , VREF+, VREF-. . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V) Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V) Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 60 12 PDIP Package . . . . . . . . . . . . . . . . . . . 80 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 75 N/A Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65οC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 750kHz, Unless Otherwise Specified 25oC PARAMETER TEST CONDITIONS MIN TYP -40oC TO 85oC MAX MIN MAX UNITS ACCURACY Resolution Integral Linearity Error, INL (End Point) Differential Linearity Error, DNL Gain Error, FSE (Adjustable to Zero) Offset Error, VOS (Adjustable to Zero) 12 - - 12 - Bits J - - ±1.5 - ±1.5 LSB K - - ±1.0 - ±1.0 LSB J - - ±2.0 - ±2.0 LSB K - - ±1.0 - ±1.0 LSB J - - ±3.0 - ±3.0 LSB K - - ±2.5 - ±2.5 LSB J - - ±2.0 - ±2.0 LSB - - ±1.0 - ±1.0 LSB 0.1 0.1 ±0.5 ±0.5 ±0.5 ±0.5 LSB LSB K Power Supply Rejection, PSRR Offset Error PSRR Gain Error PSRR VREF = 4V VDD = VAA+ = 5V ±5% VDD = VAA+ = 5V ±5% DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal RMS Noise Total Harmonic Distortion, THD Spurious Free Dynamic Range, SFDR J fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 68.8 69.2 - - - dB dB K fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 71.0 71.5 - - - dB dB J fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 70.5 71.1 - - - dB dB K fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 71.5 72.1 - - - dB dB J fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - -73.9 -73.8 - - - dBc dBc K fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz -80.3 -79.0 - - - dBc dBc J fS =Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - -75.4 -75.1 - - - dB dB K fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - -80.9 -79.6 - - - dB dB 6-1791 HI5812 Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 750kHz, Unless Otherwise Specified (Continued) 25oC PARAMETER TEST CONDITIONS -40oC TO 85oC MIN TYP MAX MIN MAX UNITS µA ANALOG INPUT Input Current, Dynamic At VIN = VREF+, 0V - ±50 ±100 - ±100 Input Current, Static Conversion Stopped - ±0.4 ±10 - ±10 µA Input Bandwidth -3dB - 1 - - - MHz Reference Input Current - 160 - - - µA Input Series Resistance, RS In Series with Input CSAMPLE - 420 - - - Ω Input Capacitance, CSAMPLE During Sample State - 380 - - - pF Input Capacitance, CHOLD During Hold State - 20 - - - pF 2.4 - - 2.4 - V DIGITAL INPUTS OEL, OEM, STRT High-Level Input Voltage, VIH Low-Level Input Voltage, VIL Input Leakage Current, IIL Except CLK, VIN = 0V, 5V Input Capacitance, CIN - - 0.8 - 0.8 V - - ±10 - ±10 µA - 10 - - - pF 4.6 - - 4.6 - V DIGITAL OUTPUTS High-Level Output Voltage, VOH ISOURCE = -400µA Low-Level Output Voltage, VOL ISINK = 1.6mA - - 0.4 - 0.4 V Three-State Leakage, IOZ Except DRDY, VOUT = 0V, 5V - - ±10 - ±10 µA Output Capacitance, COUT Except DRDY - 20 - - - pF High-Level Output Voltage, VOH ISOURCE = -100µA (Note 2) 4 - - 4 - V Low-Level Output Voltage, VOL ISINK = 100µA (Note 2) - - 1 - 1 V Input Current CLK Only, VIN = 0V, 5V - - ±5 - ±5 mA 20 - - 20 - µs Internal Clock, (CLK = Open) 200 300 400 150 500 kHz External CLK (Note 2) 0.05 2 1.5 0.05 1.5 MHz External CLK (Note 2) 100 - - 100 - ns CLOCK TIMING Conversion Time (tCONV + tACQ) (Includes Acquisition Time) Clock Frequency Clock Pulse Width, tLOW, tHIGH Aperture Delay, tDAPR (Note 2) - 35 50 - 70 ns Clock to Data Ready Delay, tD1DRDY (Note 2) - 105 150 - 180 ns Clock to Data Ready Delay, tD2DRDY (Note 2) - 100 160 - 195 ns Start Removal Time, tRSTRT (Note 2) 75 30 - 75 - ns Start Setup Time, tSUSTRT (Note 2) 85 60 - 100 - ns Start Pulse Width, tWSTRT (Note 2) 10 4 - 15 - ns Start to Data Ready Delay, tD3 DRDY (Note 2) - 65 105 - 120 ns Clock Delay from Start, tDSTRT (Note 2) - 60 - - - ns Output Enable Delay, tEN (Note 2) - 20 30 - 50 ns Output Disabled Delay, tDIS (Note 2) - 80 95 - 120 ns - 1.9 5 - 8 mA POWER SUPPLY CHARACTERISTICS Supply Current, IDD + IAA NOTE: 2. Parameter guaranteed by design or characterization, not production tested. 6-1792 HI5812 Timing Diagrams 1 5 - 14 4 3 2 15 1 2 3 CLK (EXTERNAL OR INTERNAL) tLOW tD1DRDY tHIGH STRT tD2DRDY DRDY DATA N - 1 D0 - D11 DATA N HOLD N VIN TRACK N TRACK N + 1 OEL = OEM = VSS FIGURE 1. CONTINUOUS CONVERSION MODE 15 2 1 2 2 3 4 5 CLK (EXTERNAL) tSUSTRT tRSTRT tWSTRT STRT tD3DRDY DRDY HOLD VIN HOLD TRACK FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK 6-1793 HI5812 Timing Diagrams (Continued) 15 1 2 3 4 5 CLK (INTERNAL) tRSTRT tDSTRT tWSTRT STRT DON’T CARE tD3DRDY DRDY HOLD HOLD TRACK VIN FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK OEL OR OEM 1.6mA tDIS tEN 90% 50% D0 - D3 OR D4 - D11 HIGH IMPEDANCE TO HIGH HIGH IMPEDANCE TO LOW TO OUTPUT PIN +2.1V 50pF 50% -1.6mA 10% FIGURE 4B. FIGURE 4A. FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM 1.6mA +2.1V 50pF -400µA FIGURE 5. GENERAL TIMING LOAD CIRCUIT 6-1794 HI5812 Typical Performance Curves 1.0 1.5 VDD = VAA+ = 5V VREF+ = 4.608V VDD = VAA+ = 5V, VREF+ = 4.608V VOS ERROR (LSBs) C 0.75 INL ERROR (LSBs) A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz B 0.5 A 0.25 1 C 0.5 A A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz 0 B 0 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 TEMPERATURE (oC) FIGURE 6. INL vs TEMPERATURE 40 60 80 100 2 C VDD = VAA+ = 5V, VREF+ = 4.608V 0.75 140 VDD = VAA+ = 5V, TA = 25oC CLK = 750kHz ERROR (LSBs) 1.5 B 0.5 A 0.25 FSE 1 DNL 0.5 INL A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz VOS 0 0 -60 -40 -20 0 20 40 60 80 100 120 3 140 3.2 TEMPERATURE (oC) 3.6 3.8 4 4.2 4.4 4.6 FIGURE 9. ACCURACY vs REFERENCE VOLTAGE 2 0.5 A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz VDD = VAA+ = 5V, VREF+ = 4.608V 3.4 REFERENCE VOLTAGE, VREF (V) FIGURE 8. DNL vs TEMPERATURE 1.5 VDD = VAA+ = 5V ±5% CLK = 750kHz VREF+ = 4.0V 0.375 C PSRR (LSBs) FSE ERROR (LSBs) 120 FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE 1.0 DNL ERROR (LSBs) 20 TEMPERATURE (oC) 1 B 0.5 0.25 0.125 PSRR VOS A PSRR FSE 0 0 -60 -40 -20 0 20 40 60 80 100 120 -60 140 TEMPERATURE (oC) FIGURE 10. FULL SCALE ERROR vs TEMPERATURE -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) FIGURE 11. POWER SUPPLY REJECTION vs TEMPERATURE 6-1795 HI5812 Typical Performance Curves (Continued) 8 6 AMPLITUDE (dB) SUPPLY CURRENT, IDD (mA) 7 5 4 INTERNAL CLOCK 3 2 1 0 -60 -40 -20 0 20 40 INPUT FREQUENCY = 1kHz SAMPLING RATE = 50kHz SNR = 72.1dB SINAD = 71.4dB EFFECTIVE BITS = 11.5 THD = -79.1dBc PEAK NOISE = -80.9dB SFDR = -80.9dB 0.0 -10.0 -20.0 -30.0 VDD = VAA+ = 5V, VREF+ = 4.608V 60 80 100 120 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -110.0 -120.0 -130.0 -140.0 140 0 500 1000 FREQUENCY BINS TEMPERATURE (oC) FIGURE 12. SUPPLY CURRENT vs TEMPERATURE 2000 FIGURE 13. FFT SPECTRUM 500 12 VDD = VAA+ = 5V, VREF+ = 4.608V 450 11 400 ENOB (BITS) INTERNAL CLOCK FREQUENCY (kHz) 1500 350 300 10 9 VREF+ = 4.608V TA = 25oC 8 A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz 250 200 B VDD = VAA+ = 5V C A 7 150 -60 -40 -20 0 20 40 60 80 100 120 140 0.1 TEMPERATURE (oC) 1 10 100 INPUT FREQUENCY (kHz) FIGURE 14. INTERNAL CLOCK FREQUENCY vs TEMPERATURE FIGURE 15. EFFECTIVE BITS vs INPUT FREQUENCY 75 -80 70 B VDD = VAA+ = 5V VREF+ = 4.608V TA = 25oC -60 SNR (dBc) THD (dBc) -70 A A. CLK =INTERNAL B. CLK = 750kHz C. CLK = 1MHz 65 C VDD = VAA+ = 5V VREF+ = 4.608V TA = 25oC 60 A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz B 55 C A -50 50 0.1 1 10 100 INPUT FREQUENCY (kHz) 0.1 1 10 100 INPUT FREQUENCY (kHz) FIGURE 16. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY FIGURE 17. SIGNAL NOISE RATIO vs INPUT FREQUENCY 6-1796 HI5812 During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto-balanced at the capacitor common node. TABLE 1. PIN DESCRIPTIONS PIN NO. NAME 1 DRDY DESCRIPTION Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. During the fourth period, all capacitors are disconnected from the input; the one representing the MSB (D11) is connected to the VREF+ terminal; and the remaining capacitors to VREF -. The capacitor-common node, after the charges balance out, will indicate whether the input was above 1/2 of (VREF+ - VREF -). At the end of the fourth period, the comparator output is stored and the MSB capacitor is either left connected to VREF+ (if the comparator was high) or returned to VREF -. This allows the next comparison to be at either 3/4 or 1/4 of (VREF+ - VREF -). 2 D0 Bit 0 (Least Significant Bit, LSB). 3 D1 Bit 1. 4 D2 Bit 2. 5 D3 Bit 3. 6 D4 Bit 4. 7 D5 Bit 5. 8 D6 Bit 6. 9 D7 Bit 7. 10 D8 Bit 8. 11 D9 Bit 9. 12 VSS Digital Ground (0V). 13 D10 Bit 10. 14 D11 Bit 11 (Most Significant Bit, MSB). 15 OEM Three-State Enable for D4-D11. Active low input. 16 VAA- Analog Ground, (0V). 17 VAA+ Analog Positive Supply. (+5V) (See text.) 18 VIN 19 VREF+ Reference Voltage Positive Input, sets 4095 code end of input range. 20 VREF- Reference Voltage Negative Input, sets 0 code end of input range. 21 STRT Start Conversion Input Active Low, recognized after end of clock period 15. 22 CLK CLK Input or Output. Conversion functions are synchronized to positive going edge. (See text.) At the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each capacitor either left at VREF+ or at VREF -. At the end of the 15th period, when the LSB (D0) capacitor is tested, (D0) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data-ready output goes active. The conversion cycle is now complete. Analog Input Analog Input. 23 OEL Three-State Enable for D0 D3. Active Low Input. 24 VDD Digital Positive Supply (+5V). The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5µA and 20pF. At the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period as shown in Figure 18. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. 20mA IIN 10mA 0mA CLK Theory of Operation HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that uses capacitor-charge balancing to successively approximate the analog input. A binarily weighted capacitor network forms the A/D heart of the device. See the block diagram for the HI5812. 5V 0V 5V DRDY The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, VREF+ or VREF -. 6-1797 0V 200ns/DIV. CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V, VIN = 4.608V, CLK = 750kHz, TA = 25oC FIGURE 18. TYPICAL ANALOG INPUT CURRENT HI5812 As long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. The analog input is tracked for 3 clock cycles. With an external clock of 750kHz the track period is 4µs. The HI5812 is specified with a 4.608V reference, however, it will operate with a reference down to 3V having a slight degradation in performance. A typical graph of accuracy vs reference voltage is presented. A simplified analog input model is presented in Figure 19. During tracking, the A/D input (VIN) typically appears as a 380pF capacitor being charged through a 420Ω internal switch resistance. The time constant is 160ns. To charge this capacitor from an external “zero Ω” source to 0.5 LSB (1/8192), the charging time must be at least 9 time constants or 1.4µs. The maximum source impedance (RSOURCE Max) for a 4µs acquisition time settling to within 0.5LSB is 750Ω. Full Scale and Offset Adjustment If the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated. VIN RSW ≈ 420Ω CSAMPLE ≈ 380pF RSOURCE – t AC Q R SOURCE(MAX) = -------------------------------------------------------------- – R SW –( N + 1 ) C SAMPLE In [ 2 ] Full scale and offset error can also be adjusted to zero in the signal conditioning amplifier driving the analog input (VIN). The HI5812 may be synchronized from an external source by using the STRT (Start Conversion) input to initiate conversion, or if STRT is tied low, may be allowed to free run. Each conversion cycle takes 15 clock periods. Reference Input The reference input VREF+ should be driven from a low impedance source and be well decoupled. As shown in Figure 20, current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the charge-balancing capacitors are switched between VREF - and VREF+ (clock periods 5 - 14). These current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. Therefore VREF+ and VREF should be well bypassed. Reference input VREF - is normally connected directly to the analog ground plane. If VREF - is biased for nulling the converters offset it must be stable during the conversion cycle. The input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. After the start of the next period 1 (specified by tD data), the output is updated. The DRDY (Data Ready) status output goes high (specified by tD1DRDY) after the start of clock period 1, and returns low (specified by tD2DRDY) after the start of clock period 2. The 12 data bits are available in parallel on three-state bus driver outputs. When low, the OEM input enables the most significant byte (D4 through D11) while the OEL input enables the four least significant bits (D0 - D3). tEN and tDIS specify the output enable and disable times. If the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. When STRT input is used to initiate conversions, operation is slightly different depending on whether an internal or external clock is used. IREF+ 10mA 0mA Figure 3 illustrates operation with an internal clock. If the STRT signal is removed (at least tRSTRT) before clock period 1, and is not reapplied during that period, the clock will shut off after entering period 2. The input will continue to track and the DRDY output will remain high during this time. 5V CLK 0V DRDY The VREF+ and VREF - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. In a typical system the VREF - might be returned to a clean ground, and the offset adjustment done on an input amplifier. VREF+ would then be adjusted to null out the full scale error. When this is not possible, the VREF input can be adjusted to null the offset error, however, VREF must be well decoupled. Control Signal FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE 20mA In many applications the accuracy of the HI5812 would be sufficient without any adjustments. In applications where accuracy is of utmost importance full scale and offset errors may be adjusted to zero. 5V 0V 2µs/DIV. CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V, VIN = 2.3V, CLK = 750kHz, TA = 25oC A low signal applied to STRT (at least tWSTRT wide) can now initiate a new conversion. The STRT signal (after a delay of (tDSTRT)) causes the clock to restart. Depending on how long the clock was shut off, the low portion of clock period 2 may be longer than during the remaining cycles. FIGURE 20. TYPICAL REFERENCE INPUT CURRENT 6-1798 HI5812 The input will continue to track until the end of period 3, the same as when free running. Figure 2 illustrates the same operation as above but with an external clock. If STRT is removed (at least tRSTRT) before clock period 2, a low signal applied to STRT will drop the DRDY flag as before, and with the first positive-going clock edge that meets the (tSUSTRT) setup time, the converter will continue with clock period 3. Clock The HI5812 can operate either from its internal clock or from one externally supplied. The CLK pin functions either as the clock output or input. All converter functions are synchronized with the rising edge of the clock signal. Figure 21 shows the configuration of the internal clock. The clock output drive is low power: if used as an output, it should not have more than 1 CMOS gate load applied, and stray wiring capacitance should be kept to a minimum. The internal clock will shut down if the A/D is not restarted after a conversion. The clock could also be shut down with an open collector driver applied to the CLK pin. This should only be done during the sample portion (the first three clock periods) of a conversion cycle, and might be useful for using the device as a digital sample and hold. If an external clock is supplied to the CLK pin, it must have sufficient drive to overcome the internal clock source. The external clock can be shut off, but again, only during the sample portion of a conversion cycle. At other times, it must be above the minium frequency shown in the specifications. In the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. This might cause an internal charge-pump voltage to decay. If the internal or external clock was shut off during the conversion time (clock cycles 4 through 15) of the A/D, the output might be invalid due to balancing capacitor droop. An external clock must also meet the minimum tLOW and tHIGH times shown in the specifications. A violation may cause an internal miscount and invalidate the results. CLK OPTIONAL EXTERNAL CLOCK 100kΩ Except for VAA+, which is a substrate connection to VDD , all pins have protection diodes connected to VDD and VSS . Input transients above VDD or below VSS will get steered to the digital supplies. The VAA+ and VAA- terminals supply the charge-balancing comparator only. Because the comparator is autobalanced between conversions, it has good low-frequency supply rejection. It does not reject well at high frequencies however; VAA- should be returned to a clean analog ground and VAA+ should be RC decoupled from the digital supply as shown in Figure 22. There is approximately 50Ω of substrate impedance between VDD and VAA+. This can be used, for example, as part of a low-pass RC filter to attenuate switching supply noise. A 10µF capacitor from VAA+ to ground would attenuate 30kHz noise by approximately 40dB. Note that back-to-back diodes should be placed from VDD to VAA+ to handle supply to capacitor turn-on or turn-off current spikes. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the A/D. A low distortion sine wave is applied to the input of the A/D converter. The input is sampled by the A/D and its output stored in RAM. The data is than transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling frequency. The noise is the RMS sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N + 1.76) dB. For an ideal 12-bit converter the SNR is 74dB. Differential and integral linearity errors will degrade SNR. SNR = 10 Log Sinewave Signal Power Total Noise Power INTERNAL ENABLE Signal-To-Noise + Distortion Ratio CLOCK SINAD is the measured RMS signal to RMS sum of noise plus harmonic power and is expressed by the following: SINAD = 10 Log 18pF Sinewave Signal Power Noise + Harmonic Power (2nd - 6th) Effective Number of Bits FIGURE 21. INTERNAL CLOCK CIRCUITRY The effective number of bits (ENOB) is derived from the SINAD data; Power Supplies and Grounding VDD and VSS are the digital supply pins: they power all internal logic and the output drivers. Because the output drivers can cause fast current spikes in the VDD and VSS lines, VSS should have a low impedance path to digital ground and VDD should be well bypassed. 6-1799 ENOB = SINAD - 1.76 6.02 HI5812 Total Harmonic Distortion Spurious-Free Dynamic Range The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. THD = 10 Log Total Harmonic Power (2nd - 6th Harmonic) Sinewave Signal Power SFDR = 10 Log Sinewave Signal Power Highest Spurious Signal Power TABLE 2. CODE TABLE BINARY OUTPUT CODE INPUT VOLTAGE† VREF+ = 4.608V VREF- = 0.0V (V) DECIMAL COUNT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Full Scale (FS) 4.6069 4095 1 1 1 1 1 1 1 1 1 1 1 1 CODE DESCRIPTION MSB LSB FS - 1 LSB 4.6058 4094 1 1 1 1 1 1 1 1 1 1 1 0 3/ FS 4 1/ FS 2 1/ FS 4 3.4560 3072 1 1 0 0 0 0 0 0 0 0 0 0 2.3040 2048 1 0 0 0 0 0 0 0 0 0 0 0 1.1520 1024 0 1 0 0 0 0 0 0 0 0 0 0 1 LSB 0.001125 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Zero † The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage. +5V 0.1µF 10µF 0.1µF 0.01µF VAA+ VREF VDD D11 . . . D0 VREF+ 4.7µF 0.1µF 4.7µF 0.001µF OUTPUT DATA DRDY OEM ANALOG INPUT OEL VIN STRT CLK VREF- VAA- VSS FIGURE 22. GROUND AND SUPPLY DECOUPLING 6-1800 750kHz CLOCK HI5812 Die Characteristics DIE DIMENSIONS: PASSIVATION: 3200µm x 3940µm Type: PSG Thickness: 13kÅ ±2.5kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: AlSi Thickness: 11kÅ ±1kÅ 1.84 x 105 A/cm2 Metallization Mask Layout HI5812 D1 D0 (LSB) DRDY VDD OEL CLK D2 STRT D3 VREF - D4 D5 VREF + D6 D7 VIN D8 VAA + VAA - D9 VSS D10 D11 (MSB) 6-1801 OEM