mcu-an-391021-e-v12

MCU-AN-391021-E-V12
Fujitsu Microelectronics Europe
Application Note
EMC Design Guide
FR50 Family
© Fujitsu Mikroelektronik GmbH, Microcontroller Application Group
History
04th Mrz. 02
11th Mrz. 02
18th Jul. 02
NFl
NFl
NFl
V1.0
V1.1
V1.2
© Fujitsu Microelectronics Europe GmbH
Initial draft
Clock modulator description added
Description DeCap added
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MCU-AN-391021-E-V12
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environment.
1.
Fujitsu Mikroelektronik GmbH warrants that the Product will perform substantially in accordance with
the accompanying written materials for a period of 90 days form the date of receipt by the customer.
Concerning the hardware components of the Product, Fujitsu Mikroelektronik GmbH warrants that the
Product will be free from defects in material and workmanship under use and service as specified in the
accompanying written materials for a duration of 1 year from the date of receipt by the customer.
2.
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3.
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.
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© Fujitsu Microelectronics Europe GmbH
Table of Contents:
1.
Introduction
4
2.
Rules to create a good Layout
4
3.
Crystal Oscillator Circuit
5
4.
Power supply routing
6
5.
Noise reduction for general IO pins
9
6.
Noise reduction by Clock Modulation
9
7.
Function of certain MCU pins
11
8.
EMI Measurement for 32-bit family
12
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-391021-E-V12
1. Introduction
In the following description, the EMC design guide of 32-bit Fujitsu microcontrollers will be
discussed. It describes how external power supply should be connected to the Vcc and Vss
pins and offers some suggestions. An overview of internal supply of MCU is made as well to
have a better understanding of the design. The EMI measurements in the following described
tests are just example measurements. The measured emissions are no data, which are
specified in the DS of the microcontroller series.
During the last designs the EMI of the Fujitsu FR50 microcontroller series could be reduced
step by step. The PLL multiplier circuit allows the usage of low crystal frequency to reduce
high-frequency noise from the oscillator circuit.
The clock tree is mostly the cause of the noise. Therefore the driver capability of clock
buffers is optimised and for one big buffer are used several small clock buffers.
Further countermeasures like using of the MCU flash and core on a base of 3.3V level
reduces the noise level of the package. For the PWM outputs it is possible to use the slew
rate control. This means that the rise and fall time can ease to reduce the harmonics.
The integration of On-chip bypass capacitors reduces the noise ripple on the internal power
supply net so that the broadband noise on the IO pins is improved.
The following description is based on the MB90F362, but the same situation exists for all
current devices of the MB91360 series, with or without an external bus interface.
2. Rules to create a good Layout
1. Use max. trace-width and min. length to connect VSS and VDD >C-pins to decoupling
capacitors (DeCap)
2. Don’t use stub line to connect the DeCap to >C-pins, let flows the noise current direct
through pads of DeCap
3. Use close ground plane direct below MCU package as shield
4. Use different ground systems for analogue, digital, power-driver and connector
ground
5. Avoid loop current in the ground system, check for ground loops.
6. Use a star point ground below MCU for analogue and digital ground, use a second
star point ground below 5V regulator for MCU, power-driver and connector ground
7. Don't create signal loop on the PCB, minimize trace length
8. Partitioned system into analogue, digital and power-driver section
9. Place series resistor or RC-block for the IO-circuit nearby MCU-pin to reduce the
noise on the signal line.
10. Use a capacitor for each connector pin to reduce the noise of external lines, place this
capacitor close to connector pin
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© Fujitsu Microelectronics Europe GmbH
3. Crystal Oscillator Circuit
Figure 1 shows the oscillator for the Fujitsu 32-bit family. For best performance, the PCB
layout of this circuit should cover only a very small area. For the layout is recommended a
PCB with two or more layers. Make sure to provide bypass capacitors via shortest distance
from X0, X1 pins, crystal oscillator, and ground lines. The lines of the oscillation circuit should
not cross lines of other circuits.
X1
X0
Microcontroller
Oscillator
Figure 1: Principle of the Oscillator circuit
It is necessary to avoid coupling noise into the power supply (pin 81/84) of the clock circuit.
The crystal oscillator has to be connected with short lines to X0/X1 and Vss. Note that pin X1
is the output of inverter. Particularly this track should have a short length.
Decoupling capacitor C B on
the back side of the PCB
Decoupling capacitor C B on
the back side of the PCB
Via to ground island
and system ground
CB
Vss
Vss
Vcc
X0
Connection to
ground layer
Via to system Vcc
CB
Vcc
X0
X1
C1
Via to ground island
on the back side
Quartz
Crystal
X1
Single ground island
on the back side
Connection to
ground layer
C2
SMD
Quartz Crystal
C1
Quartz Crystal package
has to be grounded
C2
Connection to
ground layer
b) Layout example for a SMD quartz crystal
better layout design, because C1 and C2
are connected to Vss and than after with
the system ground
a) Layout example for a leaded quartz crystal
worse layout design, because C1 and C2
are wrong connected to VSS
Figure 2: Layout example for oscillator circuit
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-391021-E-V12
4. Power supply routing
One topic our noise reduction technology is lowering internal power supply voltage on 3V
level to reduce the current flow. Fig. 2 shows the structure of 5V and 3V power supply.
I/O-PORT
FLASH
VCC
3V Regulator
VCC35
CPU
VSS
RAM
Ext.Bus Interface
External
capacitor
VSS
VCC3C
SCI / TIMER / etc.
A/D+D/A
AVcc
AVss
Figure 3: Structure of power supply for MCU core and IO-Port
Only the right placement and the value of decoupling capacitor (DeCap) guaranty the
function of decoupling capacitors. The high-speed current (di/dt) will be supported from
DeCap only. The exactly use of DeCap is important for the noise reduction on the PCB.
VCC
VCC
>C
DeCap
VCC
>C
DeCap
DeCap
GND
GND
a) VCC and GND lead to supply
noise current flows not via
DeCap, DeCap has not effect
DeCap
GND
b) GND lead noise to system GND
noise current flows partly via
DeCap, DeCap has hardly effect
>C
VCC
>C
c) GND lead noise to System GND
noise current flows partly via
DeCap, DeCap has hardly effect
VCC
>C
VCC
>C
DeCap
DeCap
GND
GND
GND
GND
d) VCC and GND lead to supply
noise current flows not via
DeCap, DeCap has not effect
e) GND is not short connected to
DeCap. between GND and
DeCap flows a loop current
DeCap has hardly effect
f) DeCap correct connected to >C
and power supply.
high speed current will be
supported from DeCap
Figure 4: The exactly use of the DeCap (decoupling capacitor)
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© Fujitsu Microelectronics Europe GmbH
The high-speed current (di/dt) will be supported from the decoupling capacitor only.
Therefore use traces with max. width and min. length between Vss/Vcc pin and DeCap.
After DeCap use thin traces to route the trace to the power supply system.
use EMC filter for
>C-supply
short length
max. width
high Z
>C
low Z
VCC
C
GND
Figure 5: The noise current flows return over the ground line
The exactly use of decoupling capacitors for the Vcc and Vss pins is the basis to reduce the
noise, but also the return way between load and MCU ground is not neglect.
high-Z
choking coil
min. length
max. width
min. length
max. width
>C
VCC
C
I slow
clock
unit
&
core
VSS
HVCC
IO-driver
HVSS
I fast
low-Z
I supply
C
I return
I crossbar
dt/di
R
C
Load
I load
Figure 6: The noise current flows return over the ground line
To ensure an efficient decoupling of the power supply, two capacitors should be placed close
on each Vcc pin. The values of both capacitors should have a relationship of about 1:100.
Typical values are e.g. 100nF (XR7) and 1nF (COG). The accurate value is depended on the
application board, e.g. impedance of PCB or the length of supply lines. However, all of the
DeCaps on the PCB should have the same value.
Lboard
Lboard
VDD
IC2
DeCap Cn
IC1
DeCap C2
Cboard
DeCap C1
A
ICn
f
GND
Figure 7: The use of several values of DeCaps lead to undefined resonance frequencies,
that’s why all DeCaps should have the same value.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-391021-E-V12
For 2-layer boards should be used a closed ground plane (located directly below the MCU).
The Vcc supplies should be taken from the bottom layer.
For 4-layer boards should be used the inside layers for GND and Vcc supplies. In this case,
both layers form additional capacitor (broadband behaviour) for the power supply.
Figure 8 shows an example of a star connection for Vcc supplies on the MCU.
This method of Vcc connection reduces the loop of the Vcc lines around the MCU, thus
reducing noise emission. A variation of this circuit may be needed, if separate filtered supply
voltages are routed to the A/D supplies (pin 34/37).
Q
VSS
ground plane
on top and
botton layer
Via to MCU supply
CB
CB
CB
VSS
X0A
C
VCC
C
X0
X1
C
X1A
VSS
VSS
Via to ground island
and system ground
C
Q
VDD
Single ground island
on the back side
VCC3C
Ground plan
below the package
on top side
CB
VDD
CB
HVss
CB
VDD
VSS
Decoupling capacitor CB on
the back side of the PCB
CB
LB
CB
star point and noise
filter for
Vcc and ground
on the back side
CB
HVcc
LB
VDD35
LB
CB
VDD35
VCC
VSS
Decoupling capacitor CB on
the back side of the PCB
CB
CB
HVss
CB
CB
AVss
AVR-
CB
HVss
CB
Decoupling capacitor CB on
the back side of the PCB
HVcc
VSS
AVR+
AVcc
VSS
VDD35
VDD35
CB
VSS
CB
Decoupling capacitor C B on
the back side of the PCB
Connection to
power supply
Figure 8: 32-bit family with a subclock or stepper motor driver,
recommended layout for multiple layers PCB
Note: All decoupling capacitors on the Vcc pins should have the same value.
These capacitors should be placed close to the Vcc pin. The Vcc/Vss current should flows
through the pad of the capacitor.
MCU-AN-391021-E-V12
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© Fujitsu Microelectronics Europe GmbH
5. Noise reduction for general IO pins
To reduce noise, make sure to connect the Vss or Vcc with smoothed power supply, because
the noise on the power supply will also distributed via IO-pin, which is configured as static
low or high output. Figure 9 shows an example to reduce the noise on output lines.
>C
IO-Port
>C
IO-Port
Noise
length of trace
length of trace
Figure 9: Place the series resistor close to IO pin because so will be reduced the noise
of output
Note: To reduce noise, make sure to connect unused input pins to Vss or Vcc (Use pull-down
or pull-up resistor, please check the DS of the microcontroller series).
Also, especially if CMOS Logic is used, floating gates could generate problems regarding high
input currents and latch up.
6. Noise reduction by Clock Modulation
Functional principle:
The modulation of internal operation clock reduces the noise by spreading the energy of
MCU over a wide range in the frequency spectrum (Figure 10).
Figure 10: Spectrum of clock periods
First, the PLL period of the input clock is subdivided into equidistant taps via a delay chain.
By this one can achieve 16 possible positions per half period for switching edge (Figure 11)
that does mean, 16 taps for the high period and 16 taps for the low period.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-391021-E-V12
The time between two edges of the output clock is changed according to random algorithms.
The random numbers generator chooses via multiplexer the time position for the edge
(outputs of delay chain).
So the frequency of the output clock between minimal and maximal system frequency is
generated. The maximum degree of modulation is limited by the maximal possible clock
frequency of MCU. The overstepping of max clock frequency it not allowed.
Advantage: The clock modulation is an efficient way to reduce the amplitude of the peak
level. Micros with integrated Clock modulator find use in automotive sector that demands
very low emission values, e.g. particularly dashboard could disturb the car radio due to
sensitive pane aerial, which is nearby.
Disadvantage: This modulation principle leads to performance loss because the modulation
may result in frequencies above of maximum permissible clock rate. So with the clock
modulator for 64 MHz devices can only work up to 48 MHz. The next generation of clock
modulator will further reduce this disadvantage.
To
To
2
input-clock
(unmodulated clock)
t
To
2
Ni=0 Ni=1 Ni=2 Ni=3 Ni=4 Ni=5 Ni=6
output-clock
(modulated clock)
c
k
t
(N-1) *k
To
N
Ni
k
c
cycle duration of input clock
number of random numbers
current random number
modulation degree
minimal tap-distance
example:
N=7
k=2
c = 10
Figure 11: 16 possible positions per half period
Example Program:
The following example program shows how to configure and start the clock modulator.
Write the register only when the modulator is switched off
The Modulation Parameter Register CMPR defines the degree of modulation (k).
The random dispersion will be configured via the Modulation Load Shift registers CMLS0-3
and Modulation Load TAP settings registers CMLT0-3. In the field one chooses settings,
which result in a more equally, distributed random number sequence.
The calibration reload timer value CMAC determinates in which interval the clock modulator
will be calibrated.
Set the Control Register CMCR for CAN–prescaler, start calibration, select modulation clock
output.
Finally, the clock modulator is started.
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© Fujitsu Microelectronics Europe GmbH
/* Switch modulator off */
CMCR &= 0xFFFE;
/* Settings for modulation degree */
/* Resolution, random dispersion */
/* 32 MHz, N=7, k=1 */
CMPR
CMLS0
CMLS1
CMLS2
CMLS3
CMLT0
CMLT1
CMLT2
CMLT3
CMAC
=
=
=
=
=
=
=
=
=
=
0xFDF1;
0xF800;
0xFF04;
0xF813;
0x7F84;
0xF802;
0xF802;
0xF802;
0xF802;
0xFFFF;
/* Settings control register
*/
/* CAN-prescaler, start calibration */
/* Select modulated clock output
*/
CMCR = (CMCR & 0x000C) | 0xFFB2;
/* Switch modulator on */
CMCR |= 0x0013;
7. Function of certain MCU pins
Pin name
VDD
VSS
VDD
VSS
VDD
VSS
VDD35
VSS
VCC3C
MB91F362
Pin no.
118
123
144
145
79, 92, 144
78
93, 110,145
25, 51, 182,
198
26, 52, 199
159
VSS
AVCC
AVRH
AVSS
AVRL
HVDD
158
64
65
74
74
166
176
HVSS
161
171
181
X0
X0A
X1
X1A
Function
Main supply for IO buffer
close to crystal oscillator
Main supply for IO buffer and MCU core
close to the internal 3.3V regulator
Main supply for IO buffer
Main supply for Ext. Bus interface
External smooth capacitor for internal 3.3V regulator
output, it is used for supply of the MCU core
Note, that this pin leads the most of noise
Power supply for the A/D converter
Reference voltage input for the A/D converter
Power supply for the A/D converter
Reference voltage input for the A/D converter
Power supply for the PWM (high current) outputs, it is
not connected to VCC,
should be connected to extra power supply
Power supply for the PWM (high current) outputs, it is
not connected to VSS,
should be connected to extra power supply
Oscillator input, if not used so shall be connected with
pull-up or pull-down resistor (see please DS)
Oscillator output, the crystal and bypass capacitor
must be connected via shortest distance with X1 pin,
if not used so shall be open
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-391021-E-V12
8. EMI Measurement for 32-bit family
Schirmbox
Spectrum analyzer
0.1-1000MHz
10Ai
Vdd
+
Power supply
5V
be
pro
RF
10Ai
Vss
X-TEM
Filter
IEEE
Ferrit
Filter
RS232
Workstation
Figure 12: Measuring setup
The I/O pin measurements were done with default settings as following:
IO port setting
Port
Function
port x0
port x1
port x2
port x3
port x4
port x5
port x6
port x7
output
output
output
input
output
output
output
input
I/O-State
high
low
2 kHz toggling
high
low
2 kHz toggling
-
Table 1:Test pattern for the I/O port pins
The PLL and clock unit used divider settings as following:
Clock setting
Clock/PLL
DIVR0
DIVR1
CLKR
CLKB
CLKP
CLKT
CAN
16MHz
24MHz
32MHz
40MHz
48MHz
64MHz
00h
10h
36h
16MHz
16MHz
8MHz
0.0625MHz
01h
10h
26h
24MHz
12MHz
12MHz
0.46MHz
01h
10h
36h
32MHz
16MHz
16MHz
0.125MHz
03h
30h
56h
40MHz
10MHz
10MHz
0.1563MHz
02h
40h
66h
48MHz
16MHz
9.6MHz
0.1875MHz
03h
70h
76h
64MHz
16MHz
8MHz
0.25MHz
Table 2: Clock-settings for several PLL frequencies
Before reprogramming of the clock register the PLL and Clock Modulator were disabled.
The settings for UART and other timing registers were fitted.
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© Fujitsu Microelectronics Europe GmbH
The clock modulator used default settings as following:
Clock Modulator setting
PLL
n
k
c
16 MHz
24 MHz
32 MHz
40 MHz
48 MHz
64 MHz
15
15
7
3
3
-
1
1
1
1
1
-
9
9
13
15
15
-
Table 3: Clock Modulator default settings
Note:
The clock modulator doesn’t work at 64 MHz.
The INVS-bit must be set to 1.
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-391021-E-V12
Fig. 1: 1-Ohm probe, measured on common ground, IO ports are configured with test pattern
Fig. 2: 1-Ohm probe, measured on common ground, IO ports are configured with test pattern
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© Fujitsu Microelectronics Europe GmbH
Fig. 3: 150-Ohm probe, measured on static output-high, IO ports are configured with test pattern
Fig. 4: 150-Ohm probe, measured on static output-low, IO ports are configured with test pattern
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-391021-E-V12
Fig. 5: 150-Ohm probe, measured on (2kHz) toggling output, IO ports are configured with test pattern
Fig. 6: 150-Ohm probe, measured on input with 6k8 pull-up, IO ports are configured with test pattern
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© Fujitsu Microelectronics Europe GmbH