NB6L295 D

NB6L295
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential
LVPECL Outputs
Multi−Level Inputs w/ Internal Termination
The NB6L295 is a Dual Channel Programmable Delay Chip
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designed primarily for Clock or Data de−skewing and timing
adjustment. The NB6L295 is versatile in that two individual variable
MARKING
delay channels, PD0 and PD1, can be configured in one of two
DIAGRAM*
24
operating modes, a Dual Delay or an Extended Delay.
1
In the Dual Delay Mode, each channel has a programmable delay
QFN−24
NB6L
MN SUFFIX
section which is designed using a matrix of gates and a chain of
295
CASE
485L
24
1
ALYWG
multiplexers. There is a fixed minimum delay of 3.2 ns per channel.
G
The Extended Delay Mode amounts to the additive delay of PD0
A
= Assembly Location
plus PD1 and is accomplished with the Serial Data Interface MSEL bit
L
= Wafer Lot
set High. This will internally cascade the output of PD0 into the input
Y
= Year
of PD1. Therefore, the Extended Delay path starts at the IN0/IN0
W
= Work Week
G
= Pb−Free Package
inputs, flows through PD0, cascades to the PD1 and outputs through
(Note: Microdot may be in either location)
Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended
*For additional marking information, refer to
Delay Mode.
Application Note AND8002/D.
The required delay is accomplished by programming each delay
channel via a 3−pin Serial Data Interface, described in the application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
section. The digitally selectable delay has an increment resolution of
dimensions section on page 12 of this data sheet.
typically 11 ps with a net programmable delay range of either 0 ns to
6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the
Extended Delay Mode.
The Multi−Level Inputs can be driven directly by differential
LVPECL, LVDS or CML logic levels; or by single ended LVPECL,
LVCMOS or LVTTL. A single enable pin is available to control both
inputs. The SDI input pins are controlled by LVCMOS or LVTTL
level signals. The NB6L295 LVPECL output contains temperature
compensation circuitry. This device is offered in a 4 mm x 4 mm
24−pin QFN Pb−free package. The NB6L295 is a member of the
ECLinPS MAX™ family of high performance products.
Features
• 3 ps Typical Clock Jitter, RMS
• Input Clock Frequency > 1.5 GHz with 550 mV
• 20 ps Pk−Pk Typical Data Dependent Jitter
VOUTPP
• LVPECL, CML or LVDS Differential Input Compatible
• Input Data Rate > 2.5 Gb/s
• LVPECL, LVCMOS, LVTTL Single−Ended Input
• Programmable Delay Range: 0 ns to 6 ns per Delay
Compatible
Channel
• 3−Wire Serial Interface
• Programmable Delay Range: 0 ns to 11.2 ns for
• Input Enable/Disable
Extended Delay Mode
• Operating Range: VCC = 2.375 V to 3.6 V
• Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel
• LVPECL Output Level; 780 mV Peak−to−Peak, Typical
• Total Delay Range: 6 ns to 17 ns in Extended Delay
• Internal 50 W Input Termination Provided
Mode
• −40°C to 85°C Ambient Operating Temperature
• Monotonic Delay: 11 ps Increments in 511 Steps
• 24−Pin QFN, 4 mm x 4 mm
• Linearity $20 ps, Maximum
• These are Pb−Free Devices*
• 100 ps Typical Rise and Fall Times
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 4
1
Publication Order Number:
NB6L295/D
2
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Figure 1. Simplified Functional Block Diagram
SLOAD
SCLK
SDATA
VT1
D8
IN1
IN1
50 W
50 W
VT1
VT0
IN0
IN0
50 W
50 W
VT0
D7
EN
D6
D5
D4
0
128
GD* 1
0
D3
D2
D1
*GD = Gate Delay
256 1
GD*
11 Bit Shift Register
0
1
D0
1
MSEL
64
GD*
0
1
256 1
GD*
*GD = Gate Delay
0
64
GD*
0
128
GD* 1
0
PSEL
32
GD*
32
GD*
1
0
1
0
1
0
1
9 Bit Latch
16
GD*
0
PD1
9 Bit Latch
16
GD*
PD0
8
GD*
8
GD*
1
0
1
0
4
GD*
4
GD*
1
0
1
0
2
GD*
2
GD*
1
0
1
0
1
GD*
1
GD*
1
0
1
0
1
0
Q1
Q1
Q0
Q0
NB6L295
NB6L295
VT0 IN0
24
23
IN0 VT0 GND VCC0
22
21
20
Exposed Pad
(EP)
19
VCC
1
18
Q0
EN
2
17
Q0
SLOAD
3
16
VCC0
SDIN
4
15
VCC1
SCLK
5
14
Q1
VCC
6
13
Q1
NB6L295
7
VT1
8
9
IN1 IN1
10
11
12
VT1
GND VCC1
Figure 2. Pinout: QFN−24 (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
1
VCC
Power Supply
Description
2
EN
LVCMOS/LVTTL Input
Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open Pin Default
state LOW (37 kW pulldown resistor). High forces Q LOW and Q HIGH.
3
SLOAD
LVCMOS/LVTTL Input
Serial Load; This pin loads the configuration latches with the contents of the shift register. The
latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH−
to−LOW transition of S_LOAD for proper operation. Open Pin Default state LOW (37 kW pulldown
resistor).
4
SDIN
LVCMOS/LVTTL Input
Serial Data In; This pin acts as the data input to the serial configuration shift register. Open Pin
Default state LOW (37 kW pulldown resistor).
5
SCLK
LVCMOS/LVTTL Input
Serial Clock In; This pin serves to clock the serial configuration shift register. Data from SDIN is
sampled on the rising edge. Open Pin Default state LOW (37 kW pulldown resistor).
6
VCC
Power Supply
7
VT1
8
IN1
LVPECL, CML, LVDS Input
Non−inverted differential input. Note 1.
9
IN1
LVPECL, CML, LVDS Input
Inverted differential input. Note 1.
10
VT1
11
GND
Power Supply
Negative Power Supply
12
VCC1
Power Supply
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
13
Q1
LVPECL Output
Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to
VCC1 − 2.0 V.
14
Q1
LVPECL Output
Non−inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to
VCC1 − 2.0 V.
15
VCC1
Power Supply
Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
16
VCC0
Power Supply
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
17
Q0
LVPECL Output
Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to
VCC0 − 2.0 V.
18
Q0
LVPECL Output
Non−inverted Differential Output . Channel 0. Typically terminated with 50 W resistor to
VCC0 − 2.0 V.
19
VCC0
Power Supply
Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
20
GND
Power Supply
Negative Power Supply
21
VT0
22
IN0
LVPECL, CML, LVDS Input
Inverted differential input. Note 1.
23
IN0
LVPECL, CML, LVDS Input
Noninverted differential input. Note 1.
24
VT0
−
EP
Positive Supply Voltage for the Inputs and Core Logic
Positive Supply Voltage for the Inputs and Core Logic
Internal 50 W Termination Pin for IN1
Internal 50 W Termination Pin for IN1
Internal 50 W Termination Pin for IN0
Internal 50 W Termination Pin for IN0
Ground
The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to GND and must be connected to GND on the PC
board.
1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx input then the device will be susceptible to self−oscillation.
2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected
to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate.
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NB6L295
Table 2. ATTRIBUTES
Characteristics
Value
Input Default State Resistors
37 kW
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 3)
> 2 kV
> 100V
QFN−24
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
3094
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC, VCC0,
VCC1
Positive Power Supply
VIO
Positive Input/Output Voltage
VINPP
Differential Input Voltage
IIN
Input Current Through RT (50 W Resistor)
IOUT
Output Current (LVPECL Output)
TA
Condition 2
GND = 0 V
GND = 0 V
−0.5 v VIO v VCC + 0.5
Rating
Unit
4.0
V
4.5
V
VCC − GND
V
$50
mA
50
100
mA
mA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 4)
0 lfpm
500 lfpm
QFN−24
QFN−24
37
32
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 4)
QFN−24
11
°C/W
Tsol
Wave Solder Pb−Free
265
°C
|INx − INx|
Continuous
Surge
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6L295
Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to
+85°C
Characteristic
Symbol
Min
Typ
Max
Unit
110
140
170
mA
VCC = VCC0 = VCC1 = 3.3 V
VCC = VCC0 = VCC1 = 2.5 V
VCC − 1075
2225
1425
VCC − 950
2350
1550
VCC − 825
2475
1675
mV
VCC = VCC0 = VCC1 = 3.3 V
VCC − 1825
1475
VCC − 1725
1575
VCC − 1625
1675
mV
VCC = VCC0 = VCC1 = 2.5 V
VCC − 1825
675
VCC − 1725
775
VCC − 1600
900
POWER SUPPLY CURRENT
ICC
Power Supply Current (Inputs, VTx and Outputs Open) (Sum of ICC,
ICC0, and ICC1)
LVPECL OUTPUTS (Notes 5 and 6, Figure 21)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 10 and 11) (Note 7)
Vth
Input Threshold Reference Voltage Range
1050
VCC − 150
mV
VIH
Single−Ended Input HIGH Voltage
Vth + 150
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
Vth − 150
mV
VISE
Single−Ended Input Voltage Amplitude (VIH − VIL)
300
VCC − GND
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 12 and 13) (Note 8)
VIHD
Differential Input HIGH Voltage
1200
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC − 150
mV
VID
Differential Input Voltage Swing (INx, INx) (VIHD − VILD)
150
VCC − GND
mV
VCMR
Input Common Mode Range (Differential Configuration) (Note 9)
950
VCC – 75
mV
IIH
Input HIGH Current INx/INx, (VTn/VTn Open)
−150
150
mA
IIL
Input LOW Current IN/INX, (VTn/VTn Open)
−150
150
mA
SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS
VIH
Single−Ended Input HIGH Voltage
2000
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
800
mV
IIH
Input HIGH Current
−150
150
mA
IIL
Input LOW Current
−150
150
mA
60
W
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
40
50
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVPECL outputs loaded with 50 W to VCC − 2.0 V for proper operation.
6. Input and output parameters vary 1:1 with VCC.
7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. Vth is applied to the complementary input when operating in
single−ended mode.
8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
9. VCMR(min) varies 1:1 with voltage on GND Pin, VCMR(max) varies 1:1 with VCC. The VCMR range is referenced to the most positive side
of the differential input signal.
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5
NB6L295
Table 5. AC CHARACTERISTICS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 10)
Symbol
fSCLK
Characteristic
Min
Typ
Serial Clock Input Frequency, 50% Duty Cycle
Max
Unit
20
MHz
VOUTPP
Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.5 GHz
(Note 15) (See Figure 22)
530
fDATA
Maximum Data Rate (Note 14)
2.5
tRange
Programmable Delay Range (@ 50 MHz)
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
Extended Mode
IN0/IN0 to Q1/Q1
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew − Dual Mode
Lin
Linearity (Note 12)
ts
Setup Time (@ 20 MHz)
SDIN to SCLK
SLOAD to SCLK
EN to SDIN
0.5
1.5
0.5
0.3
1.0
ns
th
Hold Time
SDIN to SCLK
SLOAD to SCLK
EN to SLOAD
1.0
1.0
0.5
0.6
ns
tpwmin
Minimum Pulse Width SLOAD
tJITTER
Random Clock Jitter RMS; SETMIN to SETMAX
(Note 13)
fin ≤ 1.5 GHz
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
Extended Mode
IN0/IN0 to Q1/Q1
Deterministic Jitter; SETMIN to SETMAX (Note 14)fDAT
A ≤ 2.5 Gbps
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
D[8:0] = 0
D[8:0] = 1
0
2
60
60
5
100
175
ps
$15
$20
ps
1
tr, tf
Output Rise/Fall Times (@ 50 MHz), (20% − 80%) Qx,
Qx
85
−405C
Dt
ns
6.9
13.7
150
Min
Characteristic
Propagation Delay (@ 50 MHz)
Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1
D[8:0] = 0
D[8:0] = 1
Extended Mode
Gb/s
5.7
11.2
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
tPLH,
tPHL
mV
0
0
VINPP
Symbol
780
IIN0/IN0 to Q1/Q1
D[8:0] = 0
D[8:0] = 1
Step Delay
(Selected D Bit HIGH All Others LOW)
Typ
ns
Max
Min
3
6
10
20
20
30
ps
VCC − GND
mV
120
170
ps
+255C
+855C
Typ
Max
Min
Typ
Max
Unit
ns
2.7
7.2
2.9
8.0
3.2
8.8
2.8
7.5
3.1
8.4
3.4
9.3
2.9
7.9
3.2
9.2
3.6
9.9
5.0
14.2
5.5
15.2
6.0
17.1
5.2
14.8
5.8
16.5
6.3
18.2
5.5
15.6
6.2
16.4
6.8
19.6
ps
D0 HIGH
D1 HIGH
D2 HIGH
D3 HIGH
D4 HIGH
D5 HIGH
D6 HIGH
D7 HIGH
D8 HIGH
9.6
19.4
40
81
167
338
678
1358
2715
8.7
19
42
85
175
355
714
1432
2861
11
24.4
52
99
196
389
774
1544
3074
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing VINPPmin and VINPPmax from a 50% duty cycle clock source, VCMR (min and max). All loading with an external
RL = 50 W to VCC. See Figure 20. Input edge rates 40 ps (20% − 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
12. Deviation from a linear delay (actual Min to Max) in the Dual Mode 511 programmable steps.
13. Additive random CLOCK jitter with 50% duty cycle input clock signal.
14. NRZ data at PRBS23 and K28.5.
15. Input and output voltage swing is a single−ended measurement operating in differential mode.
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6
NB6L295
Serial Data Interface Programming
The NB6L295 is programmed by loading the 11−Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs. The
11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11−bit load cycle is required to program
the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially set
PD0 and PD1; Dual Mode Operation as shown in Figures 3 and 4 and Extended Mode Operation as shown in Figures 5 and 6.
DUAL MODE OPERATIONS
Control
Bits
PD0 Programmable Delay
0/1
D8
0/1
D7
0/1
D6
0/1
D5
0/1
D4
0/1
D3
0/1
D2
0/1
D1
0/1
D0
0
MSEL
(MSB)
Control
Bits
PD1 Programmable Delay
0
Value
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
1
Value
PSEL
Bit
Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL
PSEL
Bit
Name
(LSB)
(MSB)
(LSB)
Figure 3. PDO Shift Register
Figure 4. PD1 Shift Register
EXTENDED MODE OPERATIONS
Control
Bits
PD0 Programmable Delay
Control
Bits
PD1 Programmable Delay
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
0
Value
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
1
Value
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL
PSEL
Bit
Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL
PSEL
Bit
Name
(MSB)
(LSB)
(MSB)
Figure 5. PDO Shift Register
(LSB)
Figure 6. PD1 Shift Register
Refer to Table 6, Channel and Mode Select BIT Functions. In a load cycle, the 11−Bit Shift Register least significant bit
(clocked in first) is PSEL and will determine which channel delay buffer, either PDO (LOW) or PD1 (HIGH), will latch the
delay data value D[8:0]. The MSEL BIT determines the Delay Mode. When set LOW, the Dual Delay Mode is selected and
the device uses both channels independently. A pulse edge entering IN0/IN0 is delayed according to the values in PD0 and exits
from Q0/Q0. An input signal pulse edge entering IN1/IN1 is delayed according to the values in PD1 and exits from Q1/Q1.
When MSEL is set HIGH, the Extended Delay Mode is selected and an input signal pulse edge enters IN0 and IN0 and flows
through PD0 and is extended through PD1 to exit at Q1 and Q1. The most significant 9−bits, D[8:0] are delay value data for
both channels. See Figure 7.
Table 6. CHANNEL AND MODE SELECT BIT FUNCTIONS
BIT Name
PSEL
Function
0 Loads Data to PD0
1 Loads Data to PD1
MSEL
0 Selects Dual Programmable Delay Paths, 3.1 ns to 8.8 ns Delay Range for Each Path
1 Selects Extended Delay Path from IN0/IN0 to Q1/Q1, 6.0 ns to 17.2 ns Delay Range; Disables Q0/Q0 Outputs,
Q0−LOW, Q0−HIGH.
D[8:0]
Select one of 512 Delay Values
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NB6L295
Q0/Q0
Q1/Q1
PD0 Delay
PD1 Delay
PD0 Latch
PD1 Latch
MSEL
PSEL
D2
D1
D0
1
D5
D4
D3
D8
D7
D6
0
SDATA
D2
D1
D0
D5
D4
D3
D6
D8
D7
D2
D1
D0
D5
D4
D3
D6
SLOAD
D8
D7
MSEL
SCLK
11−Bit Shift Register
Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels
Serial Data Interface Loading
Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by
using the SCLK input pin and latching the data with the SLOAD input pin. The 11−bit SHIFT REGISTER shifts once per rising
edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section
of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOW−to−HIGH edge
transition (transparent state) into a data Latch register and latches the data with a subsequent HIGH−to−LOW edge transition.
Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL
and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence.
Input EN should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After
programming, the EN should be returned LOW (enabled) for functional delay operation.
The disabling of EN (HIGH) forces Qx LOW and Qx HIGH and is included during programming to prevent (or mask out)
any potential runt pulses or extended pulses which might occur in the internal delay gates programming switching, but it is not
required for programming.
EN
LSB
MSB
PSEL
MSEL
C0
C1
D0
D1
D2
D3
D4
D5
D6
D7
D8
SDIN
SCLK
SLOAD
ts SDIN to
SCLK
C2
C3
C4
C5
C6
C7
C8
C9
C10
ts SCLK to SLOAD
th SDIN to SCLK
tpwmin
Figure 8. SDI Timing Diagram
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NB6L295
Table 7 shows theoretical values of delay capabilities in both the Dual Delay Mode and in the Extended Delay Modes of
operation.
Table 7. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN DUAL MODE
INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1
Dual Mode
PD1 D[8:0]
(Decimal)
PD0 D[8:0]
(Decimal)
MSEL
PD0 Delay* (ps)
PD1 Delay* (ps)
000000000
(0)
000000000
(0)
0
0
0
000000000
(0)
000000001
(1)
0
11
0
000000000
(0)
000000010
(2)
0
22
0
000000000
(0)
000000011
(3)
0
33
0
000000000
(0)
000000100
(4)
0
44
0
000000000
(0)
000000101
(5)
0
55
0
000000000
(0)
000000110
(6)
0
66
0
000000000
(0)
000000111
(7)
0
77
0
000000000
(0)
000001000
(8)
0
88
0
•
•
•
•
•
•
•
•
•
000000000
(0)
000010000
(16)
0
176
0
000000000
(0)
000100000
(32)
0
352
0
000000000
(0)
001000000
(64)
0
704
0
000000000
(0)
111111101
(509)
0
5599
0
000000000
(0)
111111110
(510)
0
5610
0
000000000
(0)
111111111
(511)
0
5621
0
*Fixed minimum delay not included
Table 8. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN EXTENDED MODE
INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1
Extended Delay Mode
PD1 D[8:0]
(Decimal)
PD0 D[8:0]
(Decimal)
MSEL
PD0* (ps)
PD1* (ps)
Total Delay* (ps)
000000000
(0)
000000000
(0)
1
0
0
0
000000000
(0)
000000001
(1)
1
0
11
11
000000000
(0)
000000010
(2)
1
0
22
22
000000000
(0)
000000011
(3)
1
0
33
33
•
•
•
•
•
•
•
•
•
•
•
•
000000000
(0)
111111101
(509)
1
0
5599
5599
000000000
(0)
111111110
(510)
1
0
5610
5610
000000000
(0)
111111111
(511)
1
0
5621
5621
000000001
(1)
111111111
(511)
1
11
5621
5632
000000010
(2)
111111111
(511)
1
22
5621
5643
•
•
•
•
•
•
•
•
•
•
•
•
111111100
(508)
111111111
(511)
1
5588
5621
11209
111111101
(509)
111111111
(511)
1
5599
5621
11220
111111110
(510)
111111111
(511)
1
5610
5621
11231
111111111
(511)
111111111
(511)
1
5621
5621
11242
*Fixed minimum delay not included
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9
NB6L295
VTx
VCC
50 W
INx
I
INx
50 W
VTx
Figure 9. Input Structure
VCC
Vthmax
INx
VIH
VIHmax
VILmax
Vth
VIH
Vth
VIL
Vth
VIL
Vthmin
INx
Figure 10. Differential Input Driven
Single−Ended
Figure 11. Vth Diagram
INx
INx
INx
INx
Figure 12. Differential Inputs
Driven Differentially
VIHD(MAX)
VILD
VILD
VINPP = VIH(INx) − VIL(INx)
Qx
VOUTPP = VOH(Qx) − VOL(Qx)
Qx
VIHD(MIN)
GND
VIHD
INx
INx
VIHD
VID = VIHD − VILD
VID = |VIHD(INx) − VILD(INx)|
Figure 13. Differential Inputs Driven
Differentially
VILD(MAX)
VCMR
VILmin
GND
Vth
VCC
VIHmin
tPD
tPD
VILD(MIN)
Figure 14. VCMR Diagram
Figure 15. AC Reference Measurement
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10
NB6L295
VCC
VCC
INx
VCC
VCC
INx
NB6L295
Zo = 50 W
LVPECL
Driver
50 W
VTx
VTx
50 W
50 W*
VTx
LVDS
Driver
VTx
Zo = 50 W
50 W*
Zo = 50 W
VTx = VTx INx
INx
VTx = VTx = VCC − 2.0 V
GND
NB6L295
Zo = 50 W
GND
GND
Figure 16. LVPECL Interface
GND
Figure 17. LVDS Interface
VCC
VCC
INx
NB6L295
Zo = 50 W
CML
Driver
VTx
50 W*
VTx
50 W*
VCC
Zo = 50 W
INx
VTx = VTx = VCC
GND
GND
Figure 18. CML Interface, Standard 50 W Load
VCC
VCC
INx
VCC
VCC
INx
NB6L295
Zo = 50 W
Differential
Driver
NB6L295
Zo = 50 W
50 W*
VTx
Single−Ended
Driver
VREFAC
VTx
50 W*
VTx
50 W*
VTx
50 W*
VREFAC
Zo = 50 W
INx
INx
VTx = VTx = External VREFAC
GND
VTx = VTx = External VREFAC
GND
GND
Figure 19. Capacitor−Coupled Differential
Interface (VTx/VTx Connected to VREFAC;
VREFAC Bypassed to Ground with 0.1 mF
Capacitor)
GND
Figure 20. Capacitor−Coupled Single−Ended
Interface (VTx/VTx Connected to External VREFAC;
VREFAC Bypassed to Ground with 0.1 mF Capacitor)
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11
NB6L295
Z = 50 W
Q
Driver
Device
D
Receiver
Device
Z = 50 W
Q
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 21. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
VOUTPP, TYPICAL OUTPUT VOLTAGE
AMPLITUDE (mV)
800
700
600
500
400
300
200
100
0
0
0.5
1.0
1.5
2.0
fOUT, CLOCK OUTPUT FREQUENCY (GHz)
Figure 22. Output Voltage Amplitude (VOUTPP) vs.
Output Frequency at Ambient Temperature (Typical)
ORDERING INFORMATION
Package
Shipping†
NB6L295MNG
QFN−24
(Pb−free)
92 Units / Rail
NB6L295MNTXG
QFN−24
(Pb−free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
NB6L295
PACKAGE DIMENSIONS
QFN24, 4x4, 0.5P
MN SUFFIX
CASE 485L−01
ISSUE A
D
A
PIN 1
IDENTIFICATION
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
B
E
2X
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
L
0.15 C
2X
0.15 C
A2
0.10 C
A
0.08 C
A3
A1
SEATING
PLANE
REF
D2
e
L
7
C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.60
0.80
0.20 REF
0.20
0.30
4.00 BSC
2.70
2.90
4.00 BSC
2.70
2.90
0.50 BSC
0.30
0.50
12
6
13
E2
24X
b
1
0.10 C A B
18
24
19
e
0.05 C
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NB6L295/D