INTERSIL X60250

X60250
®
Data Sheet
September 14, 2005
Micro Power Programmable Voltage
Reference
PROGRAMMABLE VOLTAGE
REFERENCE APPLICATIONS
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FEATURES
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FN8146.1
1.25V 1.0%, 20ppm/°C Tempco Reference
Adjustable to ±0.25% Over the 0 to 1.25V Range
8 bit, 100kΩ XDCP on-chip
Programmable Resolution of 4.9mV (255 steps)
Extra Matched 100kΩ Resistor Available for
Increased Resolution Over a Smaller Range
2.7V to 5.5V Supply Range
2-Wire Interface for Programming Reference
Setting
Low Supply Current: 12µA in Normal Mode
8-pin TSSOP Package
Programmable Reference
NV Memory
Pb-Free Plus Anneal Available (RoHS Compliant)
Sensor Bias
Variable DAC reference
Linear Voltage Regulators
DC/DC converters
Voltage comparators
Motor controllers
Amplifier biasing
DESCRIPTION
The Intersil X60250 combines a temperature
compensated voltage reference with a Intersil Digitally
Controlled Potentiometer (XDCP) to provide a precision
adjustable reference with a range of 0.0V to 1.25V. The
device includes a serial bus interface to enable in-circuit
programming of the reference voltage.
The XDCP contains a resistor chain with 255 taps to
provide 8 bits of digital adjustment to the reference
voltage. Non-volatile storage retains the digital wiper
setting, for permanent reference programming. An
additional matched 100kΩ resistor is available to
increase resolution of the output voltage while retaining
accuracy.
IC BLOCK DIAGRAM
VCC
VREFOUT
Pwr On Recall
1.25V
Reference
100K
256 Tap DCP
EE
PROM
SCL
VOUT
R1
Serial
Interface
SDA
100kΩ
Digital Wiper
Control
GND
1
VREFL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X60250
Ordering Information
PART NUMBER
PART MARKING
OUTPUT VOLTAGE
(V)
RESOLUTION
TEMP RANGE (°C)
PACKAGE
X60250V8I
60250 I
1.250
8 bits
-40 to 85
8 Ld TSSOP
X60250V8IZ (Note)
60250I Z
1.250
8 bits
-40 to 85
8 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
TSSOP
VREFL
1
8
SCL
VCC
2
7
SDA
VREFOUT
3
6
GND
VOUT
4
5
R1
PIN ASSIGNMENTS
TSSOP
Symbol
1
VREFL
2
VCC
3
VREFOUT
4
VOUT
Description
DCP and auxiliary resistor reference input
Positive Power Supply
Bandgap Reference Output
DCP Wiper Output
5
R1
6
GND
Ground
7
SDA
Serial Data Input/Output
8
SCL
Serial Clock Input
2
Auxiliary resistor input
FN8146.1
September 14, 2005
X60250
ABSOLUTE MAXIMUM RATINGS
COMMENTS
Supply Voltage Range...................................-1V to 7V
Bias Temperature Range .................... -40°C to +85°C
Storage Temperature Range............. -65°C to +150°C
Voltage on VREF(LOW) pin .............................0V to VCC
Voltage on all other pins ................ -0.3V to VCC+0.3V
Lead temperature (soldering, 10 seconds) ........ 300°C
Absolute Maximum Ratings indicate limits beyond
which permanent damage to the device and impaired
reliability may occur. These are stress ratings provided
for information only and functional operation of the
device at these or any other conditions beyond those
indicated in the operational sections of this specification
are not implied.
RECOMMENDED OPERATING CONDITIONS
Min
Max
Temperature
-40°C
+85°C
Supply Voltage
2.7V
5.5V
For guaranteed specifications and test conditions, see
Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
ELECTRICAL CHARACTERISTICS
(Over operating conditions unless otherwise specified. IOUT = 12.5 µA, R1 = N/C (Floating).)
ANALOG PARAMETERS
Limits
Symbol
Parameter
Min.
Typ. (1)
Max.
Unit
2.7
3.0
5.5
V
20
µA
RL=0, VREFL, VOUT, RAUX = floating
µA
RL=0, VREFL, VOUT, RAUX = floating
TA = 25°C
Test Conditions
Power Supply
VCC
Supply Voltage Range
IQ
Supply Current
VCC = 2.7V
VCC = 3V
VCC = 5.5V Write
IQ(NV)
15
60
Non-Volatile Supply Current
VCC = 2.7V
VCC = 3V
VCC = 5.5V
1100
600
1300
Reference Output Voltage
DC Parameters
VREFOUT
Output Voltage
1.237
VREFL
DCP and auxilliary resistor
reference input
GND
TCOref
Temperature coefficient of
VREF output voltage
PSRR
Power Supply Rejection
IOUT
Output Current
Sourcing
Sinking
1
ROUT
Output Impedance
1
ISC
Short Circuit Current
Sourcing
Sinking
5
0
CL
Load Capacitance
3
1.250
20
55
1.263
V
VREFOUT
V
70
ppm/°C
dB
(6)
400
µA
(2)
2.5
Ω
Given by ROUT = (∆VREF/∆IOUT) (2)
66
0.001
(2, 5)
0.003
mA
At 5.5V
µF
Reference output stable for all CL up
to specifications (2)
FN8146.1
September 14, 2005
X60250
ANALOG PARAMETERS (CONTINUED)
Limits
Symbol
Parameter
Typ. (1)
Min.
Max.
Unit
Test Conditions
AC Parameters
VN
µVP-P 0.1Hz to 10Hz (2)
µVRMS 10Hz to 10kHz (2)
Output Voltage Noise
100
200
Power-on Response
250
µs
1% Settling (2)
Line Ripple Rejection
60
dB
VDD = 3V ±100mV, f = 120 Hz (2)
Reference DCP
Resolution
8
bits
100
115
kΩ
Wiper Resistance
VCC = 2.7V
VCC = 3V
Ω
600
5000
1200
Absolute Linearity (INL)
±0.2
LSB
Relative Linearity (DNL)
±0.1
LSB
RTOT Temperature Coeff.
±300
ppm/°C
Ratiometric Temp. Coeff.
±20
ppm/°C
RTOT
End to end resistance
RW
85
(2)
RAUX (Auxiliary Resistor)
RTOT
End to end resistance
85
100
RTOT Temperature Coeff.
115
kΩ
±300
ppm/°C RL=0, VREFL, VOUT, RAUX = floating
DCP Matching Tolerance
0.1
%
DCP Matching Temp. Coeff.
±20
ppm/°C
DIGITAL PARAMETERS
Limits
Symbol
Parameter
Min.
Typ. (1)
Max.
Unit
Test Conditions
ILI
Input Leakage Current
2
µA
VIN = GND to VCC
ILO
Output Leakage Current
2
µA
VOUT = GND to VCC
VIL
Input Low Voltage
0
VCC x 0.2
V
VIH
Input High Voltage
VCC x 0.7
VCC
V
CIN
Input Capacitance
VOL
Output Low Voltage
0
10
%VDD
IOL = 100 µA (2)
VOH
Output High Voltage
90
100
%VDD
IOH = 100 µA (2)
CL
Output Load
100
pF
5
pF
(2)
EEPROM PARAMETERS (Erase at VCC = 5.0 V min, T = 25°C)
Parameter
Min.
Units
Write Cycle Endurance
100,000
Cycles per bit
CAPACITANCE
Symbol
Test
Max.
Units
Test Conditions
CIN/OUT
Input/Output capacitance (SDA)
8
pF
VOUT = 0V (2)
CIN
Input capacitance (SCL)
6
pF
VIN = 0V (2)
4
FN8146.1
September 14, 2005
X60250
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing threshold level
VCC x 0.5
External load at pin SDA
2.3kΩ to VCC and 100 pF to VSS
AC SPECIFICATIONS
Symbol
fSCL
Parameter
SCL Clock Frequency
tIN
Pulse width Suppression Time at inputs
tAA
SCL LOW to SDA Data Out Valid
(2)
Min.
Max.
Unit
0
400
kHz
50
(2)
ns
0.1
tBUF
Time the bus must be free before a new transmission can start
tLOW
tHIGH
(2)
0.9
µs
1.3
µs
Clock LOW Time
1.3
µs
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
0.6
µs
50
ns
tSU:STO
Stop Condition Setup Time
tDH
Data Output Hold Time
(2)
(2)
(2, 3)
tR
SDA and SCL Rise Time
tF
SDA and SCL Fall Time (2, 3)
Cb
Capacitive load for each bus line (2, 3)
20 +.1Cb
300
ns
20 +.1Cb
300
ns
400
pF
TIMING DIAGRAMS
Bus Timing
tBUF
tF
tHIGH
tR
tLOW
tBUF
SCL
tSU:STA
SDA IN
tSU:DAT
tHD:STA
tHD:DAT
tSU:STO
tAA
tDH
tHD:STO
tHD:DAT
SDA OUT
5
FN8146.1
September 14, 2005
X60250
WRITE CYCLE TIMING
SCL
8th Bit of Last Byte
SDA
ACK
tWC
Stop
Start
Condition
Condition
POWER-UP TIMING
Symbol
Parameter
∆VCC/∆t
(2)
tPUR
tPUW
VCC Power-up rate
Time from Power-up to
Min.
Max.
Unit
0.2
50
V/ms
Read (2)
1
ms
(2)
5
ms
Time from Power-up to Write
NONVOLATILE WRITE CYCLE TIMING
Symbol
tWC
Parameter
Write Cycle Time
(4)
Min.
Typ.
Max.
Unit
5
10
ms
Notes: (1)
(2)
(3)
(4)
Typical values are for TA = 25°C and VCC = 3.0V
This parameter is guaranteed by characterization.
Cb = total capacitance of one bus line in pF.
tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile
write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
(5) Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in
VOUT is divided by the temperature range; in this case, -40°C to +85°C = 125°C. TCOref = [Max V(VREF) - Min V(VREF)] ×
106 / (1.25V × 125°C)
6
FN8146.1
September 14, 2005
X60250
FUNCTIONAL DESCRIPTION
The X60250 combines a micropower precision reference
with an 8-bit, 256 tap digitally controlled 100kΩ
potentiometer (DCP) which allows nonvolatile setting of
an output reference voltage. When normally configured
with the VREFL pin tied to ground, the device provides an
output range of 0V to 1.25V with 4.90mV resolution.
The device can also be configured with an optional
100kΩ series resistor to ground, which effectively halves
the output voltage range while doubling the resolution.
Grounding the R1 pin while floating the VREFL pin places
the device in this mode. Output voltage setting accuracy
can be as high as 0.10% while permitting adjustment
from 0.625V to 1.25V (2.45mV resolution).
Reference Section
The reference is designed to provide an accurate, low
tempco voltage source while requiring less than 12µA
(typical) of supply current. This supply current is for the
reference section only. Keep in mind that the DCP will
increase supply current draw by VREF/RTOTAL
(typically 1.25/100k or 12.5µA). The total current drawn
by the adjustable reference circuit will be less than 25µA
(typically).
The reference output has a typical impedance of 1Ω and
can provide up to 400µA of load current. It is intended to
drive the resistive load of the DCP, which is a minimum
of 85kΩ, but can also be used to drive off chip circuitry
provided the loading does not exceed the 400µA
maximum. Also, highly capacitive loads can make the
reference oscillate, so no more than 2000pF should be
placed directly on the output of the VREFOUT pin.
The reference output produces about 200µV RMS of
noise (10kHz bandwidth) due to its micropower design.
This is easily reduced in normal applications, as shown in
the applications section for optimizing circuits for
reducing output noise levels.
DCP Section
The 256 tap DCP has an 8-bit nonvolatile wiper control
register which controls which tap is selected. The
register is changed by performing a serial data write to its
address (0h, see Serial Interface section). The resulting
wiper position will produce an output voltage at VOUT,
depending on whether the DCP VREFL is grounded or the
R1 pin is grounded. The wiper consists of CMOS
transistors and has a finite resistance, typically 600Ω at
VCC = 5V (this parameter increases with decreasing
VCC). The wiper resistance will produce errors in
reference circuits due to I-R drops if current flows
through the wiper. However, typically these circuits will
have the wiper connected to a high impedance
comparator or amplifier input which results in very small
7
wiper currents and thus only a small output voltage error.
If the X60250 is used with the wiper connected to VREFL
to produce a current source, care must be taken to avoid
exceeding the maximum output current of the reference
(typically 400µA).
Power-Up considerations
The X60250 contains EEPROM nonvolatile storage cells
which are recalled during power-up. This recall process
works best with power supply (VCC) ramping that is
monotonic and free of excessive glitches (<100mV
disturbances give best results). The ramp rate spec
should be adhered to, although the most sensitive part of
recall is between VCC = 1.0V and 2.5V. Effort should be
made to make sure the device receives a power-up ramp
between those voltage levels that meet the ramp rate
spec and have no glitches.
Recall of the stored wiper position happens in < 1ms
from VCC reaching 2.5V. Note that any excursions of VCC
below 2.5V, although temporary, can cause the wiper to
be loaded with the midpoint value (80h) until VCC
recovers to its normal voltage.
Register Organization
There are 2 nonvolatile registers and 1 volatile register
available for storage and recall via the serial bus. They
contain the current wiper position, a general purpose
data register and a status register.
The wiper register is nonvolatile and is at address 0h and
contains 8 bits, with the 00h setting corresponding to the
tap position nearest VREFL, and the FFh setting nearest
to VREFOUT.
The general purpose register is nonvolatile and is at
address 1h, and contains 8 bits for use as scratchpad
memory or serial number information.
The Status register is volatile and is at address 7h. It has
one active bit, D3, which is the WEL bit. This bit must be
set to 1 berfore any nonvolatile writes are performed to
the other registers. See the register information on the
next page.
FN8146.1
September 14, 2005
X60250
X60250 REGISTER BIT MAP
Addr
D7
D6
D5
D4
D3
D2
D1
D0
0
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
7
0
0
0
0
WEL
0
0
0
REGISTER DESCRIPTIONS
Reg
Nonvolatile
0
1
7
Description
VOUT wiper setting
General Purpose data storage register
Status register
Y
Y
N
REGISTER 0 (NONVOLATILE)
This register is used to hold the DCP wiper position, which is given by:
Code
V OUT = V REF × --------------- (with
255
VREFL = GND)
REGISTER 1 (NONVOLATILE)
This 8 bit register is used for general storage such as date code, temp setting, etc.
STATUS REGISTER
Bit
Value
D - D4
D3
0
0-1
D2 - D0
0
Description
Must remain 0
WEL bit
Must be programmed to "1" for Reg 0 or 1 EEPROM
write. When accessing, only WEL bit may be changed
Must remain 0
8
FN8146.1
September 14, 2005
X60250
X60250 BUS INTERFACE INFORMATION
Figure 1. Slave Address, Word Address, and Data Bytes - Write Mode
Slave Address*
Device Identifier
Slave Address Byte
0
1
0
1
0
0
0/1
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Byte 0
Byte Address
Byte 1
Data Byte
Byte 2
Figure 2. Slave Address, Word Address, and Data Bytes - Read Mode
Slave Address*
Device Identifier
0
1
0
1
0
0
0/1
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Slave Address Byte
Byte 0
Data Byte
9
Byte 1
Data Byte
Byte 2
FN8146.1
September 14, 2005
X60250
X60250 BUS INTERFACE INFORMATION
Pin Descriptions
Slave Address, Address Byte, and Data Byte
VREFOUT
The byte communication format for the serial bus is
shown in Figure 1 on the previous page. The first byte,
BYTE 0, defines the device identifier, 0101 in the upper
half; and the device slave address in the low half of the
byte. The slave address is set to 0. The next byte,
BYTE 1, is the Address Byte. The Address Byte
identifies a unique address for the Status or Control
Registers as shown in the Register Descriptions table.
The following byte, Byte 2, is the byte used for READ
and WRITE operations.
Reference voltage output.
The 1.25V bandgap
reference output (VREF) is available at this pin for
application to other circuits. Maximum output current is
400µA. The VREFOUT pin also connects to the Rh
terminal of the 256-tap DCP.
Start Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. On powerup, the SCL pin must be brought LOW prior to the
START condition. See Figure 3.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH followed by a HIGH to LOW
transistion on SCL. After going LOW, SCL can stay LOW
or return to HIGH. See Figure 3.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 4. The device will
respond with an acknowledge after recognition of a start
condition and if the correct Device Identifier and Select
bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
acknowledge after the receipt of each subsequent eight
bit word. The device will acknowledge all incoming data
and address bytes, except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– The 2nd Data Byte of a Status Register Write Operation (only 1 data byte is allowed)
10
VOUT
DCP Wiper Output. This pin functions as the wiper of the
DCP, and can be used as a variable voltage source for
voltages between GND and VREF . Since it is connected
to the DCP resistor, any loads on this pin must be high
impedance for best performance.
R1
Auxiliary Resistor Input. The R1 pin is connected to one
end of a 100kΩ resistor (R1) which closely matches the
DCP resistance. The other end of R1 is tied to the RREFL
terminal of the DCP. When R1 is grounded and VREFL is
left open, the output voltage range of VOUT will be from
VREF/2 to VREF , and the effective resolution (mV/step) of
the Reference control is doubled. R1 should be left open
if not used.
GND
This pin is common for the VREF output and for control
signal inputs.
SDA
Serial Data Input/Output. Bidirectional pin used for serial
data transfer. As an output, it is open drain and may be
wire-ored with any number of open drain or open
collector outputs. A pullup resistor is required and the
value is dependent on the speed of the serial data bus
and the number of outputs tied together.
SCL
Serial Clock Input. Accepts a clock signal for clocking
serial data into and out of the device.
VREFL
DCP and Auxiliary Resistor Input. This pin is connected
to one end of the 256-tap DCP, and also to one end of
the 100kΩ auxiliary resistor. When connected to ground,
VOUT range will be from 0V to VREF . When left open
and R1 is connected to ground, the voltage at this pin will
be from VREF/2 to VREF .
FN8146.1
September 14, 2005
X60250
Figure 3. Valid Start and Stop Conditions
VCC
Positive Power Supply. Connect to a voltage supply in
the range of 2.7V < VCC < 5.5V, with minimum noise and
ripple. For best performance, bypass with a 0.1µF
capacitor to ground.
SCL
SDA
Start
Stop
Figure 4. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
11
Data Change
Data Stable
FN8146.1
September 14, 2005
X60250
Figure 6. Byte Write Sequence
Signals from
the Master
SDA Bus
S
t Device
a
ID
r
t
01 0 1 0
Slave
Address*
Byte
Address 0
S
t
o
p
Data
0 0/1 0
A
C
K
Signals From
The Slave
A
C
K
A
C
K
*Note: The X60250 will respond to either 000 or 001 slave addresses.
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array.
Upon receipt of each address byte, the X60250 responds
with an acknowledge. After receiving the address bytes
the X60250 awaits the eight bits of data. After receiving
the 8 data bits, the X60250 again responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition. The X60250 then begins an
internal write cycle of the data to the nonvolatile memory.
During the internal write cycle, the device inputs are
disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance.
See Figure 6.
A write to a protected block of memory is ignored, but will
still receive an acknowledge. At the end of the write
command, the X60250 will not initiate an internal write
cycle, and will continue to okay commands.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and its associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X60250 resets itself without performing the
write. The contents of the array are not affected.
Figure 7. Random Address Read Sequence
Signals from the
Master
S
t
a
r
t
SDA Bus
Device
ID
01 0 1 0
Slave
Address
Byte
Address 0
0 0/1 0
Random Address Read
Random read operation allows the master to access any
location in the X60250. Prior to issuing the Slave
Address Byte, the master must first perform a “dummy”
write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues the
word address bytes. After acknowledging receipt of each
word address byte, the master immediately issues
another start condition and the slave address byte. This
is followed by an acknowledge from the device and then
by the eight bit data word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. Refer to Figure 7 for
the address, acknowledge, and data transfer sequence.
12
Device
ID
01 0 1 0
A
C
K
Signals from
the Slave
S
t
a
r
t
A
C
K
S
t
o
p
Slave
Address
0
0 1
A
C
K
Data
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 7. The X60250 then goes
into standby mode after the stop and all bus activity will
be ignored until a start is detected. This operation loads
the new address into the address counter. The next
Current Address Read operation will read from the newly
loaded address. This operation could be useful if the
master knows the next address it needs to read, but is
not ready for the data.
FN8146.1
September 14, 2005
X60250
TYPICAL PERFORMANCE CHARACTERISTIC CURVES
VRefout vs Temperature (2 representative units)
1.25120
1.2550
1.25070
1.2540
Refout
1.25020
R f
1.2530
t
1.2520
VREFOUT (V)
VRefout (V)
1.24970
IREFOOUT vs VREFOUT
1.24920
1.24870
1.24820
+25 deg C
1.2510
1.2500
-40 deg C
1.2490
1.2480
1.24770
+85 deg C
1.2470
1.24720
1.2460
1.24670
1.24620
-50
1.2450
0.00
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
0.10
0.20
0.30
100
VRefout vs Vcc
0.60
0.70
0.80
50.00E-6
Refout (-40C)
Refout (25C)
Refout (85C)
1.256E+0
1.255E+0
Icc (-40C)
Icc (25C)
Icc (85C)
45.00E-6
40.00E-6
1.254E+0
35.00E-6
Icc (A)
VRefout (V)
0.50
Icc vs Vcc
1.257E+0
1.253E+0
1.252E+0
30.00E-6
25.00E-6
1.251E+0
20.00E-6
1.250E+0
1.249E+0
2.50
0.40
IREFOUT (mA)
Temperature (C)
15.00E-6
3.00
3.50
4.00
4.50
5.00
5.50
6.00
Vcc (V)
10.00E-6
2.50
3.00
3.50
4.00
4.50
5.00
5.50
Vcc (V)
Vref Output Voltage Noise, 0.1Hz to 10Hz
VREF Output Noise Spectrum
10
9
Filter = 1 zero at 0.1Hz
2 poles at 10Hz
Noise, uV/rt*Hz
8
7
6
5
4
3
2
1
Vertical = 50µV/div
Horizontal = 1 sec/div
0
10
100
1000
10000
Frequency
DNL
0.50
0.40
0.40
0.30
0.30
0.20
0.20
ERROR (LSB)
ERROR (LSB)
INL
0.50
0.10
0.00
-0.10
0.10
0.00
-0.10
-0.20
-0.20
-0.30
-0.30
-0.40
-0.40
-0.50
-0.50
0
50
100
150
Tap Position
13
200
250
0
50
100
150
200
250
Tap Position
FN8146.1
September 14, 2005
X60250
TYPICAL PERFORMANCE CHARACTERISTIC CURVES (Continued)
Power On Settling Time
Figure 9. Using Auxilliary Resistor
APPLICATIONS INFORMATION
Standard Reference configurations
Figure 8 shows the device connections to produce a 0
to 1.250V adjustable reference with 8 bits of resolution.
VREFL will be grounded in this case. Figure 9 has
device connections to produce a 0.625V to 1.250V
reference with 8 bits of resolution, with R1 grounded.
This configuration effectively doubles the output voltage
control resolution, increasing the accuracy of the
desired reference output voltage. Since the auxiliary
resistor is matched to the DCP resistor, temperature
drift is minimized.
VREFOUT
VOUT
1.25V
Reference
100K
0.625V to 1.25V
Range
R1
100K
GND
VREFL
Figure 8. Standard Configuration
VREFOUT
Reducing Output Noise
VOUT
1.25V
Reference
100K
R1
100K
GND
VREFL
Adjusted
Reference
Voltage
0.0 to 1.25V Range
The output noise voltage of the reference is typically
200µV rms in the 10kHz bandwidth. An advantage of the
adjustable reference configuration is the ease in filtering
this noise. Simply adding a capacitor to the VOUT pin will
produce a single pole filter with a corner frequency of:
1
F CORNER = --- × π × R DCP × C FILTER
2
RDCP will vary with tap position and wiper resistance. If
the approximate tap position of the DCP is known, it can
be used to calculate this resistance as follows:
255 – tapw
#- × R

||  tapw
--------------#
R DCP = ----------------------------TOTAL  255 × R TOTAL + R WIPER
255
For example, with VCC = 5V, tap # = 127 (corresponding
to VOUT = 0.623V), CFILTER = 0.1µF, using typical values:
R DCP = 25K + 0.6K = 25.6kΩ
F CORNER = 62Hz
14
FN8146.1
September 14, 2005
X60250
Since this is a single pole rolloff, the actual noise
bandwidth is 1.57 times this, or 97Hz. This should
reduce typical output noise to about 45µV rms. Note that
if the wiper is set to the highest tap positon (tap# = 255)
to give a VOUT of 1.25V, the resulting RDCP = RWIPER or
600Ω, and the filter bandwidth will now be 2.6kHz,
increasing noise significantly. If tap positions near
VREFOUT will be used, then a series resistor ROUT should
be added to better control noise bandwidth.
Figure 10. Reducing Output Noise
VREFOUT
ROUT
VOUT
1.25V
Reference
100K
R1
(optional)
Filtered
Reference
Voltage
CFILTER
Higher Reference Voltages
If a reference voltage higher than 1.25V is required, then
an opamp can be added to amplify the VOUT voltage.
There are many micropower opamps available, such as
the LMV341, which can produce an output at very close
to either supply rail. Figure 11 shows a circuit for a 0V to
5.0V adjustable reference, which has 8 bits of control.
Note that if the auxiliary resistor is connected to ground
instead of VREFL, then the output voltage range will be
2.5V to 5.0V, but resolution will double. Total current
draw from that circuit will be 156µA (typically, with
VOUT = 5V) including reference and opamp circuitry.
Note that due to VCC supply variations, the output may
not span up to 5.00V which would result in missing codes
at the top end of the DCP range.
Figure 11. Increasing Reference Output Voltage
VREFOUT
+5V
100K
GND
R1 20K
1.25V
Reference
VREFL
100K
CFILTER
5
1
3
+
6
4
0 to
5.0V
LMV341
–
2
100K
100K
GND
15
33K
VREFL
FN8146.1
September 14, 2005
X60250
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
(4.16) (7.72)
Detail A (20X)
(1.78)
.031 (.80)
.041 (1.05)
See Detail “A”
(0.42)
(0.65)
All Measurements Are Typical
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN8146.1
September 14, 2005