HUF76139P3, HUF76139S3S Data Sheet 75A, 30V, 0.0075 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs These N-Channel power MOSFETs are manufactured using the innovative UltraFET™ process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. September 1999 File Number 4399.5 Features • Logic Level Gate Drive • 75A, 30V • Ultra Low On-Resistance, rDS(ON) = 0.0075Ω • Temperature Compensating PSPICE® Model • Temperature Compensating SABER© Model • Thermal Impedance SPICE Model • Thermal Impedance SABER Model • Peak Current vs Pulse Width Curve • UIS Rating Curve Formerly developmental type TA76139. • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information Symbol PART NUMBER PACKAGE BRAND HUF76139P3 TO-220AB 76139P HUF76139S3S TO-263AB 76139S D G NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF76139S3ST. S Packaging JEDEC TO-220AB JEDEC TO-263AB SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) GATE SOURCE 6-154 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation. SABER is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HUF76139P3, HUF76139S3S3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 30 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 30 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 75 64 61 Figure 4 A A A Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 17, 18 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 1.35 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -40 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 30 - - V VDS = 25V, VGS = 0V - - 1 µA VDS = 25V, VGS = 0V, TC = 150oC - - 250 µA VGS = ±16V - - ±100 nA OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250µA, VGS = 0V (Figure 12) ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figures 9, 10) - 0.0065 0.0075 Ω ID =64A, VGS = 5V (Figure 9) - 0.0082 0.010 Ω ID = 61A, VGS = 4.5V (Figure 9,) - 0.009 0.011 Ω THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RθJC (Figure 3) - - 0.74 oC/W Thermal Resistance Junction to Ambient RθJA TO-220AB, TO-263AB - - 62 oC/W tON VDD = 15V, ID ≅ 61A, RL = 0.246Ω, VGS = 4.5V, RGS = 4.5Ω (Figures 15, 21, 22) - - 255 ns - 20 - ns - 150 - ns td(OFF) - 30 - ns tf - 40 - ns tOFF - - 105 ns SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Turn-Off Time 6-155 HUF76139P3, HUF76139S3S Electrical Specifications TA = 25oC, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - - 120 ns - 16 - ns - 65 - ns td(OFF) - 90 - ns tf - 55 - ns tOFF - - 218 ns - 65 78 nC - 38 46 nC - 2.5 3 nC SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID ≅ 75A RL = 0.200Ω, VGS = 10V, RGS = 10Ω (Figures 16, 21, 22) GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 10V Gate Charge at 5V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Threshold Gate Charge VDD = 15V, ID ≅ 64A, RL = 0.234Ω Ig(REF) = 1.0mA (Figures 14, 19, 20) Gate to Source Gate Charge Qgs - 7.60 - nC Gate to Drain “Miller”Charge Qgd - 18.40 - nC - 2700 - pF - 1100 - pF - 200 - pF MIN TYP MAX UNITS ISD = 75A - - 1.25 V trr ISD = 75A, dISD/dt = 100A/µs - - 85 ns QRR ISD = 75A, dISD/dt = 100A/µs - - 160 nC CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Reverse Recovery Time Reverse Recovered Charge TEST CONDITIONS Typical Performance Curves 80 VGS = 10V 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 60 VGS = 4.5V 40 20 0.2 0 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 6-156 150 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE HUF76139P3, HUF76139S3S Typical Performance Curves (Continued) 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3000 TC = 25oC IDM, PEAK CURRENT (A) FOR TEMPERATURES ABOVE 25oC DERATE PEAK 1000 CURRENT AS FOLLOWS: I VGS = 10V = I25 175 - TC 150 VGS = 5V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 FIGURE 4. PEAK CURRENT CAPABILITY TJ = MAX RATED TC = 25oC ID, DRAIN CURRENT (A) 1000 100µs 100 1ms 10ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) IAS, AVALANCHE CURRENT (A) 1000 2000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC 10 0.001 100 STARTING TJ = 150oC 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 6-157 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY HUF76139P3, HUF76139S3S Typical Performance Curves 160 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX -40oC VGS = 10V VGS = 5V VGS = 4.5V 25oC 150oC ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 160 (Continued) 120 80 40 VGS = 3.5V 80 VGS = 3V 40 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC VDD = 15V 0 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) 0 6 FIGURE 7. TRANSFER CHARACTERISTICS 2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ON RESISTANCE (mΩ) rDS(ON), DRAIN TO SOURCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 50A 12 10 ID = 25A 8 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 75A 1.5 1.0 0 60 120 TJ, JUNCTION TEMPERATURE (oC) 180 FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA 1.0 0.8 0.6 0.4 -60 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.5 -60 6 NORMALIZED GATE THRESHOLD VOLTAGE 0 FIGURE 8. SATURATION CHARACTERISTICS 14 ID = 75A VGS = 4V 120 0 60 120 180 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 6-158 ID = 250µA 1.1 1.0 0.9 -60 0 60 120 TJ , JUNCTION TEMPERATURE (oC) 180 FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE HUF76139P3, HUF76139S3S Typical Performance Curves (Continued) C, CAPACITANCE (pF) VGS , GATE TO SOURCE VOLTAGE (V) 10 4000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 3000 CISS 2000 COSS 1000 CRSS VDD = 15V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 50A ID = 25A 2 0 0 0 0 5 10 15 20 25 20 30 VDS , DRAIN TO SOURCE VOLTAGE (V) 60 80 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 800 500 VGS = 4.5V, VDD = 15V, ID = 61A, RL = 0.246Ω VGS = 10V, VDD = 15V, ID = 75A, RL= 0.2Ω SWITCHING TIME (ns) SWITCHING TIME (ns) 40 Qg, GATE CHARGE (nC) 600 tr 400 td(OFF) tf 200 400 td(OFF) 300 200 tf 100 tr td(ON) 0 td(ON) 0 0 10 20 30 40 50 0 RGS, GATE TO SOURCE RESISTANCE (Ω) 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01Ω tAV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT 6-159 FIGURE 18. UNCLAMPED ENERGY WAVEFORMS HUF76139P3, HUF76139S3S Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 10 VGS Qg(5) + VDD VGS = 5V VGS DUT VGS = 1V Ig(REF) 0 Qg(TH) Ig(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + VGS - VDD 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 21. SWITCHING TIME TEST CIRCUIT 6-160 10% 50% 50% PULSE WIDTH FIGURE 22. SWITCHING TIME WAVEFORM HUF76139P3, HUF76139S3S PSPICE Electrical Model SUBCKT HUF76139 2 1 3 ; REV April 1998 CA 12 8 3.15e-9 CB 15 14 3.15e-9 CIN 6 8 2.3e-9 LDRAIN DPLCAP DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DRAIN 2 5 10 RLDRAIN RSLC1 51 + RSLC2 EBREAK 11 7 17 18 33 .45 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 DBREAK 5 51 ESLC 11 - RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE IT 8 17 1 GATE 1 LDRAIN 2 5 4e-9 LGATE 1 9 6e-9 LSOURCE 3 7 3e-9 + 17 EBREAK 18 50 EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD SOURCE 3 7 RSOURCE RLSOURCE S1A RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 0.25e-3 RGATE 9 20 1 RLDRAIN 2 5 40 RLGATE 1 9 60 RLSOURCE 3 7 30 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.35e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 12 S2A 13 8 S1B CA RBREAK 15 14 13 17 18 RVTEMP S2B 13 CB 6 8 VBAT 5 8 EDS - - IT 14 + + EGS 19 - + 8 22 RVTHRES S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*643),8.4))} .MODEL DBODYMOD D (IS = 3.4e-12 IKF = 13 TIKF = 13 RS = 3.25e-3 TRS1 = 1.5e-3 TRS2 = 5e-6 CJO = 3.75e-9 TT = 3.8e-8 M = 0.40 XTI =5.2 ) .MODEL DBREAKMOD D (RS = 7.5e-2 TRS1 = 2e-3 TRS2 = 1e-6 IKF = 0.1) .MODEL DPLCAPMOD D (CJO = 2.05e-9 IS = 1e-30 N = 10 M = 0.65 VJ = 1.1) .MODEL MMEDMOD NMOS (VTO = 1.85 KP = 15 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1) .MODEL MSTROMOD NMOS (VTO = 2.18 KP = 155 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.35 KP =.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10) .MODEL RBREAKMOD RES (TC1 = 1.0e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 4.75e-2 TC2 = 1e-4) .MODEL RSLCMOD RES (TC1 = 2e-3 TC2 = 4e-5) .MODEL RSOURCEMOD RES (TC1 = 1.45e-3 TC2 = 5e-6) .MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -9e-6) .MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 0.5e-9) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.5 VOFF= -2.5) VON = -2.5 VOFF= -5.5) VON = 0.00 VOFF= 0.50) VON = 0.50 VOFF= 0.00) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 6-161 HUF76139P3, HUF76139S3S SABER Electrical Model REV March 1998 template huf76139 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 3.4e-12, xti = 5.2, cjo = 3.75e-9, tt = 3.8e-8, m = 0.40) d..model dbreakmod = () d..model dplcapmod = (cjo = 2.05e-9, is = 1e-30, n = 10, vj = 1.1 m = 0.65) m..model mmedmod = (type=_n, vto = 1.85, kp = 15, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.18, kp = 115, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.35, kp = 0.01, is = 1e-30, tox = 1) DPLCAP sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -2.5) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.5, voff = -5.5) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0) LDRAIN DRAIN 2 5 RSLC1 51 RLDRAIN RDBREAK RSLC2 c.ca n12 n8 = 3.15e-9 c.cb n15 n14 = 3.15e-9 c.cin n6 n8 = 2.3e-9 72 ISCL EVTHRES + 19 8 + i.it n8 n17 = 1 LGATE GATE 1 l.ldrain n2 n5 = 4e-9 l.lgate n1 n9 = 6e-9 l.lsource n3 n7 = 3e-9 RDRAIN 6 8 ESG EVTEMP RGATE + 18 22 9 20 21 DBODY EBREAK + 17 18 MSTRO CIN - 8 LSOURCE 7 RSOURCE RLSOURCE S1A 12 S2A 13 8 S1B CA RBREAK 15 14 13 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/643))** 8.4)) } } - IT 14 + + spe.ebreak n11 n7 n17 n18 = 33.45 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 6-162 MWEAK MMED m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u 71 11 16 6 RLGATE res.rbreak n17 n18 = 1, tc1 = 9.8e-4, tc2 = -4e-7 res.rdbody n71 n5 = 2.65e-3, tc1 = 2.3e-3, tc2 = -4.2e-6 res.rdbreak n72 n5 = 8.5e-2, tc1 = 0, tc2 = 0 res.rdrain n50 n16 = 0.25e-3, tc1 = 4.75e-2, tc2 = 1e-4 res.rgate n9 n20 = 1 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 60 res.rlsource n3 n7 = 30 res.rslc1 n5 n51 = 1e-6, tc1 = 2e-3, tc2 = 4e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.35e-3, tc1 = 1.45e-3, tc2 = 5e-6 res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 0.5e-9 res.rvthres n22 n8 = 1, tc1 = -2e-3, tc2 = -9e-6 DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod RDBODY VBAT 5 8 EDS - + 8 22 RVTHRES SOURCE 3 HUF76139P3, HUF76139S3S SPICE Thermal Model th JUNCTION REV March 1998 HUF76139 RTHERM1 CTHERM1 th 6 500e-2 CTHERM2 6 5 3e-2 CTHERM3 5 4 1e-2 CTHERM4 4 3 3e-2 CTHERM5 3 2 0.35e-1 CTHERM6 2 tl 1 CTHERM1 6 RTHERM2 RTHERM1 th 6 2.5e-4 RTHERM2 6 5 5e-4 RTHERM3 5 4 2.8e-3 RTHERM4 4 3 88e-3 RTHERM5 3 2 18e-2 RTHERM6 2 tl 0.5e-1 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model Saber thermal model HUF76139 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 500e-2 ctherm.ctherm2 6 5 = 3e-2 ctherm.ctherm3 5 4 = 1e-2 ctherm.ctherm4 4 3 = 3e-2 ctherm.ctherm5 3 2 = 0.35e-1 ctherm.ctherm6 2 tl = 1 4 RTHERM4 CTHERM4 3 RTHERM5 rtherm.rtherm1 th 6 = 2.5e-4 rtherm.rtherm2 6 5 = 5e-4 rtherm.rtherm3 5 4 = 2.8e-3 rtherm.rtherm4 4 3 = 88e-3 rtherm.rtherm5 3 2 = 18e-2 rtherm.rtherm6 2 tl = 0.5e-1 } CTHERM5 2 RTHERM6 CTHERM6 tl CASE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6-163