IRS2052M functional description

Application Note AN-1159
IRS2052M Functional Description
By Jun Honda, Xiao-chang Cheng
Table of Contents
1
IRS2052M General Description ................................................................................................................... 2
Typical Implementation ........................................................................................................................... 3
2
Input Section ................................................................................................................................................ 4
2.1 OTA (Operating Trans-conductance Amplifier) ....................................................................................... 5
2.2 PWM Modulator....................................................................................................................................... 5
2.3 Clock Synchronization ............................................................................................................................. 7
2.4 Click Noise Elimination .......................................................................................................................... 10
2.5 CSD Voltage and OTA Operational Mode ............................................................................................ 11
2.6 Self-oscillation Start-up Condition ......................................................................................................... 12
3
MOSFET Selection .................................................................................................................................... 13
4
Over Current Protection (OCP) ................................................................................................................. 14
4.1 Protection Control.................................................................................................................................. 15
4.2 Programming OCP Trip Level ............................................................................................................... 18
5
Over Temperature Protection .................................................................................................................... 23
5.1 Over Temperature Protection Input (OTP) ............................................................................................ 23
5.2 On-chip Over Temperature Protection .................................................................................................. 25
5.3 Over Temperature Warning Output (OTW) ........................................................................................... 25
6
Fault Output ............................................................................................................................................... 26
7
CLIP Output ............................................................................................................................................... 26
8
Deadtime Design ....................................................................................................................................... 27
8.1 How to Determine Optimal Deadtime ................................................................................................... 27
8.2 Programming Deadtime ........................................................................................................................ 28
9
Power Supply Considerations ................................................................................................................... 29
9.1 Supplying VAA and VSS .......................................................................................................................... 29
9.2 Recommended Power Supply Configuration for Gate Driver Stage ..................................................... 30
9.3 Designing High-side Bootstrap Power Supply ...................................................................................... 32
9.4 Start-up/Power-down Sequence (UVLO) .............................................................................................. 37
9.5 Power Supply Decoupling ..................................................................................................................... 38
10 Junction Temperature Estimation .............................................................................................................. 39
10.1
PMID: Power Dissipation of the Input Floating Logic and Protection Circuitry ................................... 39
10.2
PLSM: Power Dissipation of the Input Level Shifter............................................................................ 39
10.3
PLOW: Power Dissipation of Low Side ............................................................................................... 39
10.4
PLSH: Power Dissipation of the High-side Level Shifter ..................................................................... 40
10.5
PHIGH: Power Dissipation of High Side .............................................................................................. 40
10.6
PD: Total Power Dissipation .............................................................................................................. 40
10.7
TJ: Junction Temperature.................................................................................................................. 41
11 Board Layout Considerations .................................................................................................................... 42
11.1
Ground Plane .................................................................................................................................... 43
1.1
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1
IRS2052M General Description
The IRS2052M is a two channel Class D audio amplifier driver with integrated PWM modulators and over current
protection. Combined with four external MOSFETs and external passive components, the IRS2052M forms two
complete Class D amplifiers. The versatile structure of the analog input section with an error amplifier and a
PWM comparator has flexibility of implementing different types of PWM modulator schemes.
Loss-less current sensing utilizes RDS(on) of the MOSFETs. The protection control logic monitors the status of the
power supplies and load current through each MOSFET.
For the convenience of half bridge configuration, the analog PWM modulator and protection logic are constructed
on a floating well.
The IRS2052M implements start-up click noise reduction to suppress unwanted audible noise during PWM startup and shutdown.
Figure 1 Functional Block Diagram of IRS2052M
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1.1
Typical Implementation
CH1 OUTPUT
VCC
POWER GND
-B
Fosc SELECT
AGND
CLIP1
INPUT 1
-5V
+5V
INPUT 2
CLIP2
PTC
+B
CH2 OUTPUT
The following explanations are based on a typical application circuit with self-oscillating PWM topology shown in
Figure 2. For further information on the design, refer to the IRAUDAMP10 reference design.
Figure 2 IRS2052M Typical Application Circuit
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2
Input Section
The audio input stage of the IRS2052M is configured as an inverting error amplifier.
In Figure 3, the voltage gain of the amplifier GV is determined by input resistor RIN and feedback resistor RFB.
GV 
RFB
RIN
Since the feedback resistor RFB is part of an integrator time constant, which determines switching frequency,
changing overall voltage gain by RIN is simpler and, therefore, recommended in most cases.
Note that the input impedance of the amplifier is equal to the input resistor RIN.
A DC blocking capacitor C3 should be connected in series with RIN to minimize DC offset in the output.
Minimizing DC offset is essential for audible noise-less Turn-ON and -OFF. A ceramic capacitor is not
recommended due to the potential cause of distortion.
The connection of the non-inverting input IN+ is a reference for the error amplifier, and thus is crucial for audio
performance. Connect IN+ to the signal reference ground in the system, which has the same potential as the
negative terminal of the speaker output.
Figure 3 IRS2052M Typical Control Loop Design
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2.1
OTA (Operating Trans-conductance Amplifier)
The front-end error amplifier of the IRS2052M features an operational trans-conductance amplifier (OTA), which
is carefully designed to obtain optimal audio performance. The OTA outputs a current to the COMP pin, unlike a
voltage output in an operational amplifier (OPA). The non-inverting input is internally tied to the GND pin.
The inverting input has clamping diodes to GND to improve recovery from clipping as well as ensuring stable
start up. The OTA output COMP is internally connected to the PWM comparator whose threshold is (VAAVSS)/2.
For stable operation of the OTA, a compensation capacitor Cc minimum of 1nF is required. The OTA shuts down
when VCSD<Vth2.
2.2
PWM Modulator
The IRS2052M allows the user to choose from numerous ways of PWM modulator implementations. In this
section, all the explanations are based on a typical application circuit of a self-oscillating PWM.
2.2.1
Self-Oscillating PWM Modulator Design
The typical application features a self-oscillating PWM scheme. For better audio performance, front end 2nd
order integration is chosen.
2.2.2
Self-Oscillating Frequency
Self-oscillating frequency is determined mainly by the following items in Figure 3.





Integration capacitors, C1 and C2
Integration resistor, R1
Propagation delay in the gate driver
Feedback resistor, RFB
Duty cycle
The bus voltage and input resistance RIN have little influence on the self-oscillating frequency. Note that as is
the nature of a self-oscillating PWM, the switching frequency decreases as PWM modulation deviates from
idling.
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2.2.3
Determining Self-Oscillating Frequency
Choosing the switching frequency entails making many design trade offs.
At lower switching frequencies, the efficiency at the MOSFET stage improves, but inductor ripple current
increases. Also output PWM switching carrier leakage increases.
At higher switching frequencies the efficiency degrades due to switching losses, but wider bandwidth can be
achieved. The inductor ripple decreases yet iron losses increase. The junction temperature of the gate driver
IC might be a stopper for going to a higher frequency.
For these reasons, 400kHz is chosen for a typical design example, which can be seen in the IRAUDAMP10
reference design.
2.2.4
Choosing External Components Value
For suggested component values of components for a given target self-oscillating frequency, refer to Table 1.
The OTA output has limited voltage and current compliances. This set of component values ensures that the
OTA operates within its linear region so optimal THD+N performance can be achieved.
In case the target frequency is somewhere in between the frequencies listed in Table 1, adjust the frequency
by tweaking R1, if necessary.
Target SelfOscillation
Frequency
(kHz)
500
450
400
350
300
250
200
150
100
70
C1=C2
(nF)
2.2
2.2
2.2
2.2
2.2
2.2
4.7
10
10
22
R1
(ohms)
200
165
141
124
115
102
41.2
20.0
14.0
4.42
Condition: IRS2052M with IRF6665, DS=VAA, Vbus=+/-35V, DT=25ns, RFB=47k.
Table 1 External Component Values vs. Self Oscillation Frequency
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2.3
Clock Synchronization
In the PWM control loop design example, the self-oscillating frequency can be set and synchronized to an
external clock. This optional feature helps
 To maintain low audio noise floor when adjacent channels oscillating at frequencies close each other.
 To realize desired switching frequencies in order to prevent AM radio interferences.
Through a C-R network CCK and RCK, the internal clock oscillator injects periodic pulsating charges into the
integrator stage, forcing oscillation to lock up to the internal clock frequency. To maximize audio performance,
the self-running frequency without clock injection should be 5 to 10% higher than the internal clock frequency.
Figure 4 Clock Synchronization
2.3.1
Internal Clock Oscillator
The IRS2052M integrates two clock oscillators and synchronization networks for each PWM channel. To prevent
AM radio reception interference, two PWM frequencies are selectable via XSL pin. As shown in Table 2, when
XSL is bias to VAA, X1A and X1B are active. When XSL is GND, X2A and X2B are active. When XSL is VSS,
both clock oscillators are disabled. This mode is self-oscillating PWM and is also convenient to check self
oscillating frequency before clock synchronization is taken place. Unselected inverter(s) is cut off.
XSL pin
VAA
GND
VSS
X1A/B
Activated
Disabled
Disabled
X2A/B
Disabled
Activated
Disabled
Table 2 XSL pin and Clock Oscillation Mode
The inverters INV1 and INV2 are unbuffered (4069UB type) C-MOS single-stage inverters. The clock oscillator is
active whenever UVAA is not in under lockout. Recommended ceramic resonators are as follows.
CSBLA400KECE-B0 (400kHz, murata, DigiKey 490-1186-ND)
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CSBLA480KEC8-B0 (480kHz, murata, DigiKey 490-1188-ND)
Clock signal is internally distributed to PWM modulators in CH1 and CH2. In order to reduce rms values of
inductor ripple current in bus capacitor, internal clock is spaced each other by 180 degrees. The internal clock
synchronization feature can be disabled by pulling XSL pin down to VSS.
VAA
CL1A
VSS
X1A
X1
CL1B
RD1
CL2A
INV1
1M
X1B
INV2
X2A
X2
CL2B
RD2
1M
X2B
X1
VAA
X2
X1
SELF-OSC
XSL
SELF OSC
CLOCK
SELECT
X2
VSS
CKO
COMP1
IN1
COMP2
IN2
GND
Figure 5 Internal Clock Oscillator
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2.3.2
Internal Clock Lock Range
Figure 6 shows how a self-oscillating frequency locks up to an external clock frequency. A design of a 400kHz
self-oscillating frequency synchronizes to internal clock whose frequency is within the red border lines.
Figure 6 Typical Lock Range to External Clock
2.3.3
Daisy-chained Clock Configuration
When multiple IRS2052M is configured in a master and slave clock mode shown in Figure 7, multiple IRS2052M
can be daisy-chained with the first device being a master.
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VAA
VSS
VAA
VSS
VAA
CL1A
X1A
X1
CL1B
RD1
CL2A
X1A
INV1
1M
X1B
INV2
X2A
X2
CL2B
RD2
INV1
1M
X1B
INV2
X2A
1M
1M
X2B
X2B
VAA
X1
X2
X1
SELF-OSC
XSL
X1
X2
SELF OSC
XSL
CLOCK
SELECT
SELF OSC
CLOCK
SELECT
X2
VSS
CKO
CKO
COMP1
COMP1
IN1
TO
ADDITIONAL
IRS2052M
IN1
COMP2
COMP2
IN2
IN2
GND
GND
IRS2052M (MASTER)
IRS2052M (SLAVE1)
Figure 7 Daisy-chained Clock Configuration
2.4
Click Noise Elimination
The IRS2052M furnishes audible click noise reduction to minimize audible noise from loudspeakers upon start or
stop of PWM oscillation. To make this feature in effect, audio signal needs to be removed before start or stop
PWM. Also, make sure DC offset stays less than 50mV in the normal operating condition.
2.4.1
Turn-on Click Noise Reduction
The IRS2052M has a unique feature that minimizes audible click noise at PWM-start. When CSD is in between
Vth1 and Vth2 during start up, an internal closed loop around the OTA enables an oscillation that generates
voltages at COMP and IN-, bringing them to steady state values. It runs at around 1MHz, independent from the
switching oscillation.
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Figure 8 Turn-ON Click Noise Elimination
As a result, all capacitive components connected to COMP and IN- pins, such as C1, C2, C3 and Cc in Figure 8,
are pre-charged to their steady state values during the start up sequence. This allows instant settling of PWM
operation.
To utilize the click noise reduction function, the following conditions must be met.
1. CSD pin has slow enough ramp up from Vth1 to Vth2 such that the voltages in the capacitors can settle
to their target values.
2. High-side bootstrap power supply needs to be charged up prior to starting oscillation.
3. Audio input has to be zero.
4. For internal local loop to override external feedback during the startup period, DC offset at speaker
output prior to shutdown release has to satisfy the following condition.
DCoffset  30A  RFB
2.4.2
Turn-off Click Noise Reduction (Soft-shutdown)
To further reduce audible click noise when PWM stops, the IRS2052M has a unique feature that minimizes
PWM-stop audible click noise. The internal shutdown timing control block assures a specific timing to stop PWM.
When CSD pin is pulled-down to shutdown the PWM, the internal soft-shutdown block waits until a moment
where audible noise is minimal prior to shutdown. The Turn-off noise reduction function installs maximum of tSSD
delay from when the CSD pin threshold falls under the shutdown threshold Vth1.
2.5
CSD Voltage and OTA Operational Mode
The CSD pin determines the operational mode of the IRS2052M as shown in Figure 9. The OTA has three
operational modes; cut off, local oscillation and normal operation while the gate driver section has two modes;
normal and shutdown with CSD voltage.
When VCSD < Vth2, the IC is in shutdown mode and the OTA is cut off. When Vth2< VCSD < Vth1, the HO and LO
outputs are still in shutdown mode. The OTA is activated and starts local oscillation, which pre-biases all the
capacitive components in the error amplifier. When VCSD>Vth1, shutdown is released and PWM operation starts.
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~
~
~
~
~
~
Figure 9 VCSD and OTA Mode
2.6
Self-oscillation Start-up Condition
The IRS2052M requires the following conditions be met to start PWM oscillation in the typical application
circuit.
-
All the control power supplies, VAA, VSS, VCC and VBS are above the under voltage lockout
thresholds.
CSD pin voltage is over Vth1 threshold.
iIN  iFB
Where i IN 
VIN
V
, i FB   B .
RIN
RFB
Note that this condition also limits the maximum audio input voltage feeding into R1. If this condition is
exceeded, the amplifier stops its oscillation during the operation period. This allows a 100% modulation
index; however, care should be taken so that the high-side floating supply does not decay due to a lack of
low-side pulse ON state.
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3
MOSFET Selection
There are a couple of limitations on the size of the MOSFET to be used with the IRS2052M.
1. Power dissipation
Power dissipation from the gate driver stage in the IRS2052M is proportional to switching frequency and the
gate charge of the MOSFET. The higher the switching frequency, the lower the gate charge of the MOSFET
that can be used.
Refer to Junction Temperature Estimation later in this application note for details.
2. Switching Speed
Internal over current protection has a certain time window to measure the output current. If switching
transition takes too long, the internal OCP circuitry starts monitoring voltage across the MOSFET which
induces false triggering of OCP. Less than 20nC of gate charge per output is recommended.
The IRS2052M accommodates a range of IR Digital Audio MOSFETs, providing a scalable design for various
output power levels. For further information on MOSFET section, refer to AN-1070, Class D Amplifier
Performance Relationship to MOSFET Parameters.
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4
Over Current Protection (OCP)
The IRS2052M features over current protection to protect the power MOSFETs during abnormal load conditions.
The control logic is shown in Figure 11. The IRS2052M starts a sequence of events when it detects an over
current condition during either high-side or low-side turn on of a pulse.
As soon as either the high-side or low-side current sensing block detects over current:
1. The OC Latch (OCL) flips logic states and shutdowns the outputs LO and HO.
2. The CSD pin starts discharging the external capacitor Ct.
3. When VCSD, the voltage across Ct, falls below the lower threshold Vth2, an output signal from COMP2
resets OCL.
4. The CSD pin starts charging the external capacitor Ct.
5. When VCSD goes above the upper threshold Vth1, the logic on COMP1 flips and the IC resumes
operation.
As long as the over current condition exists, the IC will repeat the over current protection sequence at a repetition
rate dependent upon capacitance at the CSD pin.
Figure 10 Over Current Protection Timing Chart
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VAA
FLOATING
HIGH SIDE 1
Vth1
COMP1
`
PROT
CSD
S
`
COMP2
Ct
R
Vth2
VSS
On-chip
OTP
FAULT
Q
WARN
FLOATING
HIGH SIDE 2
UVLO(VB)
UVLO(VB)
OC DET
(H1)
OC DET
(H2)
HV
LEVEL
SHIFT
HV
LEVEL
SHIFT
SD
HV
LEVEL
SHIFT
HV
LEVEL
SHIFT
FLOATING INPUT
GND
OC DET
(L1)
SD
OTW
UVLO(VCC)
PWM1
DEAD TIME
HO1
LO1
HV
LEVEL
SHIFT
WARN
OTP
OC DET
(L2)
SD
SD
PWM2
DEAD TIME
HO2
LO2
LOW SIDE
Figure 11 Production Control Functional Block Diagram
4.1
Protection Control
The internal protection control block dictates the operational mode, normal or shutdown, using the input of the
CSD pin. In shutdown mode, the IC forces LO and HO to output 0V with respect to COM and VS respectively to
turn off the power MOSFETs.
The CSD pin provides five functions.
1. Power up delay timer
2. Self-reset timer
3. Shutdown input
4. Latched protection configuration
5. Shutdown status output (host I/F)
The CSD pin cannot be paralleled with another IRS2052M.
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4.1.1
Self Reset Protection
By putting a capacitor between CSD and VSS, the IRS2052M resets itself after entering shutdown mode.
After the OCP event, the CSD pin discharges Ct voltage VCSD down to the lower threshold Vth2 to reset the
internal shutdown latch. Then, the IRS2052M begins to charge Ct in an attempt to resume operation. Once the
voltage of the CSD pin rises above the upper threshold, Vth1, the IC resumes normal operation.
Figure 12 Self Reset Protection Configuration
4.1.2
Designing Ct
The timing capacitor, Ct, is used to program tRESET and tSU.
 tRESET is the amount of time that elapses from when the IC enters the shutdown mode to the time when
the IC resumes operation. tRESET should be long enough to avoid over heating the MOSFETs from the
repetitive sequence of shutting down and resuming operation during over current conditions. In most of
applications, the minimum recommended time for tRESET is 0.1 second.
 tSU is the amount of time between powering up the IC in shutdown mode to the moment the IC releases
shutdown to begin normal operation.
The Ct determines tRESET and tSU as following equations:
t RESET 
t SU 
Ct  V AA
1.1  I CSD
Ct  V AA
0.7  I CSD
[s]
[s]
where ICSD = the charge/discharge current at the CSD pin
VAA = the floating input supply voltage with respect to VSS.
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4.1.3
Shutdown Input
The IRS2052M can be shut down by an external shutdown signal SD. Figure 13 shows how to add an external
discharging path to shutdown the PWM.
Figure 13 Shutdown Input
4.1.4
Latched Protection
Connecting CSD to VAA through a 10k Ω or less resistance configures the over current protection latch. The latch
locks the IC in shutdown mode after over current is detected. An external reset switch can be used to bring CSD
below the lower threshold Vth2 for a minimum of 200ns to properly reset the latch. After the power up sequence,
a reset signal to the CSD pin is required to release the IC from the latched shutdown mode.
VAA
Vth1
<10k
COMP1
`
CSD
`
COMP2
SHUTDOWN
Vth2
VSS
Figure 14 Latched Protection with Reset Input
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4.1.5
Interfacing with System Controller
The IRS2052M can communicate with an external system controller through a simple interfacing circuit shown in
Figure 15. A generic PNP transistor U1 detects the sink current at the CSD pin during an OCP event and outputs
a shutdown signal to an external system controller. Another generic NPN transistor U2 can then reset the internal
protection logic by pulling the CSD voltage below the lower threshold Vth2 for a minimum of 200ns. Note that the
CSD pin is configured to operate in latched OCP. After the power up sequence, a reset signal to the CSD pin is
required to release the IC from the shutdown mode.
Figure 15 Interfacing with Host Controller
4.2
Programming OCP Trip Level
In a Class D audio amplifier, the direction of the load current alternates with the audio input signal. An overcurrent condition can therefore occur during either a positive current cycle or a negative current cycle. The
IRS2052M uses the RDS(on) of the output MOSFETs as current sensing resistors. Due to the structural constraints
of high voltage ICs, current sensing is implemented differently for the high side and low side. If the measured
current exceeds a predetermined threshold, the OCP block outputs a signal to the protection block, forcing HO
and LO low and protecting the MOSFETs.
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Figure 16 Bi-directional Over Current Protection
4.2.1
Low Side Over Current Sensing
For negative load currents, low-side over current sensing monitors the load condition and shuts down switching
operation if the load current exceeds the preset trip level.
Low-side current sensing is based on the measurement of VDS across the low side MOSFET during the low-side
on state. In order to avoid triggering OCP from overshoot, a blanking interval inserted after LO turn on disables
over current detection for 450ns.
The OCSET pin is to program the threshold for low-side over current sensing. When the measured VDS measured
of the low side MOSFET exceeds the voltage at the OCSET pin with respect to COM, the IRS2052M begins the
OCP sequence described earlier.
Note that the programmable OCSET range is 0.5V to 5.0V. To disable the low side OCP, connect OCSET to
VCC directly.
To program the trip level for over current, the voltage at OCSET can be calculated using the equation below.
VOCSET = VDS(LOW SIDE) = ITRIP+ x RDS(on)
In order to minimize the effect of the input bias current at the OCSET pin, select resistor values for R4 and R5
such that the current through the voltage divider is 0.5mA or more.
* Note: Using VREF to generate an input to OCSET through a resistive divider provides improved immunity from
fluctuations in VCC.
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Figure 17 Low Side Over Current Sensing
4.2.2
Low Side Over Current Setting
Assume that the low side MOSFET has RDS(on) of 100mΩ. VOCSET to set the current trip level at 30A is given by:
VOCSET = ITRIP+ x RDS(on) = 30A x 100m = 3.0V
Choose R4+R5=10 k to properly load the VREF pin.
R5 
VOCSET
10k
VREF
3.0V
10k
5.1V
 5.8k

where VREF = 5.1V
Based on the E-12 series resistor values, choose R5 = 5.6k and R4 = 3.9k to complete the design.
In general, RDS(on) has a positive temperature coefficient that needs to be considered when setting the threshold
level. Also, variations in RDS(on) will affect the selection of external or internal component values.
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4.2.3
High Side Over-Current Sensing
For positive load currents, high-side over current sensing also monitors the load condition and shuts down
switching operation if the load current exceeds the preset trip level. High-side current sensing is based on the
measurement of VDS across the high-side MOSFET during high-side turn on through pins CSH and Vs. In order
to avoid triggering OCP from overshoot, a blanking interval inserted after HO turn on disables over current
detection for 450ns.
In contrast to low-side current sensing, the threshold at which the CSH pin engages OC protection is internally
fixed at 1.2V. An external resistive divider R2 and R3 can be used to program a higher threshold.
An external reverse blocking diode, D1, is required to block high voltages from feeding into the CSH pin while the
high side is off. Due to a forward voltage drop of 0.6V across D1, the minimum threshold required for high-side
over current protection is 0.6V.
VCSH 
R3
 VDS ( HIGHSIDE)  V F ( D1) 
R 2  R3
where VDS(HIGH SIDE) = the drain to source voltage of the high side MOSFET during high side turn on
VF(D1) = the forward drop voltage of D1
Since VDS(HIGH SIDE) is determined by the product of drain current ID and RDS(on) of the high side MOSFET. VCSH
can be rewritten as:
VCSH 
R3
 RDS ( ON )  I D  VF ( D1) 
R 2  R3
The reverse blocking diode D1 is forward biased by a 10k resistor R1.
Figure 18 Programming High Side Over Current Threshold
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4.2.4
High Side Over Current Setting
Figure 18 demonstrates the typical circuitry used for high side current sensing. In the following example, the over
current protection level is set to trip at 30A using a MOSFET with an RDS(on) of 100m. The component values of
R2 and R3 can be calculated using the following formula:
Let R2 + R3=10 k.
R3  10k 
VthOCH
V DS  V F
where VthOCL = 1.2V
VF = the forward voltage of reverse blocking diode D1 = 0.6V.
[email protected]=30A = the voltage drop across the high side MOSFET when the MOSFET current is 30A.
Therefore, [email protected]=30A = ID x RDS(on) = 30A x 100m = 3V
Based on the formulas above, R2 = 6.8k and R3 = 3.3k.
4.2.5
Choosing the Right Reverse Blocking Diode
The selection of the appropriate reverse blocking diode D1 depends on its voltage rating and speed. To
effectively block bus voltages, the reverse voltage must be higher than the voltage difference between +B and –B
and the reverse recovery time must be as fast as the bootstrap charging diode. A diode such as the NXP
BAV21W, a 200V, 50ns high speed switching diode, is more than sufficient.
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5
Over Temperature Protection
The IRS2052M equips two over temperature protection features; OTP input to sense MOSFET temperature and
on-chip OTP to protect the IC itself.
5.1
Over Temperature Protection Input (OTP)
The over temperature protection input OTP is for an external PTC Thermistor to monitor temperature of MOSFET.
The OTP pin equips a 0.6mA internal current source to bias the external PTC resistor. Over temperature warning
activates when the voltage at any of OTP input pin goes higher than 1.4V. Over temperature protection activates
when the voltage at any of OTP input pin goes higher than 2.8V. Each threshold has 200mV.
The OTP pin of IRS2052M is designed for connecting a PTC Thermistor with characteristics shown in Figure 20.
Recommended PTC Thermistor includes PRF15**471QB1RC, PRF18**471QB1RB or PRF21**471QB1RA
series from Murata Manufacturing co., ltd.
A thermostat IC with open drain output, such as LM26 from National Semiconductor, can also be used as a
temperature sensor for better accuracy as shown in Figure 22.
Figure 19 Over Temperature Protection (OTP) Input Structure
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Figure 20 Recommended PTC sensor characteristics
OTP Status
200mV
SHUTDOWN
200mV
WARNING (OTW)
VETW
1.4V
VETSD
VETO
2.8V
5.1V
VOTP
Figure 21 VOTP vs. Over Temperature Protection Status
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VCC
VETW
OTW
IET =
0.6mA
THERMOSTAT IC
OTP
VETSD
ACTIVE HIGH
BDE1101G (ROHM)
LM26 (National)
OTP
VETZ =
5.1V
COM
-VBUS
Figure 22 OTP pin with Thermostat IC
5.2
On-chip Over Temperature Protection
If the junction temperature TJ of IRS2052M becomes higher than on-chip thermal warning threshold TW, the onchip over temperature protection pulls OTW pin down to GND. If the junction temperature TJ keeps increasing
and exceed on-chip thermal shutdown threshold TSD, the on-chip over temperature protection shuts down PWM
as long as the junction temperature is higher than the threshold.
Figure 23 On-chip OTP
5.3
Over Temperature Warning Output (OTW)
OTW output is an open drain output referenced to GND to report whether the IRS2052M is experiencing high
temperature from either OTP input or on-chip OTP. OTW activates if OTP pin voltage becomes higher than
warning threshold VETW, or if junction temperature reaches warning threshold TW.
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6
FAULT Output
FAULT output is an open drain output referenced to GND to report whether the IRS2052M is in shutdown mode
or in normal operating condition. If FAULT pin is open, the IRS2052M is in normal operation mode, i.e. HO and
LO are active. Following conditions triggers shutdown internally and pulls FAULT pin down to GND.
 Over Current Protection
 Over Temperature Protection (internal or external via OTP pin)
 Shutdown mode from CSD pin voltage
7
CLIP Output
When the output of the amplifier looses track to an expected target value, the amplifier enters clipping condition.
CLIP output is to flag the clipping condition. The integrated clipping detection monitors voltage in COMP pin with
a window comparator and pull an open drain MOSFET referenced to GND. Detection threshold at COMP pin is
set at 10% and 90% of VAA-VSS. Each channel has independent CLIP outputs. Each CLIP output has 1us
minimum pulse width once triggered.
The CLIP outputs are disabled when the IRS2052M is in shutdown mode.
VAA
IN-1
OTA
GND
COMP1
VSS
VAA
R
CLIP1
PGEN
8R
R
VSS
Figure 24 Clipping Detection
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8
Deadtime Design
Dead time is the blanking period inserted between either high-side Turn-OFF and low-side Turn-ON, or low-side
Turn-OFF and high-side Turn-ON. Its purpose is to prevent shoot through, or a rush of current through both
MOSFETs. In the IRS2052M, an internal dead time generation block allows the user to select the optimum dead
time from a range of preset values. Selecting a preset dead time through the DT pin voltage can easily be done
through an external voltage divider. This way of setting dead time prevents outside noise from modulating the
switching timing, which is critical to the audio performance.
8.1
How to Determine Optimal Deadtime
The effective deadtime in an actual application differs from the deadtime specified in this datasheet due to the
switching fall time, tf. The deadtime value in this datasheet is defined as the time period between the beginning of
turn-off on one side of the switching stage and the beginning of turn-on on the other side as shown in Figure 25.
The fall time of the MOSFET gate voltage must be subtracted from the deadtime value in the datasheet to
determine the effective deadtime of a Class D audio amplifier.
(Effective deadtime) = (Deadtime in datasheet) – tf
90%
HO (or LO)
Effective dead - time
10%
tf
LO (or HO)
Dead-time
in
datasheet
10%
Figure 25 Effective Dead Time
A longer deadtime period is required for a MOSFET with a larger gate charge value because of the longer tf.
Although a shorter effective, deadtime setting is beneficial to achieving better linearity in Class D amplifiers, the
likelihood of shoot-through current increases with narrower deadtime settings. Negative values of effective
deadtime may cause excessive heat dissipation in the MOSFETs, leading to potentially serious damage.
To calculate the optimal deadtime in a given application, the fall time tf for both HO and LO in the actual circuit
need to be taken into account. In addition, variations in temperature and device parameters could also affect the
effective deadtime in the actual circuit. Therefore, a minimum effective deadtime of 10ns is recommended to
avoid shoot-through current over the range of operating temperatures and supply voltages.
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8.2
Programming Deadtime
The IRS2052M selects the deadtime from a range of preset deadtime values based on the voltage applied at the
DT pin. An internal comparator translates the DT input to a predetermined deadtime by comparing the input with
internal reference voltages. These internal reference voltages are set in the IC through a resistive voltage divider
using VCC. The relationship between the operation mode and the voltage at DT pin is illustrated in the Figure 26
below.
Dead- time
45nS
65nS
85nS
105nS
0.23xVcc
0.36xVcc
0.57 xVcc
Vcc
VDT
Figure 26 Deadtime vs. VDT
Table 3 suggests pairs of resistor values used in the voltage divider for selecting deadtime. Resistors with up to
5% tolerance are acceptable when using these values.
Figure 27 External Voltage Divider for DT Pin
Deadtime Mode
DT1
DT2
DT3
DT4
R1
<10k
5.6k
8.2k
Open
R2
Open
4.7k
3.3k
<10k
DT Voltage
Vcc
0.46 x Vcc
0.29 x Vcc
COM
Table 3 Recommended Resistor Values for Dead Time Selection
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9
9.1
Power Supply Considerations
Supplying VAA and VSS
For best audio performance, it is preferred to produce VAA and VSS with external regulators, such as the three
terminal regulators. Standard 7805 and 7905 regulators are suitable.
Figure 28 Supplying VAA and VSS with External Regulators
When switched mode regulators provide VAA and VSS, it is required to place a two-stage noise filter in the supply
lines as shown in Figure 29 to prevent noise from influencing the switching ripple voltage on +/-5V.
Figure 29 Supplying VAA and VSS from Switched Mode Power Supply
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9.2
Recommended Power Supply Configuration for Gate Driver Stage
Figure 30 shows the recommended power supply configuration for gate driver power supplies. Gate driver stage
has four power supply inputs.
1.
2.
3.
4.
VB1-VS1: CH1 high side gate drive supply
VB2-VS2: CH2 high side gate drive supply
VCC-COM: low side logic supply
VCC2-COM2: CH1-2 low side gate drive supply
RVBS1 - RVBS2 prevent CVBS1 – CVBS2 from over-charging due to under shoots in VS1 – VS2. RVBS1 - RVBS2 reduce
switching noise triggered by Qrr of bootstrap diode DBS1 – DBS2 .
All power supplies except VCC-COM generate switching noise. RVCC2 isolates the switching noise from low side
gate drive current and bootstrap charge pump current feeding into VCC. These optional filtering resistors are
effective to achieve best audio performance in higher power applications (>100W).
Figure 30 Recommended Power Supply Configurations for Gate Driver Stage
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9.2.1
VCC and VCC2
The Non-floating section of IRS2052M has two supply voltages, VCC and VCC2. The VCC is paired with COM to
supply logic and small signal circuitries. The VCC2 and COM2 feed power to LO1-3 low side gate drive stages.
It is recommended to supply both VCC and VCC2 from a single supply source. VCC must be equal or higher
than VCC2, but no more than 5V.
9.2.2
COM and COM2
COM and COM2 must be tied to each other in as short a distance as possible.
9.2.3
Bottom Pad Connection
The Exposed bottom pad in the MLPQ48 package where the IC die sits has the same voltage potential as COM
and COM2. However, it is not directly connected inside. The pad may be tied to COM and COM2 with short
distance trace(s), or may be floated. Do not use the bottom pad as the low side power supply return path.
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9.3
Designing High-side Bootstrap Power Supply
The high-side driver requires a floating supply VBn referring to respective switching node VSn where the source
of the MOSFET is connected. A charge pump method (floating bootstrap power supply) eliminates the need of a
floating power supply and thus is used in the typical application circuit.
9.3.1
Floating Bootstrap Power Supply
The floating bootstrap power supply charges bootstrap capacitor CBS from the low-side power supply VCC during
the low-side MOSFET ON period. When the high-side MOSFET is ON, the charging diode turns off to float the
VBS supply. CBS retains its voltage as a floating power supply referenced to VS. Before CBS discharges and VBS
crosses the under voltage lock out threshold UVBS, the next charging cycle should start by turning on the lowside MOSFET.
Figure 31 depicts the low-side MOSFET ON state. I1 turns off the high-side MOSFET first, then I2 turns on the
low side the MOSFET. As soon as switching node VS reaches negative supply –B, the bootstrap diode DBS turns
on and starts charging CBS with current I3 from VCC. Note that VBS = VCC – (forward drop voltage of DBS).
VBn
L
OFF
HOn
H
ON
+B
+
-
CBS
I3
DBS
OFF
I1
-B
VSn
LEVEL
SHIFT
VCC2
PWM
H
L
Vcc
I2
ON
LOn
ON
12V
L
OFF
-B
COM, COM2
IRS2052M
Figure 31 Charging VBS: Low-side ON Period
After the low-side conduction period, I4 in Figure 32 turns off the low-side MOSFET. Then I5 turns on the highside MOSFET, lifting VS up to +B. As long as the high side is ON, the bootstrap diode DBS isolates the floating
power supply VBS.
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VBn
H
ON
HOn
+B
+
-
CBS
DBS
ON
L
OFF
I5
VSn
LEVEL
SHIFT
VCC2
PWM
L
H
Vcc
OFF
LOn
H
OFF
12V
ON
I4
COM, COM2
-B
IRS2052M
Figure 32 High-side ON Period
9.3.2
Choosing Bootstrap Capacitance
Since a MOSFET is a voltage driven device, I5 is only to fill up the gate charge of the high-side MOSFET during
the rising edge that is a one time event for entire high-side MOSFET on-time. After that, no more current flows
from CBS. In spite of that, the high-side gate driver stage in the IRS2052M has quiescent current consumption
IQBS to drain the charge of CBS during the high-side MOSFET ON-time. High-side sensing bias current IR1 via
detecting diode D1 is another current to take into considerations. (Figure 34) Normally, leakage current in the
gate of a MOSFET is negligibly small compared to the IQBS and IR1.
The minimum bootstrap capacitance is determined as follows.
C BS 
( I QBS  I R1 )  t ON
VCC  1.5  UVBS
Where CBS: floating bootstrap capacitance [F]
IQBS: high-side quiescent current [A]
IR1: high-side current sensing bias current [A]
tON: longest high-side MOSFET conduction time [s]
VCC: low-side power supply voltage [V]
UVBS: high-side under voltage lockout threshold [V]
1.5: voltage drop in the bootstrap charging diode DBS
The bootstrap capacitor sees the VCC supply voltage. A ceramic capacitor (X7R, X5R or X5S type) or aluminium
electrolytic capacitor with 25V or higher voltage rating is recommended.
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VCC - VF
UVBS
VBS
0
HO
Figure 33 VBS Discharging
Figure 34 CBS Discharging During High-side ON Period
9.3.3
Choosing Bootstrap Diode
The bootstrap diode blocks bus voltage (+B)-(-B) + (voltage overshoot), therefore a diode with voltage rating of
1.5 x bus voltage is a minimum requirement. In order to charge the bootstrap capacitor in a very short low-side
ON period in a high PWM modulation ratio, a fast recovery type is necessary. One with a short reverse recovery
time of trr<50ns is recommended.
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9.3.4
Damping Resistor
Inserting a damping resistor in series with bootstrap diode DBS is an effective way to eliminate the following
potential problems in bootstrap power supply design.


EMI noise due to reverse recovery charge of the bootstrap diode; note that this diode is a switching
device for the charge pump
Overcharge to bootstrap supply capacitor CBS
Figure 35 explains how the floating supply voltage VBS is over charged by a negative spike on VS voltage that is
induced by stray inductances in –B feeding line. Generally, a 1 to 5 ohms resistor helps to prevent these issues.
Figure 35 VBS Charging With and Without RBS
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9.3.5
Charging VBS Prior to Start
For proper start-up, it is necessary for the high side bootstrap capacitor be charged prior to PWM start-up
through a resistor RCHARGE from the positive supply bus to the VB pin. By utilizing an internal 15.3V Zener diode
between VB and VS, this scheme eliminates the need to charge the boot strap capacitor through low side turn on
during start up.
The value of this charging resistor is subject to several constraints:
- The minimum resistance of RCHARGE is limited by the maximum PWM modulation index of the system.
When HO is high, RCHARGE drains the bootstrap power supply so it reduces holding up time, hence
maximum continuous HO on time.
- The maximum resistance of RCHARGE is limited by the current charge capability of the resistor during
startup:
I CHARGE  I QBS
where ICHARGE = the current through RCHARGE
IQBS = the high side supply quiescent current.
ICHARGE generates a DC offset at the speaker output prior to PWM start up. Check that the DC offset does not
exceed a condition for click noise elimination. See Click Noise Elimination section for more detail.
Figure 36 Boot Strap Supply Pre-charging
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9.4
Start-up/Power-down Sequence (UVLO)
The protection control block in the IRS2052M monitors the status of VAA and VCC to ensure that both voltage
supplies are above their respective UVLO (under- voltage lockout) thresholds before beginning normal operation.
If either VAA or VCC is below the under voltage threshold, LO and HO are disabled in shutdown mode until both
VAA and VCC rise above their voltage thresholds.
As soon as VAA or VCC falls below its UVLO threshold, protection logic in the IRS2052M turns off LO and HO,
shutting off the power MOSFETs.
Figure 37 IRS2052M UVLO Timing Chart
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9.5
Power Supply Decoupling
Because the IRS2052M contains analog circuitry, careful attention must be given to decoupling the power
supplies for proper operation of the IC. Ceramic capacitors minimum of 0.1µF or aluminium capacitors minimum
of 1uF should be placed close to the power supply pins of the IC on the board. Due to large capacitance
variations, Y5V dielectric or similar type ceramic capacitors are not recommended.
Please refer to the application note AN-978 for general design considerations of a high voltage gate driver IC.
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10 Junction Temperature Estimation
The power dissipation in the IRS2052M is dominated by the following items:
- PMID: Power dissipation of the input floating logic and protection circuitry
- PLSM: Power dissipation of the Input Level Shifter
- PLOW: Power dissipation in low side
- PLSH: Power dissipation of the High-side Level Shifter
- PHIGH: Power dissipation in high side
The following equations are for reference only. Because of the non-linear characteristics in gate drive stage,
these assumptions may not be accurate.
10.1 PMID: Power Dissipation of the Input Floating Logic and Protection Circuitry
The power dissipation of the input floating section is given by:
PMID  V AA  V SS   I QAA1
Where
IQAA1 = floating input section quiescent supply current in normal operation mode
10.2 PLSM: Power Dissipation of the Input Level Shifter
PLSM = 1.5 x 10-9 x fSW x VSS BIAS x 2
Where
fSW = the PWM switching frequency
VSS BIAS = the bias voltage of VSS with respect to COM
10.3 PLOW: Power Dissipation of Low Side
The power dissipation of the low side comes from the losses of the logic circuitry and the losses of driving LO.
PLOW  PLDD  2  PLO

RO
 I QCC  VCC   2  Vcc  Q g  f SW 

RO  R g  R g (int)





Where
PLDD = power dissipation of the internal logic circuitry
PLO = power dissipation from of gate drive stage for LO
RO = output impedance of LO, typically 20 Ω for the IRS2052M
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Rg(int) = internal gate resistance of the low side MOSFET, typically 2Ω
Rg = external gate resistance of the low side MOSFET
Qg = total gate charge of the low side MOSFET
10.4 PLSH: Power Dissipation of the High-side Level Shifter
PLSH = 0.4nC x fsw x VBUS x 2
Where
fSW = PWM switching frequency
VBUS = difference between the positive bus voltage and negative bus voltage
10.5 PHIGH: Power Dissipation of High Side
The power dissipation of the high side comes from the losses of the logic circuitry and the losses of driving
HO.
PHIGH  2  ( PLDD  PHO )


RO

 2  I QBS  VBS   2  VBS  Qg  f SW 




R
R
R
O
g
g
(int)


Where
PLDD = power dissipation of the internal logic circuitry
PHO = power dissipation of the gate drive stage for HO
RO = equivalent output impedance of HO, typically 20 Ω for the IRS2052M
Rg(int) = the internal gate resistance of the high side MOSFET, typically 2Ω
Rg = external gate resistance of the high side MOSFET
Qg = total gate charge of the high side MOSFET
10.6 PD: Total Power Dissipation
Total power dissipation, PD, is given by
PD  PMID  PLSM  PLOW  PHSM  PHIGH .
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10.7 TJ: Junction Temperature
Given junction to ambient thermal resistance RthJA, the junction temperature TJ can be calculated from the
formula provided below and must not exceed 150°C.
T J  [ Rth JA  Pd  T A ]  150 C
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11 Board Layout Considerations
The floating input section of the IRS2052M consists of a low noise OTA error amplifier and a PWM comparator
along with CMOS logic circuitry. The high frequency bypass capacitor CVAA-VSS should be placed closest to the
IRS2052M to supply the logic circuitry. CVAA and CVSS are for stable operation of the OTA and should be placed
close to the IC.
Gate driver supply capacitors CVCC, CVCC2, CVBS1 and CVBS2 provide gate-charging current and should also be
placed close to the IRS2052M.
CVSS
CVAA
CVBS2
CVCC
IRS2052M
CVCC2
CVBS1
Figure 38 Placement Sensitive Bypass Capacitors
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11.1 Ground Plane
In addition to the key component locations mentioned above, it is important to properly pour ground planes to
obtain good audio performance. Since each functional block within the IRS2052M refers to different potentials, it
is recommended to apply three reference potentials.
11.1.1
Analog Ground
The Input analog section around the OTA is referenced to the signal ground, or GND, which should be a quiet
reference node for the audio input signal. The peripheral circuits in the floating input section such as CSD and
COM pins refer to this ground. These nodes should all be separate from the switching stages of the system. In
order to prevent potential capacitive coupling to the switching nodes, use a ground plane only in this part of the
circuit. Do not share the ground plane with gate driver or power stages.
11.1.2
Gate Driver Reference
The gate driver stage of the IRS2052M is located between pins 7 and 30 and is referenced to the negative bus
voltage, COM and COM2. This is the substrate of the IC and acts as ground. Although the negative bus is a
noisy node in the system, both of the gate drivers refer to this node. Therefore, it is important to shield the gate
drive stages with the negative bus voltage so that all the noise currents due to stray capacitances flow back to
the power supply without degrading signal ground.
11.1.3
Power Ground
Power ground is the ground connection that closes the loops of the bus capacitors and inductor ripple current
circuits. Separate the power ground and input signal grounds from each other as much as possible to avoid
common stray impedances.
Figure 39 illustrates how to paint out reference planes. The power GND plane should include a negative bus cap.
Power reference plane should include Vcc. Also, use distinctly different symbols for the different grounds.
For further board layout information, refer to AN-1135, PCB Layout with IR Class D Audio Gate Drivers
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Figure 39 Applying Ground Planes
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