MOBILE MULTIMEDIA INTERFACE (M2I) Final VERY LOW POWER 1.8V Datasheet 16K X 16 IDT70P9268L SYNCHRONOUS DUAL-PORT STATIC RAM Features ◆ ◆ ◆ True Dual-Ported Memory Cells – Allows simultaneous access of the same memory location ◆ High per-port throughput performance – Industrial: 800 Mbps ◆ Low-Power Operation – Active: 15 mA (typ.) – Standby: 2 uA (typ.) ◆ Multiplexed address and data I/Os ◆ ◆ ◆ ◆ ◆ Counter enable and repeat features Full synchronous operation on both ports Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL-compatible, single 1.8V (+/- 100mV) power supply Industrial temperature range (-40C to +85C) Available in a 100-ball fpBGA (fine pitch BGA) Green parts available, see ordering information Block Diagram A0L – A13L DATA0L – DATA15L DATA0R – DATA15R I/O0R – I/O15R I/O0L – I/O15L UBL LBL CNTEN L CNTRPT L ADSR 16K x 16 ADSL Address/Data UBR Address/Data MEMORY I/O Control I/O Control Addr0L – Addr 13L CLKL ARRAY Addr0R – Addr 13R LBR CNTEN R CNTRPT R CLKR SPECIAL FUNCTION SFEN LOGIC CEL OEL R/WL INTL CLKL CONTROL LOGIC SF0 – SF 7 CER OER R/WR INTR CLKR ZZ CONTROL ZZL ZZR LOGIC NOTES: 1. This block diagram depicts operation with the address and data signals mux’d on the right port but not on the left port. If each port is set to operate with the address and data signals mux’d, then both sides of the block diagram will be the same as the right port pictured above. 1 of 23 ©2007 Integrated Device Technology, Inc. August 22, 2007 DSC 5695/1 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Device Description Final Datasheet Industrial Temperature Range Designed primarily for use as a high-speed, low-power inter-connect in multi-processor wireless handsets, the IDT70P9268 or Mobile Multimedia Interconnect (M2I) provides many advantages over embedded serial interfaces, asynchronous memories, and other legacy solutions to interprocessor communication. Performance The M2I supports unparalleled data throughput rates of up to 900 Mbps per port. This is achieved through the implementation of a synchronous architecture which allows the device to support much shorter cycle times (20 ns compared to 55 ns for most low-power asynchronous memories). Additionally, the adoption of a synchronous architecture allows the M2I to support on-chip counter functionality which helps to eliminate the inefficiencies associated with asynchronous implementations of the address-data-multiplex (ADM) interface. Asynchronous ADM (address-data multiplex) interfaces require the assertion of an external address on one cycle followed by the associated data on the subsequent cycle. This results in an access scheme that imparts a 50% inefficiency into a system already limited by slow cycle times. The M2I’s counter functionality allows a single external address to be asserted on one cycle followed by data being burst into or out of the device on every subsequent cycle. This, when combined with the dramatically improved cycle time, translates to roughly six times greater throughput per-port when compared with asynchronous ADM devices. Power Consumption In portable applications, power consumption is of vital concern. This is why the M2I includes several features targeted at reducing the power consumption of the device itself and the system as a whole. First, the M2I was designed to consume 40% less operating current than low-power asynchronous memories (15 mA compared to 25 mA). When combined with it’s superior performance and counter functionality, which allow it to complete media transfers in fewer cycles, this enables the M2I to consume nearly 90% less energy than asynchronous memories during transfers of a given file size. Second, the M2I features port-specific chip-enable and sleep mode pins which allow the two ports of the M2I to be powered down into standby mode independently of one another. When combined with the M2I’s interrupt flag functionality, this allows the processor subsystems to communicate with one another and to shut off whole portions of the handset which are not in use, dramatically reducing the power consumption of the system. Flexibility To help meet the ever changing requirements of wireless handsets, the M2I has been designed to provide a great deal of flexibility. The M2I has the ability to support both ADM and traditional SRAM interfaces, allowing it to seamlessly interface with both current and legacy processors. Additionally, the M2I helps to free up GPIO pins on the processors, allowing designers to include differentiating functionality that helps set their product apart from the competition. By supporting the ADM interface, the M2I consumes nearly 50% fewer pins per-port than non-multiplexed solutions. The M2I also frees up additional GPIO pins on the processors by including 8 dynamically programmable GPIO extender pins. These pins allow the processors to offload the need to monitor or control simple, binary state devices (e.g. switches, LED drivers, etc.) to the M2I and allow the processors to use their GPIO pins for more value added functions. 2 of 23 August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range Pin Configuration IDT70P9268 BY100 100-BALL fpBGA A1 A2 VSS B1 A3 B2 R/WR C1 D1 B3 D2 F2 G1 ADSL H1 R/WL J1 G2 K1 A4L(3) H3 K2 A6L(3) F5 G4 J3 G5 H4 H5 VSS J4 I/O1L K3 J5 I/O6L K4 I/O2L I/O3L H7 I/O11L J6 I/O7L K5 J7 K6 I/O5L I/O10L K8 A10L(3) K9 VSS SF3 H10 A12L(3) J9 I/O15L SF1 G10 OEL H9 A9L(3) J8 VDD K7 VDD G9 H8 VDD F10 VSS ZZL I/O13L I/O9L F9 G8 A7L(3) SF4 E10 VSS VSS VSS D10 SF5 E9 F8 SF2 G7 H6 I/O4L D9 VDD OER C10 SF7 SF6 E8 F7 I/O12L C9 D8 SFEN B10 I/O14R ZZR MSEL(2) A13L(3) G6 I/O8L C8 I/O13R A10 I/O15R B9 VSS I/O12R E7 SF0 F6 VSS VDD I/O0L A5L(3) E6 CNTRPTL CLKL A3L(3) A2L(3) J2 A1L(3) G3 A0L(3) H2 F4 B8 D7 I/O9R A9 VDD I/O11R C7 I/O8R D6 E5 UBL CNTENL C6 I/O3R A8 I/O10R B7 VSS I/O6R D5 E4 F3 LBL B6 C5 LBR VDD A7 VDD I/O5R I/O2R D4 E3 VSS CEL B5 C4 UBR A6 I/O7R VSS CNTRPTR D3 E2 F1 B4 INTR INTL A5 I/O4R I/O1R C3 CNTENR CER E1 VDD CLKR C2 ADSR A4 I/O0R I/O14L NC J10 A11L(3) K10 A8L(3) NOTES: 1. The device setup shown above features multiplexed address and data signals on the right port and non-multiplexed address and data signals on the left port. 2. For multiplexed address and data signal operation on the left port, this pin should be set to VDD. For non-multiplexed address and data signal operation on the left port, this pin should be set to VSS. 3. For multiplexed address and data signal operation on the left port, these pins should be set to VSS. 3 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Pin Names (70P9268) Left Port CE L R/W L OE L A 0L – A 15L I/O 0L – I/O 15L N/A CLK L UB L LB L ADS L CNTEN L CNTRPT L INT L ZZ L Right Port CE R R/W R OE R N/A N/A I/O+A 0R – I/O+A 15R CLK R UB R LB R ADS R CNTEN R CNTRPT R INT R ZZ R SFEN SF 0-7 M SEL V DD V SS Final Datasheet Industrial Temperature Range Names Chip Enable (Input) Read/W rite Enable (Input) Output Enable (Input) Address (Input) Data (Input/Output) Multiplexed Address and Data (Input/Output) Clock (Input) Upper Byte Enable (Input) Lower Byte Enable (Input) Address Strobe Enable (Input) Counter Enable (Input) Counter Repeat (Input) Interrupt Flag (Output) Sleep Mode Enable (Input) Special Function Enable (Input) Special Function I/O (Input/Output) Left Port Mode Select Power (1.8V) Ground (0V) NOTES: 1. The device setup shown above features multiplexed address and data signals on both ports. 2. For non-multiplexed address and data signal operation on the left port, set pin E7 = VSS. 4 of 23 August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range Truth Table I - Read/Write and Enable Control (Multiplexed Port) OE CLK CE UB LB R/W ADS ZZ Upper Byte Lower Byte Cycle Address X ↑ H X X X X L High Z High Z X X Deslected X ↑ L H H X X L High Z High Z X X Both bytes deselected X ↑ L L H L L L -- -- N AN W rite to Upper Byte X ↑ X X X L H L D IN High Z N+1 -- X ↑ L H L L L L -- -- N AN X ↑ X X X L H L High Z D IN N+1 -- X ↑ L L L L L L -- -- N AN X ↑ X X X L H L D IN D IN N+1 -- H ↑ L L H H L L -- -- N AN L ↑ X X X H H L D O UT High Z N+2 -- H ↑ L H L H L L -- -- N AN L ↑ X X X H H L High Z D O UT N+2 -- H ↑ L L L H L L -- -- N AN Mode W rite to Lower Byte W rite to Both Bytes Read Upper Byte O nly Read Lower Byte O nly Read Both Bytes L ↑ X X X H H L D O UT D O UT N+2 -- H ↑ L L L X H L High Z High Z X X Outputs Disabled X X X X X X X H High Z High Z X X Sleep Mode – Power down Truth Table II - Read/Write and Enable Control (Non-Multiplexed Port) OE X X X X X L L L H X CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ X CE H L L L L L L L L X UB X H L H L L H L L X LB X H H L L H L L L X R/W X X L L L H H H X X ZZ L L L L L L L L L H Upper Byte I/O High Z High Z D IN High Z D IN D OUT High Z D OUT High Z High Z Lower Byte I/O High Z High Z High Z D IN D IN High Z D OUT D OUT High Z High Z Mode Deselected Both Bytes Deselected W rite To Upper Byte Only W rite to Lower Byte Only W rite to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Sleep Mode – Power Down Truth Table III - Address Counter Control External Address Internal Address Used An An + 1 CLK ADS CNTEN CNTRPT An X Previous Internal Address X An ↑ ↑ L H X L H H X An + 1 An + 1 ↑ H H H X X An ↑ X X L Mode External Address Used Counter Enabled – Internal Address Generation External Address Blocked – Counter Disabled (An + 1 reused) Counter Reset to Last External Address Loaded Recommended Operating Temperature and Supply Voltage G ra d e I n d u s t r ia l A m b ie n t T e m p e ra tu re -4 0 °C to + 8 5 ° C GND 0V 5 of 23 VDD 1 .8 V + /- 1 0 0 m V August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range Recommended DC Operating Conditions Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 1.7 0 1.2 -0.2 Typ. 1.8 0 --- Max. 1.9 0 VDD + 0.2 0.4 Unit V V V V Absolute Maximum Ratings Symbol VDD VTERM TBIAS TSTG TJN IOUT Rating Voltage on Input, Output and I/O Terminals with Respect to VSS Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature DC Output Current Industrial -0.5V to VDD +0.3V Unit V -0.5V to +2.9V V -55 to +125 -65 to +150 +150 20 °C °C °C mA Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 9 11 Unit PF PF DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8V +/- 100mV) S ym bo l |I LI | |I LO | P aram eter Input Le ak age C u rrent O utput Leak age C urrent V OL V OH V O LS F O utput Lo w V o lta ge O utput H ig h V olta g e O utput Lo w V o lta ge T es t C onditions V IN = V S S to V D D C Ex = V IH or O Ex = V IH or V O U T = V S S to V D D I O L = 0.1m A , V D D = M in I O H = -0 .1m A , V D D = M in I O L = 4m A , V D D = M in 6 of 23 M in. --- M ax. 1 1 U nit Ua UA -V D D – 0.2 V -- 0.2 -0.4 V V V August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8V +/- 100mV) Symbol Parameter Test Conditions IDD Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports – TTL Inputs) Standby Current (One Port – TTL Inputs) Full Standby Current (Both Ports CMOS Inputs) CEL and CER = VIL, Outputs Disabled, (1) f = fMAX CEL = CER = VIH, Outputs Disabled, (1) f = fMAX CE”A” = VIL and CE”B” = VIH, Active Port Outputs Disabled, (1) f = fMAX Both Ports Outputs Disabled CEL and CER > VDD – 0.2V, VIN > VDD – 0.2V, (2) or VIN < 0.2V, f = 0 CE”A” < 0.2V and CE”B” > VDD – 0.2V, VIN > VDD – 0.2V or VIN < 0.2V, (1) Active Port Outputs Disabled, f = fMAX ZZL and ZZR > VDD – 0.2V ISB1 ISB2 ISB3 ISB4 IZZ Full Standby Current (One Port – CMOS Inputs) Sleep Mode Current 70P9268 Typ. Max. 15 mA 25 mA 2 mA 4 mA 3 mA 5 mA 2 uA 8 uA 3 mA 5 mA 2 uA 8 uA NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using “AC TEST CONDITIONS” at input levels of GND to 1.8V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. AC Test Conditions Input Pulse Levels Input Rise/Fall Times VSS to VDD 3ns Max. Input Timing Reference Levels VDD/2 Output Reference Levels VDD/2 Output Load Figure 1 1.8V R1 13500Ω R2 13500Ω 1.8V R1 R2 30pF(1) Figure 1. AC Output Test Level (5pF for tLZ, tHZ, tWZ, tOW) 7 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Final Datasheet Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing for Multiplexed Port) (VDD = 1.8V +/- 100mV) Symbol tCYC tCH tCL tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD tDC tCKHZ tCKLZ tINS tINR tCO 70P9268L Ind. Only Min. Max. 20 -8 -8 --3 -3 5 -1 -5 -1 -5 -1 -5 -1 -5 -1 -5 -1 -5 -1 --10 2 --10 -12 2 -2 9 2 -12 -12 -5 -- Parameter Clock Cycle Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to High Z Output Enable to Low Z Clock to Data Valid Data Output Hold After Clock High Clock High to Output High Z Clock High to Output Low Z Interrupt Flag Set Time Interrupt Flag Reset Time Clock to Clock Offset 8 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Final Datasheet Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing for Non-Multiplexed Port) (VDD = 1.8V +/- 100mV) Symbol tCYC tCH tCL tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOLZ tOHZ tCD tDC tCKHZ tCKLZ tINS tINR tCO 70P9268L Ind. Only Min. Max. 20 -8 -8 --3 -3 5 -1 -5 -1 -5 -1 -5 -1 -5 -1 -5 -1 -5 -1 -2 --10 -12 2 -2 10 2 -12 -12 -5 -- Parameter Clock Cycle Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Low Z Output Enable to High Z Clock to Data Valid Data Output Hold After Clock High Clock High to Output High Z Clock High to Output Low Z Interrupt Flag Set Time Interrupt Flag Reset Time Clock to Clock Offset 9 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Timing Waveform for Mux’d Port Single Read Cycle Final Datasheet Industrial Temperature Range tCYC tCH tCL CLK tSC tHC tSB tHB CE UB / LB tSW R/W tSAD tHAD tSA tHA ADS OE tOE ADDR / DATA tOHZ tOLZ An Dn tCLZ tCD tCKHZ Timing Waveform for Mux’d Port Burst Read Cycle tCYC tCH tCL CLK tSAD tHAD ADS tSCN tHCN CNTEN tSA ADDR / DATA tHA An Dn Dn+1 tCKLZ tCD 10 of 23 tCKHZ August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Timing Waveform for Mux’d Port Single Write Cycle Final Datasheet Industrial Temperature Range tCYC tCH tCL CLK tSC CE tSW R/W tSAD tHAD tSA tHA ADS ADDR / DATA tSD An tHD Dn An+1 Dn+1 Timing Waveform for Mux’d Port Burst Write Cycle tCYC tCH tCL CLK tSC CE tSW R/W tSAD tHAD ADS tSCN CNTEN tSA ADDR / DATA tHA An tSD tHD Dn Dn+1 11 of 23 Dn+2 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Final Datasheet Industrial Temperature Range Timing Waveform of Mux’d Port Write to Non-Mux’d Port Read tCYC tCH tCL CLKA t sw tHW R/WA tSA tHA tSA tHA ADSA ADDR / DATAA tSD MATCH tHD VALID tCYC tCH tCL tCO CLKB tCD tSW tHW tSA tHA R/WB ADDRESSB NO MATCH MATCH DATAB VALID tDC NOTES: 1. CE, UB/LBn = VIL; CNTEN and REPEAT = VIH. 2. OE = VIL for Port, which is being read from. OE = VIH for Mux’d Port, which is being written to. 3. If tCO < minimum specified, then data from Non-Mux’d Port read is not valid until following Non-Mux’d Port clock cycle (i.e., time from write to valid read on opposite port will be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Non-Mux’d Port read is available on first Non-Mux’d Port clock cycle (i.e., time from write to valid read on opposite port will be tCO + tCYC2 + tCD2). 12 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Final Datasheet Industrial Temperature Range Timing Waveform of Non-Mux’d Port Write to Mux’d Port Read tCYC tCH tCL CLKA t sw tHW R/WA tSA tSA ADDRESSA tHA MATCH tSD DATAIN”A” NO MATCH tHD VALID tCO CLKB tSW tHW R/WB tSA ADDR/DATAB tHA tCD MATCH VALID tDC 13 of 23 August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Timing Waveform of Non-Mux’d Port Read-to-Write-to-Read Industrial Temperature Range tCYC tCH tCL CLK tSC tHC tSB tHB tSW tHW tSA tHA CE UB/LB tSW tHW R/W ADDRESS An An+1 An+2 An+2 tSD DATAIN An+3 An+4 tHD Dn+2 tCD tCKHZ tCKHZ (1) DATAOUT Qn+3 Qn READ NOP(4) WRITE READ NOTES: 1. Output UB/LB state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 14 of 23 August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range Timing Waveform of Non-Mux’d Port Read-to-Write-to-Read (OE Controlled) tCYC tCH tCL CLK tSC tHC tSB tHB tSW tHW tSA tHA CE UB/LB tSW tHW R/W ADDRESS An An+1 An+2 tSD DATAIN An+3 An+4 An+5 tHD Dn+2 Dn+3 tCKHZ tCD (1) DATAOUT Qn+4 Qn tOHZ OE READ WRITE READ NOTES: 1. Output UB/LB state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 15 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Final Datasheet Industrial Temperature Range Timing Waveform of Non-Mux’d Port Write with Counter Advance CLK tSA ADDRESS tHA An INTERNAL ADDRESS An tSAD An+1 An+2 An+3 An+4 tHAD ADS tSCN tHCN CNTEN tSA DATAIN tHA Dn Dn+1 WRITE EXTERNAL ADDRESS Dn+1 WRITE WITH COUNTER Dn+2 Dn+3 Dn+4 WRITE COUNTER HOLD NOTES: 1. CE, UB/LB, and R/W = VIL; CE1 and REPEAT = VIH. 2. CE, UB/LB = VIL. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 16 of 23 August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range Timing Waveform of Non-Mux’d Port Operation with Counter Repeat CLK tSA ADDRESS tHA An INTERNAL ADDRESS An tSAD tHAD tSW tHW An+1 An+2 An+2 An An+1 An+2 ADS R/W tSCN tHCN CNTEN CNTRPT DATAIN tSRPT tHRPT tSA tHA Data 0 Data 1 Data 2 Data 3 DATAOUT Data 0 WRITE TO ADS ADDRESS An ADVANCE COUNTER WRITE TO An+1 ADVANCE COUNTER WRITE TO An+2 HOLD COUNTER WRITE TO An+2 REPEAT READ LAST ADS ADDRESS An ADVANCE COUNTER READ An+1 Data 1 ADVANCE COUNTER READ An+1 NOTES: 1. CE, UB/LB = VIL. 2. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 3. No dead cycle exists during CNTRPT operation. A READ or WRITE cycle may be coincidental with the counter CNTRPT cycle: Address loaded by last valid ADS load will be accessed. 4. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 17 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Timing Waveform for x8 to x16 Bus Matching Final Datasheet Industrial Temperature Range CLKA CEA tSB tHB UBA LBA R/WA tSAD tHAD tSA tHA ADSA ADDRA / DATAA An tSAD tHAD Dn An Dn+1 CEB R/WB ADSB ADDRB / DATAB An 18 of 23 Dn, Dn+1 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Timing Waveform - Interrupt Timing Final Datasheet Industrial Temperature Range CLK CE R/W tSAD tHAD tSA tHA ADS ADDR / DATA 3FFE tSD tHD Data tINS INT tINR CLK CE R/W tSAD tHAD ADS tSOE tHOE OE 3FFE ADDR / DATA 19 of 23 Data August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Industrial Temperature Range Timing Waveform - Entering Sleep Mode Normal Operation Sleep Mode No New Reads or Writes Allowed Sleep Mode Set Cycles CLK CE R/W ADDR / DATA Data Data ZZ IZZ Timing Waveform - Exiting Sleep Mode No New Reads Or Writes Allowed Sleep Mode Normal Operation Sleep Mode Recovery Cycles CLK tSC CE tSW R/W tSAD tHAD tSA tHA ADS ADDR / DATA An tCD Dn ZZ IZZ 20 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Functional Description Final Datasheet Industrial Temperature Range The 70P9268L provides a true synchronous multiplexed and non-multiplexed Dual-Port Static RAM interface. Registered inputs provide minimal setup and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. Counter enable and counter repeat inputs are provided to facilitate burst reads and writes to the memory. Synchronous Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FFE (HEX), where a write is defined as CER = R/WR = VIL. The left port clears the interrupt through access of address location 3FFE when CEL = VIL, R/WL = VIH. Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 3FFF. The message (16 bits) at 3FFE or 3FFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address, locations 3FFE and 3FFF are not used as mail boxes, but as part of the random access memory. Truth Table IV - Interrupt Flag CLKL Ç Ç Ç Ç R /W L L X X H L e ft P o rt CEL ADDL L 3F FF X X X X L 3FF E IN T L X X L H C LK R Ç Ç Ç Ç R /W R X H L X R ig h t P o rt CER ADDR X X L 3FF F L 3FFE X X F u n c tio n IN T R L H X X S e t R ig ht IN T R F la g R e s e t R ig ht IN T R F la g S e t L e ft IN T L F la g R e s e t L e ft IN T L F la g Advanced Input Read and Output Drive Registers The IDT70P9268L is equipped with 8 Special Function (SFX) pins that can be programmed to function as either Input Read Register (IRR) or Output Drive Register (ODR) pins. IRR pins allow the user to capture the status of external binary state devices and report that status to a processor, ASIC, FPGA, etc. via a standard read access from either port. ODR pins allow the user to monitor and control the state of external binary state devices via standard reads and writes from either port. The functionality of the SF pins are determined by the status of the Pin Direction Register (PDR). Refer to Truth Table V for information on programming the PDR and operating the special function pins. Truth Table V - Input Read and Output Drive Registers SFEN L L L ADDR 0 0 0 R/W L H L I/O 0 – I/O 7 Note 1 Note 2 Note 4 I/O 8 H Note 3 L I/O 9 – I/O 15 X Note 3 X Function Program Pin Direction Register Reading the status of SFn and PDRn W rite to O utput Drive Register NOTES: 1. If I/On = H, SFn is programmed as an output and I/On will be used to read and write to this ODR location during subsequent transactions when I/O8 = L. If I/On= L, SFn is programmed as an input and I/On will be used to read this IRR location during subsequent reads where I/O8 = L. For n = 0-7. If PDRn = 0, I/On = IRRn (the registered value of SFn). If PDRn = 1, I/On = ODRn (the value last written to ODRn). For n = 8-15, I/On = PDRn-8. For I/O0 - I/O7, the value written to I/On will be input to each ODRn location (where PDRn = 1) with a “1” corresponding to “on” and a “0” corresponding to “off”. 2. 3. 4. 21 of 23 August 22, 2007 IDT70P9268L Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM Special Function I/O Operation I/O 0–7 8 9 – 15 Final Datasheet Industrial Temperature Range Function W ith SFEN = L, I/O 8 = H, the value written to address 0 on I/On will determ ine the status of PDRn (1 = output, 0 = input). W ith SFEN = L, I/O 8 = L, the value written to address 0 on I/On will be input to the corresponding ODRn location (1 = on, 0 = off). W ith SFEN = L, writing a “0” to address 0 on this I/O causes the values of I/O 0 – I/O 7 to be input to their corresponding ODR locations. W ith SFEN = L, writing a “1” to address 0 on this I/O causes the values of I/O 0 – I/O 7 to be input to their corresponding PDR locations, which in turn determ ine whether SF 0 – SF 7 are individually programm ed to be inputs (IRR) or outputs (ODR). W ith SFEN = L, reads to address 0 will output the status of the PDR, where I/On = PDRn- 8 The PDR determines whether the SFX pins will operate as IRR or ODR. The PDR is programmed by writing to address x0000 with SFEN = VIL and I/O8 = H. Writing a “0” to I/OX will set SFX to be an IRR pin. Writing a “1” to I/OX will set SFX to be an ODR pin. The status of the Special Function pins and the PDR can be read as a standard memory access to address x0000 from either port and the data is output via the standard I/Os (Truth Table V). During Special Function reads I/O0 - I/O7 output the status of the Special Function pins with I/On corresponding to SFn. I/O8 - I/O15 outputs the status of the Pin Direction Register with I/On = PDRn-8. For SF pins set to ODR operation, the status of these pins is determined by using standard write accesses from either port to address x0000 with SFEN = VIL and I/O8 = L. A written “1” will correspond to “on” for the connected binary state device and a written “0” will correspond to “off”. Sleep Mode The IDT70P9268 is equipped with an optional sleep or low-power mode on both ports. The sleep mode pin on both ports is asynchronous and active high. During normal operation, the ZZ-pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode. For normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. Clocks must also meet cycle high and low times during these periods. Three cycles prior to asserting ZZ (ZZX = VIH) and three cycles after de-asserting ZZ (ZZX = VIL), the device must be disabled via the chip enable pins. If a write or a read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). When exiting sleep mode, the device must be in Read mode (R/WX = VIH) when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid data. During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected and will not perform any reads or writes. 22 of 23 August 22, 2007 IDT70P9268L Final Datasheet Very Low Power 16K x 16 Dual Port Synchronous Static RAM Industrial Temperature Range Ordering Information XXXXX 999 A Device Type Speed Package A A Process/ Temperature Range Blank I Commercial (0°C to+70°C) Industrial (-40°C to+85°C) G Green BZ 100-pin FPBGA (BY-100) 50 70P9268 Speed in Megahertz 16Kx16 Low-Power Dual-Port RAM Final Datasheet: Definition "Final” datasheets contain descriptions for products that are in full release. Revision History 02/06/07: Initial Release 08/21/07: Final Datasheet. Initial Release CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: 408-284-2794 [email protected] The IDT logo is a registered trademark of Integrated Device Technology, Inc. 23 of 23 August 22, 2007