HS-1825ARH ® Data Sheet September 25, 2008 Radiation Hardened High-Speed, Dual Output PWM The Radiation Hardened HS-1825ARH Pulse Width Modulator is designed to be used in high frequency switched-mode power supplies and can be used in either current-mode or voltage-mode. It is well suited for single-ended boost converter applications. Device features include a precision voltage reference, low power start-up circuit, high frequency oscillator, wide-band error amplifier, and fast current-limit comparator. The use of proprietary process capabilities and unique design techniques results in fast propagation delay times and high output current over a wide range of output voltages. FN4561.8 Features • Electrically Screened to DESC SMD # 5962-99558 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Environment - Maximum Total Dose . . . . . . . . . . . . . . . . 300 krad(SI) - Vertical Architecture Provides Low Dose Rate Immunity - DI RSG Process Provides Latch-Up Immunity • Low Start-Up Current . . . . . . . . . . . . . . . . . . . 100µA (Typ) • Fast Propagation Delay . . . . . . . . . . . . . . . . . . 80ns (Typ) • 12V to 30V Operation • 1A (Peak) Dual Output Drive Capability Constructed with the Intersil Rad Hard Silicon Gate (RSG) Dielectric Isolation BiCMOS process, the HS-1825ARH has been specifically designed to provide highly reliable performance when exposed to harsh radiation environments. • 5.1V Reference Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. • Latched Overcurrent Comparator with Full Cycle Restart Detailed Electrical Specifications for the HS-1825ARH are contained in SMD 5962-99558. That document may be easily downloaded from our website. www.intersil.com/ Applications • Undervoltage Lockout • Programmable Soft-Start • Switching Frequencies to 500kHz • Programmable Leading Edge Blanking Circuit • Current or Voltage Mode Switching Power Supplies • Motor Speed and Direction Control Pinout HS-1825ARH SBDIP (CDIP2-T16) AND FLATPACK (CDFP4-F16) TOP VIEW INV 1 16 VREF 5.1V NON-INV 2 15 VCC E/A OUT 3 14 OUTPUT B CLOCK 4 13 VC RT 5 12 POWER GND CT 6 11 OUTPUT A RAMP 7 SOFT START 8 10 GND 9 ILIM/SD NOTE: Grounding the Soft-Start pin does not inhibit the outputs. The outputs may be inhibited by applying >1.26V to the ILIM/SD pin. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-1825ARH Ordering Information INTERNAL MKT. NUMBER ORDERING NUMBER TEMP. RANGE (°C) PKG. DWG. # PACKAGE 5962F9955801V9A HS0-1825ARH-Q -50 to +125 HS0-1825ARH/Sample HS0-1825ARH/Sample -50 to +125 5962F9955801VEC HS1-1825ARH-Q -50 to +125 16 Ld SBDIP D16.3 5962F9955801QEC HS1-1825ARH-8 -50 to +125 16 Ld SBDIP D16.3 5962F9955801VXC HS9-1825ARH-Q -50 to +125 16 Ld Flatpack K16.A 5962F9955801QXC HS9-1825ARH-8 -50 to +125 16 Ld Flatpack K16.A HS1-1825ARH/Proto HS1-1825ARH/Proto -50 to +125 16 Ld SBDIP D16.3 HS9-1825ARH/Proto HS9-1825ARH/Proto -50 to +125 16 Ld Flatpack K16.A Typical Performance Curves 100 10k C220pF DMAX 90 C1000pF 1k DMAX (%) FREQUENCY (kHz) C470pF C2200pF C4700pF 100 80 70 60 C22nF 10 C10nF 1 10 Rt TIMING RESISTANCE (kΩ) 100 FIGURE 1. OSCILLATOR FREQUENCY vs Rt AND Ct 2 50 1 10 Rt TIMING RESISTANCE (kΩ) 100 FIGURE 2. MAXIMUM DUTY CYCLE vs Rt FN4561.8 September 25, 2008 HS-1825ARH Die Characteristics DIE DIMENSIONS 4710µm x 3570µm (185 mils x 140 mils) Thickness: 483µm ±25.4µm (19 mils ±1 mil) Backside Finish Silicon ASSEMBLY RELATED INFORMATION INTERFACE MATERIALS Substrate Potential Glassivation Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ±1.0kÅ Unbiased (DI) ADDITIONAL INFORMATION Top Metallization Type: ALSiCu Thickness: 16.0kÅ ±2kÅ Worst Case Current Density <2.0 x 105 A/cm2 Substrate Radiation Hardened Silicon Gate, Dielectric Isolation Metallization Mask Layout Transistor Count 225 HS-1825ARH (4) CLK/LEB RT (5) (3) EAOUT CT (6) (2) IN+ RAMP (7) (1) INSS (8) (16) VREF ILIM (9) OSCGND (NOTE 1) (15) VCC GND (10) (14) OUTB OUTA (11) (12) PGND (NOTE 2) PGND (12) (NOTE 2) (13) VC (NOTE 2) VC (13) (NOTE 2) NOTES: 1. This is the oscillator ground (OSCGND) bond pad and must be connected to GND. 2. PGND and VC each require two bond pad connections. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 3 FN4561.8 September 25, 2008