F3 Design Guide

Application Note, V1.1, October 2009
ICE3Axxx/ICE3Bxxx
CoolSET F3 Design Guide
Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
Edition 2009-10-31
Published by Infineon Technologies Asia Pacific,
168 Kallang Way,
349253 Singapore, Singapore
© Infineon Technologies AP 2004.
All Rights Reserved.
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ICE3AXXX/ 3BXXX
Revision History:
2009-10
Previous Version:
V1.0
Page
Subjects (major changes since last revision)
10
Add precaution for the startup sequence.
CoolSET F3 Design Guide:
License to Infineon Technologies Asia Pacific Pte Ltd
Luo Junyang
Jeoh Meng Kiat
Lim Chee Siong, Simon
Kok Eric
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
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V1.1
ANP0015
ICE3AXXX/ ICE3BXXX
Table of Contents
Page
1
Introduction ...................................................................................................................................5
2
Block Diagram ...............................................................................................................................6
3
Package..........................................................................................................................................8
4
Typical Application Circuit...........................................................................................................9
5
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
Function Description ..................................................................................................................10
Startup Cell....................................................................................................................................10
Soft Start and Normal Operation...................................................................................................10
Active Burst Mode .........................................................................................................................11
Entering Active Burst Mode...........................................................................................................11
Working in Active Burst Mode .......................................................................................................12
Leaving Active Burst Mode ...........................................................................................................13
VCC supply during burst mode .......................................................................................................14
6
6.1
6.2
Protection Features ....................................................................................................................15
Auto Restart Mode ........................................................................................................................15
Latched Off Mode..........................................................................................................................15
7
Blanking Window ........................................................................................................................16
References ......................................................................................................................................................17
Application Note
4
2009-10-31
ICE3AXXX/ ICE3BXXX
1
Introduction
The CoolSET™-F3, ICE3AXXX/ICE3BXXX, is the further development of the second generation
CoolSET™-F2 with some new features. This application note provides detail functional description of these
new features. The description of all other functions and calculations are shown in the datasheet as well as in
the application note “AN-SMPS-ICE2Axxx”.
A new standby power concept is implemented into the controller to meet the requirements for the lowest
Standby Power at minimum load and no load condition. An intelligent Active Burst Mode is used for the
Standby Mode. The controller constantly monitors the feedback voltage during Burst Mode which leads to
immediate response in case of load jump at the output. Entering and leaving Burst Mode depends on the
level of the feedback voltage.
Unlike the CooSET™-F2 which uses an external resistor for startup, the CooSET™-F3 has an integrated
startup cell which is connected to high voltage MOSFET Drain. It charges the VCC capacitor when AC is
pluged in. the startup cell is switched off once Undervoltage Lockout on-threshold 15V is exceeded. Power
losses are therefore reduced. The efficiency under light load condition is increased dramatically.
Auto Restart Mode and Latched Off Mode are implemented in the IC during protection. This feature increase
the system’s robustness and safety.
The ICE3AXXX/ICE3BXXX provides a Blanking Window, which delays the activation of the overload
protection for a limited time. This allows the IC to support applications which need surge power for a short
while (e.g. switching on capacitive load). The Blanking Window is also used to avoid accidentally entering of
the Active Burst Mode, which assures the stability of the system in all operating conditions.
In this application note, the IC functions are described in detail and its performance is shown by the results.
Application Note
5
2009-10-31
ICE3AXXX/ ICE3BXXX
2
Block Diagram
+
Snubber
CBulk
85 ... 270 VAC
Converter
DC Output
VOUT
-
CVCC
VCC
6.5V
3.25k
RSoftS
Drain
Depl-CoolMOS™
Power Management
Internal Bias
Startup Cell
6.5V
Voltage
Reference
T2
SoftS
T3
VCC
17V
C1
4.4V
4.0V
4.0V
S1
Undervoltage Lockout
Power-Down
Reset
5k
CSoftS
GND
1V
T1
&
G1
15V
8.5V
Oscillator
Duty Cycle
max
Spike
Blanking
8.0us
Soft Start Soft-Start
Comparator
C11
Thermal
m
Clock
&
G7
C7
TShutdown
j
>140°C
C2
PWM
Section
Duty Cycle 0.72
Max
1
Gate
Driver
FF1
S
R Q
1
G8
&
G9
G2
5.4V
6.5V
4.8V
RFB
C3
PWM
Comparator
C4
&
C8
Auto Restart
Mode
G5
Propagation-Delay
Compensation
5k
C5
FB
10pF
1.32V
4.0V
Control Unit
3.4V
&
G6
Active Burst
Mode
0.85V
x3.7
C6a
C6b
&
G10
PWM OP
&
G1
1
Vcsth Leading
Edge
Blanking
220ns
C10
C12
0.257V
Current Mode
10k
1pF
CS
D1
RSense
Current Limiting
CoolSET™F3
ICE3Axxxx ICE3Bxxxx
fOSC
Figure 1
100kHz
67kHz
Block Diagram of CoolSET™-F3 ICE3XXXX65 (non latached mode)
Application Note
6
2009-10-31
ICE3AXXX/ ICE3BXXX
+
Snubber
CBulk
85 ... 270 VAC
Converter
DC Output
VOUT
-
CVCC
VCC
6.5V
3.25kΩ
RSoftS
Internal Bias
T3
1V
5kΩ
CSoftS
VCC
4.4V
21V
C1
&
G1
Spike
Blanking
8.0us
1
G3
15V
4.0V
S1
Oscillator
Duty Cycle
max
Latched Off
Mode
Soft Start Soft-Start
Comparator
m
Clock
&
G7
C7
Tj >140°C
1
G8
1
Gate
Driver
FF1
S
R Q
&
G9
G2
5.4V
C3
PWM
Comparator
6.5V
C8
4.8V
RFB
C4
&
Auto Restart
Mode
G5
C5
10pF
1.32V
4.0V
Control Unit
3.4V
&
G6
Active Burst
Mode
0.85V
1.66V
C11
C10
x3.7
C6a
C6b
Spike
Blanking
190ns
Propagation-Delay
Compensation
5kΩ
FB
GND
PWM
Section
0.72
8.5V
Thermal Shutdown
C2
CoolMOS
™
Undervoltage Lockout
Power-Down
Reset
T1
Startup Cell
6.5V
Voltage
Reference
Latched Off
Mode Reset
VVCC < 6V
T2
SoftS
Drain
Power Management
PWM OP
&
G1
1
&
G10
C12
Current Mode
Vcsth Leading
Edge
Blanking
220ns
0.257V
10kΩ
1pF
CS
D1
RSense
Current Limiting
ICE3xxxxxL / CoolSET™-F3 with Latched off Mode
Figure 2
Block Diagram of CoolSET™-F3 ICE3XXXX65L (Latached mode)
Application Note
7
2009-10-31
ICE3AXXX/ ICE3BXXX
3
Package
2
There are four different package for CoolSET™-F3 product, DIP-8, DIP-7, TO-220 and I -Pak.
SoftS
1
8
GND
SoftS
1
8
GND
FB
2
7
VCC
FB
2
7
VCC
CS
3
6
N.C
CS
3
Drain
4
5
Drain
Drain
4
5
Drain
1
SoftS
FB
Drain
2
3
5
6
7
2
I -Pak
TO-220
Application Note
4
FB
7
SoftS
6
VCC
5
GND
4
CS
3
VCC
2
GND
Drain
1
DIP-7
Isense
DIP-8
8
2009-10-31
ICE3AXXX/ ICE3BXXX
4
Typical Application Circuit
Figure 3
Typical application circuit with CoolSET™-F3, ICE3B0565 15W
Application Note
9
2009-10-31
ICE3AXXX/ ICE3BXXX
5
Function Description
5.1
Startup Cell
The Startup Cell delivers a constant charge current of IVCCCharge=1.05mA to charge up the VCC capacitor CVcc
at VCC pin. When VCC exceeds the on-threshold VCCon=15V, the internal reference voltages and bias circuit
are switched on and IC blocks start to be operates. The Startup Cell is switched off by UVLO for energy
saving. The startup delay time, tDELAY, is independent from the AC line input voltage. It can be estimated by
the equation (1):
t DELAY =
VCCon ⋅ CVcc
I Vcc _ Ch arg e − I Vcc _ Start
(1)
where, IVcc_Start is the supply current when IC is in off state. Figure 4 shows the startup time delay at 85VAC
input.
Vds
0.34s
VFB
VCC
VSST
Figure 4
The startup delay time at AC line input voltage of 85V.
Precaution : For a typical application, start up should be VCC ramps up first, other pin (such as FB pin)
voltage will follow VCC voltage to ramp up. It is recommended not to have any voltage on other
pins (such as FB; BA and CS) before VCC ramps up.
5.2
Soft Start and Normal Operation
When the IC is turned on after the Startup Delay time, the Soft Start capacitor at pin1, CSST, is charged from
the initial level of 1V. The Soft Start voltage VSOFTS is generated by CSST and the internal pull up resistor
RSOFTS. The duty cycle of the gate drive is determined by the VSOFTS during the Soft Start phase, which is
terminated when VSOFTS reaches 4V. Afterward, IC goes into normal mode and the duty cycle is dependent
on the FB signal. VSOFTS is internally clamped to 4.4V during normal operation mode. The duration of the Soft
Start can be estimated by the equation (2). Figure 5 shows the soft start behaviour at 85VAC input. It can be
seen that the primary peak current follows VSST voltage and slowly increase to the maximum. The soft start
time is about 32ms.
Application Note
10
2009-10-31
ICE3AXXX/ ICE3BXXX
t SOFTS = C SST × RSOFTS × ln
5.5V
= 0.79 ⋅ C SST ⋅ RSOFTS
6.5V − 4V
(2)
VFB
VSST
Vout
1V
32ms
Figure 5
VCS
Soft start at AC line input voltage of 85V
After soft start stage, IC goes into normal operation with the conventional primary peak current control
scheme. Please refer to “AN-SMPS-ICE2Axxx”.for the details of normal operation.
5.3
Active Burst Mode
The IC provides an Active Burst Mode function at no load or low load conditions to enable the system to
achieve the lowest standby power requirement of less than 100mW. Active Burst Mode means the IC is
always in the active state and can therefore immediately response to any changes on the FB signal, VFB.
5.3.1
Entering Active Burst Mode
Because of the current mode control scheme, the feedback voltage VFB actually controls the power delivery
to output. When the output load is getting lower, the feedback voltage VFB drops. If it stays below 1.32V for a
timeframe set by the blanking time, the IC enters into the burst mode operation. The threshold power to enter
burst mode is:
PBURST _ enter = 0.5 ⋅ LP ⋅ (
VFB _ burst − VRAMP
Rsense ⋅ AV
) 2 ⋅ f SW
(3)
where, LP is the transformer primary inductance, VFB_burst=1.32V is the feedback voltage at which the system
starts to burst, VRAMP=0.85V is the maximum level of the internal Voltage Ramp on which the amplified
current ramp signal of the PWM-OP is superimposed, AV =3.7 is the internal PWM-OP gain, Rsense is the
current sense resistor, fSW is the switching frequency. Figure 6 shows the test waveform with the load drop
from full load to light load. After blanking time IC goes into burst mode.
Application Note
11
2009-10-31
ICE3AXXX/ ICE3BXXX
Vds
VSST
Vout
VFB
Figure 6
Entering Burst Mode
5.3.2
Working in Active Burst Mode
During active burst mode, the IC is constantly monitoring the output voltage by feedback pin, VFB, which
controls burst duty cycle and burst frequency. The burst “on” starts at VFB reaches 4V and stop at VFB is
down to 3.4V. During burst “on”, the primary current limit is set to only 25% of maximum peak current
(VCS=0.25V) to reduce the conduction losses and to avoid audible noise. The FB voltage is changing like a
saw tooth between 3.4V and 4V.The corresponding secondary output ripple (peak to peak) is regulated as
below:
Vout _ ripple _ pp =
Ropto
RFB ⋅ Gopto ⋅ GTL 431
⋅ ∆VFB
(4)
where, Ropto is the resistor series with optocoupler at the secondary to limit the ooptocoupler current, RFB is
the IC internal pull up resistor connected to FB Pin, Gopto is the current transfer gain of optocoupler, GTL431 is
the voltage transfer gain between the comparator TL431 output and Vout, ∆VFB=4-3.4=0.6V is the ripple on
the VFB during burst operation.
The leaving burst power threshold, ie. maximum power to be handled during burst operation is:
Pburst _ max = 0.5 ⋅ LP ⋅ (0.25 ⋅ i peak _ max ) 2 ⋅ f SW = 0.5 ⋅ LP ⋅ (0.25 ⋅
VCS _ max
Rsense
) 2 ⋅ f SW = 0.0625 ⋅ Pmax
(5)
Where, ipeak_max is the maximum primary peak current, VCS_max is the cycle by cycle current limit threshold
at CS Pin, Pmax is the maximum output power of the power supply. It can be seen that the maximum power in
burst mode is around 6.25% of Pmax. Figure 7 and Figure 8 show the test waveforms of burst mode at no
load and light load respectively. It can be seen that the burst ripple is well regulated to be 32mV and it is
independent on the output power.
Application Note
12
2009-10-31
ICE3AXXX/ ICE3BXXX
Vds
Vout
32mV
VFB
Figure 7
working in Burst Mode at no load
Vds
Vout
32mV
VFB
Figure 8
working in Burst Mode at light load
5.3.3
Leaving Active Burst Mode
When the output load is increasing to be higher than Pburst_max, Vout will drop a little bit and VFB will rise up
fast to 4.8V. The system leaves burst mode immediately when VFB reaches 4.8V. Once system leaves burst
mode, the current sense voltage limit, VCS_MAX, is released to 1V, the feedback voltage VFB swings back to
the required level. The timing diagram of leaving burst mode is shown in Figure 9.
Application Note
13
2009-10-31
ICE3AXXX/ ICE3BXXX
4.8V
4V
VFB
3.4V
Vout
Vout_AV
Vout_drop_max
1V
VCS
0.25V
Figure 9
the timing diagram of leaving burst mode
The maximum Vout drop during the mode transition is
Vout _ drop _ max =
Ropto
RFB ⋅ Gopto ⋅ GTL 431
⋅ ( 4 .8 −
1.1 ⋅ Ropto
3 .4 + 4
)=
RFB ⋅ Gopto ⋅ GTL 431
2
(6)
Figure 10 shows the waveform to leave burst mode with load jump from light load to full load. The output
voltage drop during the transition is about 130mV.
1V
0.25V
VCS
Vout
130mV
VFB
Figure 10
test waveform of leaving burst mode
5.3.4
VCC supply during burst mode
The supply voltage for VCC has to be designed so that it always stays above VCC_OFF limit during burst mode,
even at no load. This can lead to a substantial high voltage at VCC pin during maximum load operation. The
Application Note
14
2009-10-31
ICE3AXXX/ ICE3BXXX
circuit configuration for VCC in Figure 3, which consists of C5, R2, ZD1 and C6, is to ensure that the VCC will
never exceed 22V under any operation conditions.
6
Protection Features
The IC provides several protection features which lead to the Auto Restart Mode or Latched off mode. The
following table shows the conditions of the system failure and the associate protection mode.
“Latched”
ICE3xxx65L
Auto Restart
NA
NA
Latched off
TJ > 140 C
Auto Restart
Latched off
VCS>1.67V
NA
Latched off
Failure condition
VCC Overvoltage
VCC > 17V,
VSOFTS < 4V
VFB > 4.8V
VCC > 21V,
VFB > 4.8V
Overtemperature
Short Winding/
Short Diode
Output Overload /
Output Short Circuit
Open Loop
VCC Undervoltage
6.1
“Non-Latch”
ICE3xxx65
Protection functions
O
VFB > 4.8V and after the blanking
window at VSOFTS > 5.4V
During power up at light load condition
−> VCC Overvoltage
During normal operation
−> Output Over Load
Auto Restart
Auto Restart
Auto Restart
Latched off
Auto Restart
Auto Restart
VCC < 8.5V
Auto Restart
Auto Restart
Auto Restart Mode
There is always a startup phase with switching cycles in the Auto Restart Mode. After this startup phase the
conditions are checked whether the failure is still present. Normal operation proceeds once the failure mode
is removed. Otherwise, new startup phase will be initiated again.
Figure 11 shows the switching waveform of the VCC and the feedback voltage VFB when the output is shorted
to ground. The IC is turned on at VCC = 15V. After going through the startup phase, IC is off again due to the
fault still exists. VCC is discharged until 8.5V. Then, the Startup Cell is activated again to charge up capacitor
at VCC that initiates another restart cycle.
6.2
Latched Off Mode
In case of Latched Off Mode (only available for ICE3XXX65L), there is no new startup phase any more.
Once Latched Off Mode is entered, the internal Voltage Reference is switched off in order to reduce the
current consumption of the IC. In this stage only the UVLO is working which switches on/off the startup cell at
VCCoff/VCCon. Latched Off Mode can only be reset when AC line input is plugged out and VCC is discharged to
be lower than 6V.
Application Note
15
2009-10-31
ICE3AXXX/ ICE3BXXX
VdS
VFB
VCC
VSST
Figure 11
Auto Restart Mode
7
Blanking Window
The IC controller provides an adjustable blanking window before entering into Burst Mode or entering the
Auto Restart Mode due to output overload/short circuit. The purpose is to ensure that the system will not
enter Active Burst Mode or Protection Mode unintentionally. The blanking time is generated by charging the
soft start capacitor CSST from 4.4V to maximum 5.4V. The gate drive is still activated during this time period
until the feedback voltage VFB rises up above 4.8V. In case of output overload or short circuit, the transferred
power during the blanking period is limited to the maximum power defined by the value of the sense resistor
Rsense. The blanking time can be calculated by
t blanking = C SST ⋅ RSOFTS ⋅ ln
2.1V
= 0.65 ⋅ C SST ⋅ RSOFTS
6.5V − 5.4V
(7)
Figure 12 shows the test waveform when secondary output is shorted. The blanking time to enter the
protection mode is about 23ms.
Vds
23ms
VFB
1V
VSST
VCS
Figure 12
blanking window for output overload protection
Application Note
16
2009-10-31
ICE3AXXX/ ICE3BXXX
References
[1]
Infineon Technologies, Datasheet, CoolSET™-F3 Off-Line SMPS Current Mode Controller with
Integrated 650V Startup Cell / CoolMOS™
[2]
Harald Zoellinger, Rainer Kling, ICE2AXXX for Off-Line Switching Power supply.
[3]
Lim Chee Siong, Luo Junyang, Jeoh Meng Kiat, SMPS Evaluation Board with CoolSET™ F3
ICE3B0565.
Application Note
17
2009-10-31