Ordering Ordering number number:: ENA1841A ENA1841A LC87F7932B CMOS IC 32K-byte FROM and 2048-byte RAM integrated http://onsemi.com 8-bit 1-chip Microcontroller Overview The LC87F7932B is an 8-bit microcontroller that, centered around a CPU running at a minimum bus cycle time of 250ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (onboard programmable), 2048-byte RAM, an on-chip debugger, an LCD controller/driver, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), two 16-bit timers/counters (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a real time clock function (RTC), a base timer serving as a time-of-day clock, a synchronous SIO interface with automatic transfer function, an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 7-channel AD converter with a 12-/8-bit resolution selector, a high-speed clock counter, a system clock frequency divider, an internal reset circuit, and a 21source 10-vector interrupt function. Features Flash ROM • Capable of on-board programming with a wide supply voltage range of 3.0V to 5.5V • 128-byte block erase • 32768 × 8 bits RAM • 2048 × 9 bits Minimum Bus Cycle Time • 250ns (4MHz) VDD=2.4V to 3.6V Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC) • 750ns (4MHz) VDD=2.4V to 3.6V * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.1.04 41812HKIM 20120328-S00004 No.A1841-1/30 LC87F7932B Operating Temperature Range • -40°C to +85°C Ports • Normal withstand voltage I/O ports Ports whose input/output can be programmed in 1-bit units: Multiplexed functions Input ports (for debugger): LCD ports (segment output): • LCD ports/general purpose I/O ports Segment output: Common output: Bias power supply for LCD driving Multiplexed functions Input/output ports: • Oscillator pins: • Reset pin: • Power supply: 21 (P0n, P1n, P30, P70 to P73) 3 (DBGP0 (P05) to DBGP2 (P07)) 8 (P1n) 32 (S00 to S31) 4 (COM0 to COM3) 5 (V1 to V3, CUP1, CUP2) 36 (LPAn, LPBn, LPCn, LPL0 to LPL3, P1n) 4 (CF1, CF2, XT1, XT2) 1 (RES) 5 (VSS1, VSS2, VDD1, VDD2, V2) LCD Controller (1) Seven display modes are available (2) Duty: 1/3 duty, 1/4 duty (3) Bias: 1/2 bias, 1/3 bias (4) Segment/common output can be switched to general purpose I/O ports. (5) LCD power range 1) 1/3 bias V1: 1.2V to 1.8V V2: 2.4V to 3.6V V3: 3.6V to 5.4V An LCD panel that supports the V2 (=VDD) × 1.5[V] must be used when 1/3 bias is selected. If the supply voltage VDD is 3.0V, for example, use an LCD panel that supports 4.5V. 2) 1/2 bias V1: 1.2V to 1.8V V2: 2.4V to 3.6V V3: 2.4V to 3.6V (Connect V2 and V3 externally.) An LCD panel that supports the V2 (=VDD)[V] must be used when 1/2 bias is selected. If the supply voltage VDD is 3.0V, for example, use an LCD panel that supports 3.0V. Timers • Timer 0: 16 bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8 bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16 bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16 bit counter (with a 16 bit capture register) • Timer 1: 16 bit timer/counter that supports PWM/toggle output Mode 0: 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter (with toggle output) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16 bit timer/counter with an 8-bit prescaler (with toggle output) (Toggle outputs also from the low-order 8 bits) Mode 3: 16 bit timer with an 8-bit prescaler (with toggle output) (The low-order 8 bits can be used as a PWM.) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Base Timer (1) The clock can be selected from any of the following: Subclock (32.768kHz crystal oscillator/low-speed RC oscillator), system clock, and timer 0 prescaler output. (2) Interrupts can be generated at five specified time intervals. No.A1841-2/30 LC87F7932B High-speed Clock Counter (1) Capable of counting a clock with a maximum clock rate of 8MHz (at a main clock of 4MHz). (2) Real-time output Serial Interface • SIO0: 8-bit synchronous serial interface (1) Synchronous 8-bit serial I/O (2- or 3-wire configuration, 4/3 to 512/3 tCYC transfer clock rate) (2) Continuous data transfer (variable length data transfer in bit units from 1 to 256 bits, 4/3 to 512/3 tCYC transfer clock rate) (3) Bi-phase modulation Manchester/Bi-phase-Space data transfer (4) LSB first/MSB first selectable (5) SPI function: HOLD/X’tal HOLD mode release function upon receipt of a 1-byte (8-bit clock). • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clock rate) Mode 1: Asynchronous serial I/O (half duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrate) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clock rate) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) UART • Full duplex • Data length: 7/8/9 bits selectable • 1 stop bit (2 bits in continuous data transmission) • Built-in baudrate generator • Operating mode: Programmable transfer mode, fixed-rate transfer mode • Transfer data conversion: Normal (NRZ), Manchester encoding AD Converter: 12 bits/8 bits × 7 channels • 12-/8-bit AD converter resolution selectable Remote Control Receiver Circuit (multiplexed with the P73/INT3/T0IN pin) • Noise rejection function (Noise filter time constant selectable from 1/32/128 tCYC) Watchdog Timer • Generation of interrupt or system reset selectable • Two types of watchdog timer (1) Watchdog timer using an external RC circuit (2) Watchdog timer using the microcontroller’s base timer • Detection intervals (1/2/4/8 seconds) can be selected for the watchdog timer that uses the base timer by configuring options. Buzzer Output • Generates buzzer output from P17 using the base timer. Real Time Clock (RTC) (1) Uses the base timer to count the calendar years, months, days, hours, minutes, and seconds. (2) Calendar counts up to December 31, 2799 and calculates leap years automatically (3) The RTC uses the Gregorian calendar, which maintains GMT (Greenwich Mean Time). Internal Reset Function • Power-on-reset (POR) function (1) The POR causes a system reset only when power is turned on. No.A1841-3/30 LC87F7932B Interrupts: • 21 sources, 10 vectors (1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of the level equal to or lower than the current interrupt is not accepted. (2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the lowest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L 4 0001BH H or L INT3/base timer/RTC 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1-receive 8 0003BH H or L SIO1/UART-send 9 00043H H or L ADC/T6/T7/SPI 10 0004BH H or L Port 0/T4/T5 • Priority level: X > H > L • For equal priority levels, the interrupt with the lowest vector address is given priority. Subroutine Stack Levels: • Up to 1024 levels max. (Stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillator Circuits • On-chip high-speed RC oscillator: For system clock (500kHz typ) • On-chip low-speed RC oscillator: For system clock (50kHz typ) • CF oscillator: For system clock, Rf built in, Rd external • Crystal oscillator: For low-speed system clock, Rf built in • On-chip variable modulation frequency RC oscillator (VMRC): For system clock (1) Adjustable in ±4% (typ) step from a selected center frequency (2) Can measure the frequency of the source oscillator clock using an input signal from the XT1 pin as a reference. System Clock Divider • Low consumption current operation possible • The minimum instruction cycle can be selected from among 750ns, 1.5μs, 3.0μs, 6.0μs, 12μs, 24μs, 48μs, 96μs, and 192μs (at a main clock rate of 4MHz). System Clock Output • The system clock can be output from the P04 pin. No.A1841-4/30 LC87F7932B Standby Function • HALT mode: HALT mode is used to reduce power consumption. Halts instruction execution while allowing the peripheral circuits to continue operation. (Some serial transfer functions are suspended.) (1) Oscillators do not stop automatically. (2) Released by a system reset or occurrence of an interrupt • HOLD mode: HOLD mode is used to reduce power consumption. Suspends instruction execution and operation of the peripheral circuits. (1) CF oscillator, RC oscillators, crystal oscillator, and VMRC oscillator stop automatically. (2) There are five ways of releasing HOLD mode. 1) Low level input to the reset pin 2) Watchdog timer interrupt 3) Specified level input to at least one of INT0, INT1, and INT2 pins 4) Port 0 interrupt 5) SPI interrupt by receiving 1-byte (8-bit clock) • X’tal HOLD mode: X’tal HOLD mode is used to reduce power consumption. Suspends instruction execution and the operation of the peripheral circuits except the base timer. (1) CF oscillator, RC oscillators, and VMRC oscillator stop automatically. (2) The state of the crystal oscillator when X’tal HOLD mode is entered is retained. (3) There are seven ways of releasing X’tal HOLD mode. 1) Low level input to the reset pin 2) Watchdog timer interrupt 3) Specified level input to at least one of INT0, INT1, and INT2 pins 4) Port 0 interrupt 5) Base-timer interrupt 6) RTC interrupt 7) SPI interrupt by receiving 1-byte (8-bit clock) On-chip Debugger • Supports software debugging with the IC mounted on the target board. Package Form • QIP64E (14×14) (Lead-and-halogen-free product) • TQFP64J (7×7) (Lead-and-halogen-free product) • SQFP64 (10×10) (Lead-and-halogen-free product) Development Tools • On-chip debugger: TCB87 TypeB+LC87F7932B Flash ROM Programming Boards Package Programming Boards QIP64E (14×14) W87F70256Q TQFP64J (7×7) W87F70256TQ7 SQFP64 (10×10) W87F79256SQ No.A1841-5/30 LC87F7932B Flash ROM Programmer Maker Single Flash Support Group, Inc. (Formerly Ando Electric Co., Ltd.) Ganged Single/ganged Our company Model Supported Version AF9708/AF9709/AF9709B Rev 03.04 or later AF9723 (Main unit) Rev 0x.xx or later AF9833 (Unit) Rev 0x.xx or later SKK/SKK Type B Application Version (SANYO FWS) 1.05A or later Onboard SKK/SKK Type B Chip Data Version Single/ganged (SANYO FWS) 2.25 or later Device LC87F2832A LC87F7932B For information about AF-Series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: [email protected] No.A1841-6/30 LC87F7932B Package Dimensions Package Dimensions unit : mm (typ) 3159A unit : mm (typ) 3289 17.2 14.0 9.0 17 33 49 32 64 17 7.0 64 14.0 32 1 1 0.35 0.8 16 0.4 16 0.15 0.16 9.0 48 49 0.5 7.0 0.8 33 17.2 48 0.125 (0.5) 0.1 0.1 3.0max 1.2max (2.7) (1.0) (1.0) SANYO : QIP64E(14X14) SANYO : TQFP64J(7X7) Package Dimensions unit : mm (typ) 3190A 12.0 0.5 10.0 48 33 64 12.0 32 10.0 49 17 1 16 0.5 0.18 0.15 0.1 1.7max (1.5) (1.25) SANYO : SQFP64(10X10) No.A1841-7/30 LC87F7932B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 S23/LPC7 S22/LPC6 S21/LPC5 S20/LPC4 S19/LPC3 S18/LPC2 S17/LPC1 S16/LPC0 S15/LPB7 S14/LPB6 S13/LPB5 S12/LPB4 S11/LPB3 S10/LPB2 S09/LPB1 S08/LPB0 Pin Assignment LC87F7932B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P70/INT0/T0LCP/AN5 P71/INT1/T0HCP/AN6 P72/INT2/T0IN/NKIN P73/INT3/T0IN VDD2 VSS2 P10/SO0/S24 P11/SI0/SB0/S25 P12/SCK0/S26 P13/SO1/S27 P14/SI1/SB1/S28 P15/SCK1/S29 P16/T1PWML/S30 P17/T1PWMH/BUZ/S31 CUP1 CUP2 RES XT1 XT2 VSS1 CF1 CF2 VDD1 P00/UTX1/AN0 P01/RTX1/AN1 P02/AN2 P03/AN3 P04/CKO/AN4 P05/DBGP0 P06/T6O/DBGP1 P07/T7O/DBGP2 P30 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 S07/LPA7 S06/LPA6 S05/LPA5 S04/LPA4 S03/LPA3 S02/LPA2 S01/LPA1 S00/LPA0 COM3/LPL3 COM2/LPL2 COM1/LPL1 COM0/LPL0 V3 V2 V1 VDC Top view QIP64E (14×14) “Lead-and-halogen-free product” TQFP64J (7×7) “Lead-and-halogen-free product” SQFP64 (10×10) “Lead-and-halogen-free product” No.A1841-8/30 LC87F7932B PIN No. NAME PIN NO. NAME 1 P70/INT0/T0LCP/AN5 33 S08/LPB0 2 P71/INT1/T0HCP/AN6 34 S09/LPB1 3 P72/INT2/T0IN/NKIN 35 S10/LPB2 4 P73/INT3/T0IN 36 S11/LPB3 5 VDD2 37 S12/LPB4 6 VSS2 38 S13/LPB5 7 P10/SO0/S24 39 S14/LPB6 8 P11/SI0/SB0/S25 40 S15/LPB7 9 P12/SCK0/S26 41 S16/LPC0 10 P13/SO1/S27 42 S17/LPC1 11 P14/SI1/SB1/S28 43 S18/LPC2 12 P15/SCK1/S29 44 S19/LPC3 13 P16/T1PWML/S30 45 S20/LPC4 14 P17/T1PWMH/BUZ/S31 46 S21/LPC5 15 CUP1 47 S22/LPC6 16 CUP2 48 S23/LPC7 17 VDC 49 RES 18 V1 50 XT1 19 V2 51 XT2 20 V3 52 VSS1 21 COM0/LPL0 53 CF1 22 COM1/LPL1 54 CF2 23 COM2/LPL2 55 VDD1 24 COM3/LPL3 56 P00/UTX1/AN0 25 S00/LPA0 57 P01/RTX1/AN1 26 S01/LPA1 58 P02/AN2 27 S02/LPA2 59 P03/AN3 28 S03/LPA3 60 P04/CKO/AN4 29 S04/LPA4 61 P05/DBGP0 30 S05/LPA5 62 P06/T6O/DBGP1 31 S06/LPA6 63 P07/T7O/DBGP2 32 S07/LPA7 64 P30 No.A1841-9/30 LC87F7932B System Block Diagram Interrupt Control IR Standby Control PLA Flash ROM VMRC Clock Generator CF Highspeed RC Low-speed RC PC X’tal ACC WDT Reset Circuit Reset Control RES B Register C Register (POR) Bus Interface ALU SIO0 Port 0 SIO1 Port 1 Timer 0 Port 3 Timer 1 Port 7 Base Timer UART1 LCD Controller ADC INT0 to 3 Noise Filter RTC PSW RAR RAM Stack Pointer Watchdog Timer On-chip Debugger Timer 4 Timer 6 Timer 5 Timer 7 No.A1841-10/30 LC87F7932B Pin Description Pin Name I/O Description Option VSS1, VSS2 - • Power supply (-) No VDD1, VDD2, V2 - • Power supply (+) No VDC - • Internal power supply No CUP1, CUP2 Port 0 I/O P00 to P07 • Capacitor connecting pins for step-up/step-down circuits No • 8-bit I/O port Yes • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • HOLD release input • Port 0 interrupt input • Multiplexed functions P00: UART1 transmit data output P01: UART1 receive data input P04: System clock output P05: DBGP0 (LC87F7932B) P06: Timer 6 toggle output/DBGP1 (LC87F7932B) P07: Timer 7 toggle output/DBGP2 (LC87F7932B) AD converter input ports: AN0 (P00) to AN4 (P04) Port 1 I/O • 8-bit I/O port Yes P10/S24 to • I/O can be specified in 1-bit units. P17/S31 • Pull-up resistors can be turned on and off in 1-bit units. • Multiplexed functions P10: SIO0 data output P11: SIO0 data input or bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input or bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output/buzzer output Segment output for LCD: S24 (P10) to S31 (S17) Port 3 I/O P30 •1-bit I/O port Yes • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. Port 7 P70 to P73 I/O No • 4-bit I/O port • I/O can be specified in 1-bit units. • Pull-up resistors can be turned on and off in 1-bit units. • Multiplexed functions P70: INT0 input/HOLD release input/timer 0L capture input/output for watchdog timer P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/high-speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input AD converter input ports: AN5 (P70), AN6 (P71) Interrupt acknowledge type Rising Falling Rising and falling H level L level INT0 Enable Enable Disable Enable Enable INT1 Enable Enable Disable Enable Enable INT2 Enable Enable Enable Disable Disable INT3 Enable Enable Enable Disable Disable Continued on next page. No.A1841-11/30 LC87F7932B Continued from preceding page. Pin name S00/LPA0 to I/O I/O S07/LPA7 S08/LPB0 to I/O I/O No • Segment output for LCD No • Segment output for LCD No • Can be used as general purpose I/O ports (LPC) I/O COM3/LPL3 V1 to V3 • Segment output for LCD • Can be used as general purpose I/O ports (LPB) S23/LPC7 COM0/LPL0 to Option • Can be used as general purpose I/O ports (LPA) S15/LPB7 S16/LPC0 to Description • Common output for LCD No • Can be used as general purpose I/O ports (LPL) I/O RES I XT1 I/O • LCD drive bias power supply No • Reset pin No • 32.768kHz crystal resonator input pin No • General purpose input port • Must be connected to VDD1 if not to be used. XT2 I/O • 32.768kHz crystal resonator output pin No • General purpose I/O port • Must be set for oscillation and kept open if not to be used. CF1 I • Ceramic resonator input pin No • Must be connected to VDD1 if not to be used. CF2 O • Ceramic resonator output pin No • Must be kept open if not to be used. Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in output mode. Options Selected in Option Units of Type P00 to P07 1 bit 1 P10 to P17 1 bit Port Output Type Pull-up Resistor CMOS Programmable 2 N-channel open drain Programmable 1 CMOS Programmable 2 N-channel open drain Programmable P30 1 bit 1 CMOS Programmable 2 N-channel open drain Programmable P70 - No N-channel open drain Programmable P71 to P73 - No CMOS Programmable S00/LPA0 to - No CMOS No S23/LPC7 P-channel open drain N-channel open drain COM0/LPL0 to - No COM3/LPL3 CMOS No P-channel open drain N-channel open drain XT1 - No Input only No XT2 - No 32.768kHz crystal resonator output No N-channel open drain when selected as a generalpurpose output port No.A1841-12/30 LC87F7932B User Option Table Option Name Port output type Option to be Mask Version Flash-ROM Option Selected Applied on *1 Version in Units of 1 bit 1 bit P00 to P07 P10 to P17 P30 Option Selection CMOS N-channel open drain CMOS N-channel open drain CMOS 1 bit N-channel open drain Base timer Watchdog timer 1 second watchdog timer detection period 2 seconds - 4 seconds 8 seconds Program start address - 00000h *2 - 07E00h *1: Mask option selection. No change possible after mask is completed. *2: Program start address of the mask version is 00000h. *Note 1: Connect the IC as shown below to minimize noise on the VDD1. Be sure to electrically short the VSS1 and VSS2. *Note 2: The power to retain the internal memory is supplied via the V2 pin. VDD1, VDD2 and V2 are used as power supply for ports. If VDD1 and VDD2 are not backed up, the output does not go high even if a high level is applied to the port latch. Therefore, if VDD1 and VDD2 are not backed up, the high level output becomes unstable in HOLD mode, and the backup time becomes shorter because a through-current flows from VDD to GND in the input buffer. If VDD1 and VDD2 are not backed up, configure the program or set up the external circuit so that the output is held at a low level in HOLD mode to prevent an unnecessary through-current from flowing. For back up IC VDD1 Power supply VDD2 V1 V2 V3 CUP1 VDC CUP2 VSS1 VSS2 No.A1841-13/30 LC87F7932B Circuit Example (1)1/3 bias, 1/4 duty I/O I/O I/O I/O S23 S00 2 4SEG×4C OM COM3 COM0 LCD pan el C1 CUP1 CUP2 P00 P01 P02 P03 P04 P05 P06 P07 C2 C3 VDC V1 LC87F7932B C4 V2 V3 P10 P11 P12 P13 P14 P15 P16 P17 C5 2.4V to 3.6V VDD1 VDD2 RRES + CDEN RES P70 P71 P72 P73 CRES VSS1 VSS2 CF CDC XT1 XT2 CF1 CF2 P30 *1: Crystal oscillator *2: Ceramic oscillator X'tal CGC *2 CDX CGX *1 X'tal Crystal resonator Refer to Page 26 CGX Trimmer capacitor (Characteristics of a sample clock oscillator CDX Capacitor for crystal oscillator circuit) CF Ceramic resonator Refer to Page 26 CGC Capacitor for ceramic oscillator (Characteristics of a sample clock oscillator CDC Capacitor for ceramic oscillator circuit) C1 to C5 Capacitors 0.1μF (recommended) CDEN Electrolytic capacitor For back up CRES Capacitor for RES Refer to User’s manual “Reset Function” RRES Resistor for RES No.A1841-14/30 LC87F7932B (2)1/2 bias, 1/3 duty I/O I/O I/O I/O P00 P01 P02 P03 P04 P05 P06 P07 S23 S00 2 4SEG×3C OM COM2 COM0 LCD pan el CUP1 CUP2 VDC V1 LC87F7932B V2 V3 P10 P11 P12 P13 P14 P15 P16 P17 C1 C2 C3 C4 2.4V to 3.6V VDD1 VDD2 RRES + CDEN RES P70 P71 P72 P73 CRES VSS1 VSS2 CF CDC XT1 XT2 CF1 CF2 P30 *1: Crystal oscillator *2: Ceramic oscillator X'tal CGC *2 CDX CGX *1 X'tal Crystal resonator Refer to Page 26 CGX Trimmer capacitor (Characteristics of a sample clock oscillator CDX Capacitor for crystal oscillator circuit) CF Ceramic resonator Refer to Page 26 CGC Capacitor for ceramic oscillator (Characteristics of a sample clock oscillator CDC Capacitor for ceramic oscillator circuit) C1 to C4 Capacitors 0.1μF (recommended) CDEN Electrolytic capacitor For back up CRES Capacitor for RES Refer to User’s manual “Reset Function” RRES Resistor for RES No.A1841-15/30 LC87F7932B Absolute Maximum Ratings at Ta=25°C and VSS1=VSS2=0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply VDD max VDD1, VDD2, V2 VDD1=VDD2=V2 voltage Supply voltage VLCD for LCD typ max unit -0.3 +4.3 V1 -0.3 1/2VDD V2 -0.3 VDD V3 -0.3 2/3VDD -0.3 VDD+0.3 -0.3 VDD+0.3 Input voltage VI XT1, CF1, RES Input/output VIO(1) Ports 0, 1, 3, 7 voltage min LPA, LPB, LPC V LPL, XT2 Peak IOPH(1) Ports 0, 1 output High level output current current • CMOS output selected • Current at each pin IOPH(2) Port 3 • CMOS output selected IOPH(3) LPA, LPB, LPC • CMOS output selected LPL • Current at each pin -20 -4 IOPH(4) P71 to P73 • Current at each pin Total IOAH(1) Port 0 Total of all pins -20 output IOAH(2) Ports 3, 7 Total of all pins -30 current IOAH(3) Port 1 Total of all pins -20 IOAH(4) Ports 1, 3, 7 Total of all pins -45 IOAH(5) LPA, LPB, LPC, Total of all pins LPL Low level output current -10 -5 -30 mA Peak IOPL(1) Ports 0, 1 Current at each pin 20 output IOPL(2) Port 3 Current at each pin 30 IOPL(3) Port 7 Current at each pin 10 IOPL(4) LPA, LPB, LPC, Current at each pin current 6 LPL Total IOAL(1) Port 0 Total of all pins 40 output IOAL(2) Ports 3, 7 Total of all pins 50 current IOAL(3) Port 1 Total of all pins 40 IOAL(4) Ports 1, 3, 7 Total of all pins 65 IOAL(5) LPA, LPB, LPC, Total of all pins 60 LPL Allowable power Pd max dissipation Operating QIP64E (14×14) Ta = -40°C to +85°C 267 TQFP64J (7×7) 152 SQFP64 (10×10) 192 Topr temperature -40 85 range Storage temperature mW °C Tstg -55 125 range Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A1841-16/30 LC87F7932B Allowable Operating Conditions at Ta=-40°C to +85°C, VSS1=VSS2=0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Operating supply VDD(1) VDD1=VDD2=V2 voltage min typ max unit 0.75μs≤tCYC≤200μs Normal mode 2.4 3.6 2.2 3.6 (Note 2-1) Memory VHD VDD1=VDD2=V2 sustaining RAM and register contents sustained in HOLD mode. supply voltage High level input VIH(1) voltage Ports 0, 3 Output disabled LPA, LPB, LPC, LPL VIH(2) Port 1 • Output disabled P71 to 73 • When INT1VTSL=0 P70 port input (P71 only) 2.4 to 3.6 2.4 to 3.6 0.3VDD VDD +0.7 0.3VDD +0.7 VDD 2.4 to 3.6 0.85VDD VDD 2.4 to 3.6 0.9VDD VDD 2.4 to 3.6 0.75VDD VDD 2.4 to 3.6 VSS 0.2VDD 2.4 to 3.6 VSS 0.2VDD 2.4 to 3.6 VSS 0.45VDD 2.4 to 3.6 VSS 2.4 to 3.6 VSS / interrupt side VIH(3) P71 interrupt side • Output disabled • When INT1VTSL=1 VIH(4) P70 watchdog timer Output disabled side Low level input VIH(5) XT1, XT2, CF1, RES VIL(1) Ports 0, 3 voltage Output disabled LPA, LPB, LPC, LPL VIL(2) Port 1 • Output disabled P71 to 73 • When INT1VTSL=0 P70 port input (P71 only) V / interrupt side VIL(3) P71 interrupt side • Output disabled • When INT1VTSL=1 VIL(4) P70 watchdog timer Output disabled side VIL(5) Instruction cycle XT1, XT2, CF1, RES 0.8VDD -1.0 0.25VDD tCYC time 2.4 to 3.6 200 μs (Note 2-2) External system FEXCF(1) CF1 clock frequency • CF2 pin open • System clock frequency division ratio = 1/1 2.4 to 3.6 0.1 4 • External system clock MHz duty = 50±5% • CF2 pin open • System clock frequency 2.4 to 3.6 0.2 8 division ratio = 1/2 Oscillation FmCF(1) CF1, CF2 frequency range (Note 2-3) • 4MHz ceramic oscillation • See Fig. 1. FmRC(1) Internal high-speed RC oscillation FsRC(1) Internal low-speed RC oscillation FsX’tal XT1, XT2 2.4 to 3.6 4 MHz 2.4 to 3.6 250 500 750 2.4 to 3.6 25 50 75 kHz • 32.768kHz crystal oscillation 2.4 to 3.6 32.768 • See Fig. 2. VMRC oscillation usable range VMRC oscillation OpVMRC(1) When VMSL4M=0 3.0 to 3.6 8 10 12 OpVMRC(2) When VMSL4M=1 2.4 to 3.6 3.5 4 4.5 2.4 to 3.6 8 24 64 VmADJ(1) Each step of VMRAJn (Wide range) adjustment MHz % range VmADJ(2) Each step of VMFAJn (Small range) 2.4 to 3.6 1 4 8 Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. No.A1841-17/30 LC87F7932B Electrical Characteristics at Ta=-40°C to +85°C, VSS1=VSS2=0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) current Ports 0, 1, 3, 7 • Output disabled LPA, LPB, LPC • Pull-up resistor off LPL • VIN=VDD min typ max unit 2.4 to 3.6 1 2.4 to 3.6 1 2.4 to 3.6 1 2.4 to 3.6 15 (Including output Tr's off leakage current) IIH(2) RES VIN=VDD IIH(3) XT1, XT2 • Input port specification • VIN=VDD Low level input IIH(4) CF1 VIN=VDD IIL(1) Ports 0, 1, 3, 7 • Output disabled LPA, LPB, LPC • Pull-up resistor off LPL • VIN=VSS current 2.4 to 3.6 -1 2.4 to 3.6 -1 2.4 to 3.6 -1 μA (Including output Tr's off leakage current) IIL(2) RES VIN=VSS IIL(3) XT1, XT2 • Input port specification • VIN=VSS IIL(4) CF1 VIN=VSS 2.4 to 3.6 -15 High level output VOH(1) CMOS output ports IOH=-0.4mA 3.0 to 3.6 VDD-0.4 voltage VOH(2) 0, 1 IOH=-0.2mA 2.4 to 3.6 VDD-0.4 VOH(3) CMOS output port 3 IOH=-1.6mA 3.0 to 3.6 VDD-0.4 IOH=-1mA 2.4 to 3.6 VDD-0.4 IOH=-0.4mA 3.0 to 3.6 VDD-0.4 IOH=-0.2mA 2.4 to 3.6 VDD-0.4 IOH=-0.1mA 2.4 to 3.6 VDD-0.4 VOH(4) VOH(5) P71 to 73 VOH(6) VOH(7) LPA, LPB, LPC LPL Low level output VOL(1) voltage VOL(2) VOL(3) Ports 0, 1 Port 3 VOL(4) IOL=1.6mA 3.0 to 3.6 0.4 IOL=1mA 2.4 to 3.6 0.4 IOL=5mA 3.0 to 3.6 0.4 IOL=2.5mA 2.4 to 3.6 0.4 VOL(5) Port 7 IOL=1.6mA 3.0 to 3.6 0.4 VOL(6) XT2 IOL=1mA 2.4 to 3.6 0.4 VOL(7) LPA, LPB, LPC IOL=0.1mA 2.4 to 3.6 0.4 LPL LCD output voltage VODLS S00 to S31 deviation • IO=0mA • V1, V2, V3 LCD level output 2.4 to 3.6 0 ±0.2 2.4 to 3.6 0 ±0.2 2.4 to 3.6 18 V • See Fig. 8. VODLC COM0 to COM3 • IO=0mA • V1, V2, V3 LCD level output • See Fig. 8. Pull-up resistance Rpu(1) Ports 0, 1, 3, 7 Hysterisis voltage VHYS(1) Ports 1, 7 RES Pin capacitance CP All pins VOH=0.9VDD 50 150 kΩ 2.4 to 3.6 0.1VDD V 2.4 to 3.6 10 pF • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C No.A1841-18/30 LC87F7932B Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. Input clock tSCKH(1) pulse width tSCKHA(1) typ max unit 2 1 pulse width High level min 1 • Continuous data 2.4 to 3.6 tCYC transmission/reception mode 4 Serial clock • See Fig. 6. • (Note 4-1-2) Frequency tSCK(2) Low level tSCKL(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. 1/2 Output clock pulse width High level tSCK tSCKH(2) 1/2 pulse width 2.4 to 3.6 tSCKHA(2) • Continuous data transmission/reception tSCKH(2) mode +2tCYC • CMOS output selected tSCKH(2) +(10/3) tCYC tCYC • See Fig. 6. Serial input Data setup time SB0(P11), SI0(P11) • Must be specified with respect to the rising edge of SIOCLK. Data hold time 0.03 2.4 to 3.6 • See Fig. 6. thDI(1) 0.03 Input clock Output delay tdDO(1) time SO0(P10), SB0(P11) • Continuous data (1/3)tCYC transmission/reception +0.05 mode μs • (Note 4-1-3) tdDO(2) • Synchronous 8-bit mode • (Note 4-1-3) Output clock Serial output tsDI(1) tdDO(3) 1tCYC 2.4 to 3.6 +0.05 (Note 4-1-3) (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Be sure to add margin depending on its use. Note 4-1-2: In an application where the serial clock input is to be used in continuous data transmission/reception mode, the time from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to the falling edge of SIOCLK. Must be specified as the time up to the beginning of output state change in open drain output mode. See Fig. 6. No.A1841-19/30 LC87F7932B 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions Input clock Frequency tSCK(3) Low level tSCKL(3) SCK1(P15) See Fig. 6. 2.4 to 3.6 pulse width High level tSCK(4) Low level tSCKL(4) typ 1 SCK1(P15) • CMOS output selected 2 • See Fig. 6. 1/2 2.4 to 3.6 tSCK tSCKH(4) 1/2 pulse width tsDI(2) Serial input Data setup time SB1(P14), SI1(P14) • Must be specified with respect to the rising edge of SIOCLK. Data hold time unit 1 pulse width High level max tCYC tSCKH(3) Frequency min 2 pulse width Output clock Serial clock VDD[V] • See Fig. 6. thDI(2) 0.03 2.4 to 3.6 0.03 Output delay time tdDO(4) SO1(P13), Serial output SB1(P14) • Must be specified with μs respect to the falling edge of SIOCLK. • Must be specified as the time up to the beginning (1/3)tCYC 2.4 to 3.6 +0.05 of output state change in open drain output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Be sure to add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 INT2(P72) INT3(P73) when • Interrupt source flag can be set. tPIL(2) noise filter time • Event inputs for timer 0 are INT3(P73) when • Interrupt source flag can be set. tPIL(3) noise filter time • Event inputs for timer 0 are INT3(P73) when • Interrupt source flag can be set. tPIL(4) noise filter time • Event inputs for timer 0 are tPIL(5) RES 1 2.4 to 3.6 2 max unit tCYC 2.4 to 3.6 64 2.4 to 3.6 256 2.4 to 3.6 200 enabled. tPIH(4) constant is 1/128 2.4 to 3.6 enabled. tPIH(3) constant is 1/32 typ are enabled. tPIH(2) constant is 1/1 min enabled. Resetting is enabled. μs No.A1841-20/30 LC87F7932B AD Converter Characteristics at VSS1 = VSS2 = 0V <12-bit AD Conversion Mode at Ta=-40°C to +85°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0 (P00) to Absolute ET AN4 (P04), Conversion time 3.0 to 3.6 (Note 6-1) AN6 (P71) TCAD typ max unit 12 3.0 to 3.6 AN5 (P70) to accuracy min bit ±16 LSB • See conversion time calculation formulas. 3.0 to 3.6 64 115 μs 3.0 to 3.6 VSS VDD V (Note 6-2) Analog input VAIN voltage range Analog port input IAINH VAIN=VDD 3.0 to 3.6 current IAINL VAIN=VSS 3.0 to 3.6 1 -1 μA <8-bit AD Conversion Mode at Ta=-40°C to +85°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0(P00) to Absolute ET AN4(P04), Conversion time 3.0 to 3.6 (Note 6-1) AN6(P71) TCAD typ max Unit 8 bit ±1.5 3.0 to 3.6 AN5(P70) to accuracy min LSB • See conversion time calculation formulas. 3.0 to 3.6 40 90 μs 3.0 to 3.6 VSS VDD V (Note 6-2) Analog input VAIN voltage range Analog port input IAINH VAIN=VDD 3.0 to 3.6 current IAINL VAIN=VSS 3.0 to 3.6 1 -1 μA Conversion Time Calculation Formulas: 12-bit AD conversion mode: TCAD (conversion time) = ((52/(AD division ratio)) + 2) × (1/3) × tCYC 8-bit AD conversion mode: TCAD (conversion time) = ((32/(AD division ratio)) + 2) × (1/3) × tCYC <Recommended Operating Conditions> External Oscillator Supply Voltage Range (FmCF) (VDD) CF-4MHz 3.0V to 3.6V System Clock Division Ratio (SYSDIV) 1/1 Cycle Time (tCYC) 750ns AD Frequency Conversion Time (TCAD) Division Ratio (ADDIV) 12-bit AD 8-bit AD 1/8 104.5μs 64.5μs Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process is executed until the time the conversion result register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is doubled in the following cases: • The first AD conversion is performed in the 12 bits AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8 bits to 12 bits conversion mode. No.A1841-21/30 LC87F7932B Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Current IDDOP(1) consumption in VDD1=VDD2 =V2 min typ max unit • FmCF=4MHz ceramic oscillation • FsX’tal=32.768kHz crystal oscillation normal operating • System clock set to 4MHz side mode • Internal RC oscillation stopped (Note 7-1) • VMRC oscillation stopped 2.4 to 3.6 2.0 4.2 2.4 to 3.6 250 900 mA • 1/1 frequency division ratio IDDOP(2) • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to high-speed internal RC oscillation • VMRC oscillation stopped • 1/1 frequency division ratio IDDOP(3) μA • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to low-speed internal RC oscillation 2.4 to 3.6 30 120 2.4 to 3.6 2.0 5.4 2.4 to 3.6 250 900 2.4 to 3.6 20 86 2.4 to 3.6 15 72 • VMRC oscillation stopped • 1/1 frequency division ratio IDDOP(4) • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped • System clock set to 4MHz VMRC mA oscillation • 1/1 frequency division ratio IDDOP(5) • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped • System clock set to 500kHz VMRC oscillation •1/1 frequency division ratio IDDOP(6) • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to 32.768kHz side • Internal RC oscillation stopped • VMRC oscillation stopped μA • 1/1 frequency division ratio • Normal XT amp mode IDDOP(7) • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to 32.768kHz side • Internal RC oscillation stopped • VMRC oscillation stopped •1/1 frequency division ratio • Low consumption XT amp mode Note 7-1: The consumption current value does not include current that flows into the output transistors and internal pull-up resistors. Continued on next page. No.A1841-22/30 LC87F7932B Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Current IDDHALT(1) consumption VDD1=VDD2 =V2 min typ max unit HALT mode • FmCF=4MHz ceramic oscillation in HALT mode • FsX’tal=32.768kHz crystal oscillation (Note 7-1) • System clock set to 4MHz side 2.4 to 3.6 0.55 1.55 2.4 to 3.6 68 280 2.4 to 3.6 7 85 2.4 to 3.6 650 1460 mA • Internal RC oscillation stopped • VMRC oscillation stopped • 1/1 frequency division ratio IDDHALT(2) HALT mode • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to high-speed internal RC oscillation • VMRC oscillation stopped • 1/1 frequency division ratio IDDHALT(3) HALT mode • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to low-speed internal RC oscillation • VMRC oscillation stopped • 1/1 frequency division ratio IDDHALT(4) HALT mode • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped • System clock set to 4MHz VMRC oscillation • 1/1 frequency division ratio IDDHALT(5) HALT mode μA • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped 2.4 to 3.6 68 280 2.4 to 3.6 8 70 2.4 to 3.6 4 50 • System clock set to VMRC oscillation (500kHz) • 1/1 frequency division ratio IDDHALT(6) HALT mode • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to 32.768kHz side • Internal RC oscillation stopped. • VMRC oscillation stopped •1/1 frequency division ratio • Normal XT amp mode IDDHALT(7) HALT mode • FmCF=0Hz (Oscillation stopped) • FsX’tal=32.768kHz crystal oscillation • System clock set to 32.768kHz side • Internal RC oscillation stopped. • VMRC oscillation stopped • 1/1 frequency division ratio • Low consumption XT amp mode Note 7-1: The consumption current value does not include current that flows into the output transistors and internal pull-up resistors. Continued on next page. No.A1841-23/30 LC87F7932B Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Current IDDHOLD(1) consumption in VDD1=VDD2 =V2 HOLD mode Current min typ max unit HOLD mode • CF1=VDD or open 2.4 to 3.6 0.05 30 2.4 to 3.6 6.5 67 (When using external clock) IDDHOLD(2) consumption in time-of-day clock VDD1=VDD2 =V2 Time-of-day clock HOLD mode • CF1=VDD or open (When using external clock) HOLD mode • FsX’tal=32.768kHz crystal oscillation • 1/1 frequency division ratio • LCD display off • Normal XT amp mode IDDHOLD(3) Time-of-day clock HOLD mode μA • CF1=VDD or open (When using external clock) • FsX’tal=32.768kHz crystal oscillation 2.4 to 3.6 0.45 46 2.4 to 3.6 1.5 70 • 1/1 frequency division ratio • LCD display off • Low consumption XT amp mode IDDHOLD(4) Time-of-day clock HOLD mode • CF1=VDD or open (When using external clock) • FsX’tal=low-speed RC oscillation • 1/1 frequency division ratio • LCD display off No.A1841-24/30 LC87F7932B F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Onboard IDDFW(1) VDD1 programming min typ max unit • Excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 mA 20 30 ms 45 60 μs current Programming tFW(1) • Erasing operation time tFW(2) • Programming operation 3.0 to 5.5 UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Transfer rate UBR UTX (P00), 2.4 to 3.6 URX (P01) Data length: Stop bits : Parity bits: min typ 16/3 max unit 8192/3 tCYC 7/8/9 bits (LSB first) 1 bit (2 bits in continuous data transmission) None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Stop bit End of transmission Transmit data (LSB first) UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Start bit Start of reception Stop bit Receive data (LSB first) End of reception UBR No.A1841-25/30 LC87F7932B Characteristics of a Sample Main System Clock Oscillator Circuit Given below are the characteristics of a sample main system clock oscillator circuit, which are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with normal and stable oscillation confirmed by the resonator vendor. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Nominal Vendor Frequency Name 4.00MHz Circuit Constant Resonator Name Operating Oscillation Voltage Stabilization Time C1 C2 Rf1 Rd1 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] Remarks CSTCR4M00G53-R0 (15) (15) Open 1k 2.4 to 3.6 0.03 0.15 Internal CSTLS4M00G53-B0 (15) (15) Open 1k 2.4 to 3.6 0.02 0.15 C1, C2 Murata The oscillation stabilization time is the period required for the resonator to stabilize in the following situations. (See Figure 4) • After VDD goes above the operating voltage lower limit until the oscillation is stabilized. • After the instruction for starting the main clock oscillation circuit is executed until the oscillation is stabilized. • After HOLD mode is released until the oscillation is stabilized. • After HOLD mode is released and oscillation is started with CFSTOP (OCR register, bit0) set to 0 until the oscillation is stabilized. Characteristics of a Sample Sub-system Clock Oscillator Circuit Given below are the characteristics of a sample sub-system clock oscillator circuit, which are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with normal and stable oscillation confirmed by the resonator vendor. (Different evaluation boards are used for Tables 2 and 3.) Table 2 Characteristics of a Sample Sub-system Clock Oscillator Circuit with a Crystal Resonator 1 Nominal Vendor Frequency Name 32.768KHz Circuit Constant Resonator Name Epson Toyocom Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 9 9 Open 330k 2.4 to 3.6 1 3 Remarks CL=7.0pF Normal amp CL=7.0pF MC-306 3 3 Open 0 2.4 to 3.6 2 Low 6 consumption amp Table 3 Characteristics of a Sample Sub-system Clock Oscillator Circuit with a Crystal Resonator 2 (*5) Nominal Frequency Vendor Name Name SSP-T7-F 32.768kHz (*1) Seiko Instruments (*2) Circuit Constant Resonator Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 22 22 Open 820k 2.4 to 3.6 1.8 3 Remarks CL=12.5pF (*3) VT-200-F Normal amp SSP-T7-FL CL=6.0pF (*4) 7 VT-200-FL 6 Open 0 2.4 to 3.6 0.9 3 Low consumption amp (*1) Normal XT amplifier mode (*3) or low consumption amplifier mode (*4) should be selected for the sub-system clock oscillator circuit. (*2) Contact Seiko Instruments, Inc., (http://www.sii-crystal.com) for further information about the use of the resonator. (*3) When considering the use of normal XT amplifier mode, use an resonator that has a large load capacitance. (*4) When considering the use of low consumption XT amplifier mode, use a resonator that has a small load capacitance. The applicable CL value of 6.0pF makes it possible to achieve a high time accuracy for the subclock oscillator as well as high-speed oscillation startup and low power dissipation. In addition to this value, 7.0pF and 9.0pF also fall within the applicable CL value range. No.A1841-26/30 LC87F7932B (*5) A sample PCB trace pattern for a Seiko Instrument resonator is shown below. (Note 1) The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations (see Figure 4): • After the instruction for starting the subclock oscillator circuit is executed until the oscillation is stabilized. • After HOLD mode is released and oscillation is started with EXTOSC (OCR register, bit 6) set to 1 until the oscillation is stabilized. (Note 2) The circuit constants shown are the reference values that are provided by the resonator vendor for evaluation. To make final verification of the oscillation characteristics on production boards, call the resonator vendor for evaluation on printed circuit boards. (Note 3) When using an oscillator circuit, observe the following wiring precautions to avoid the possible adverse influence of wiring capacitance, especially in low consumption XT amplifier mode: • Place the components that are involved in oscillation as close to the resonator as possible with the shortest possible traces as the oscillation characteristics are subject to the variation of trace patterns. • Do not take a signal directly from the oscillator circuit. • Do not place the oscillator circuit in the vicinity of any lines that carry large current. • Exercise extreme care in the wiring method when using low consumption XT amplifier mode. CF2 CF1 Rf1 Rf2 Rd1 C1 XT2 XT1 C2 C3 Rd2 C4 CF X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1841-27/30 LC87F7932B VDD VDD lower limit Power supply 0V Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Execute oscillation enable command Operating mode Reset Unfixed Instruction execution mode Reset Time and Oscillation Stabilization Time HOLD release signal Without HOLD release HOLD release signal VALID Internal RC oscillation tmsCF CF1, CF2 (Note ) tmsX’tal XT1, XT2 (Note ) Operation mode HOLD HALT HOLD Release Signal and Oscillation Stabilization Time Note: Oscillation is enabled before HOLD mode is entered. Figure 4 Oscillation Stabilization Time No.A1841-28/30 LC87F7932B VDD Note: External circuits for reset may vary depending on the usage of POR. Please refer to the user’s manual on reset function. RRES RES CRES Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKH tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial Input/Output Waveform tPIL tPIH Figure 7 Pulse Input Timing Waveform No.A1841-29/30 LC87F7932B (a) POR release voltage (PORRL) (b) VDD Reset period 1000μs or longer Reset period Reset undefined region RES Figure 8 Sample Operating Waveforms when POR is Used (Reset pin: Pull-up resistor RRES only) • The POR function generates a reset only when power is turned on starting at the VSS level. • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 1000μs or longer. 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