Ordering number : ENA0653 LC87F7032A CMOS IC FROM 32K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller Overview The LC87F7032A is an 8-bit single chip microcontroller with the following on-chip functional blocks: • CPU: operable at a minimum bus cycle time of 250ns • 32K bytes Flash ROM • On-chip ΡΑΜ: 1024 bytes • LCD controller/driver • 16bit timer × 2ch + 8bit timer × 1ch or more • Synchronous serial I/O port (with automatic block transmit/receive function) • Asynchronous/synchronous serial I/O port • System clock divider • 20-source 10-vectored interrupt system • 8-bit AD converter × 9-channel • On chip debugger All of the above functions are fabricated on a single chip. Features Flash ROM • Block-erasable in 128byte units • 32768 × 8 bits (LC87F7032A) RAM • 1024 × 9-bits (LC87F7032A) * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 20707HKIM 20061204-S00007 No.A0653-1/21 LC87F7032A Minimum Bus Cycle Time • 250ns (4MHz) Note: Bus cycle time indicates the speed to read ROM. Minimum Instruction Cycle Time (tCYC) • 750ns (4MHz) Ports • Input/output ports Data direction programmable for each bit individually 12 (P1n, P70 to P73) Data direction programmable in nibble units 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) Other function 3 (DBGP0, DBGP1, DBGP2) • PWM input/output port1 (PWM) • LCD ports Segment output 24 (S00 to S23) Common output 4 (COM0 to COM3) Bias terminals for LCD driver 5 (V1 to V3, CUP1, CUP2) Other functions Input/output ports 8 (PCn) • Oscillator pins 4 (CF1, CF2, XT1, XT2) • Reset pin 1 (RES) • Power supply 4 (VSS1 to 2,VDD1 to 2) 1 (VDC) LCD Controller • Seven display modes are available • Duty 1/3duty, 1/4duty • Bias 1/2bias, 1/3bias • Segment output can be switched to general purpose input/output ports. Timers • Timer 0: 16-bit timer/counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register • Timer1: PWM/16 bit timer/counter with toggle output function Mode 0: 2 channel 8 bit timer/counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/counter (with toggle output) toggle output from lower 8 bits is also possible. Mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as PWM. • Timer4: 8-bit timer with 6-bit prescaler • Timer5: 8-bit timer with 6-bit prescaler • Timer6: 8-bit timer with 6-bit prescaler (with toggle output) • Timer7: 8-bit timer with 6-bit prescaler (with toggle output) • Base Timer 1) The clock signal can be selected from any of the following: Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts of five different time intervals are possible. No.A0653-2/21 LC87F7032A SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first is selectable 2) Internal 8 bit baud-rate generator (fastest clock period 4/3 tCYC) 3) Consecutive automatic data communication (1 to 256 bits) • SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) UART • Full duplex • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator AD Converter • 8-bit × 9-channels PWM • Multifrequency 12-bit PWM × 1-channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) • Noise rejection function (noise rejection filter’s time constant can be selected from 1/32/128 tCYC) Watchdog Timer • Watchdog timer can produce interrupt or system reset. • Watchdog timer has two types. Use an external RC circuit Use the microcontroller’s basetimer Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. Interrupts • 20 sources, 10 vector addresses 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART-send 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/T4/T5/PWM • Priority levels X > H > L • For equal priority levels, vector with lowest address takes precedence. No.A0653-3/21 LC87F7032A Subroutine Stack Levels • 512 levels maximum (the stack is allocated in RAM) High-speed Multiplication/Division Instructions • 16-bits × 8-bits (5 tCYC execution time) • 24-bits × 16-bits (12 tCYC execution time) • 16-bits ÷ 8-bits (8 tCYC execution time) • 24-bits ÷ 16-bits (12 tCYC execution time) Oscillation Circuits • On-chip RC oscillation for system clock use. • CF oscillation (4MHz) for system clock use. (Rf built in, Rd external) • Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in, Rd external) • On-chip frequency variable RC oscillation circuit for system clock use. System Clock Divider Function • Low power consumption operation is available • Minimum instruction cycle time (750ns, 1.5µs, 3.0µs, 6.0µs, 12µs, 24µs, 48µs, 96µs, 192µs can be switched by program (when using 4MHz main clock) Standby Function • HALT mode: HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1) Oscillation circuits are not stopped automatically. 2) Released by the system reset or interrupts. • HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. 1) CF, RC and crystal oscillation circuits stop automatically. 2) Released by any of the following conditions. (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2. (3) Port 0 interrupt • X'tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF and RC oscillation circuits stop automatically. 2) Crystal oscillator operation is kept in its state at HOLD mode inception. 3) Released by any of the following conditions (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2. (3) Port 0 interrupt (4) Base-timer interrupt ROM Correct Function • ROM correct program is executed by checking the program counter. • ROM correct program area: 128byte On-chip Debugger Function • Software debug is available on the target board. Package Form • ΤQFP64J(7×7) :Lead-free type • QIP64E(14×14) :Lead-free type Development Tool • On-chip Debugger: TCB87 TypeB+LC87F7032A No.A0653-4/21 LC87F7032A Flash ROM Programming boards Package Programming Boards TQFP64J(7×7) W87F70256TQ7 QIP64E(14×14) W87F70256Q Package Dimensions unit : mm (typ) 3289 9.0 33 32 64 17 7.0 49 1 9.0 48 0.5 7.0 16 0.4 0.125 0.16 0.1 1.2max (1.0) (0.5) SANYO : TQFP64J(7X7) Package Dimensions unit : mm (typ) 3159A 33 32 64 17 14.0 49 1 17.2 48 0.8 17.2 14.0 16 0.8 0.35 0.15 0.1 3.0max (2.7) (1.0) SANYO : QIP64E(14X14) No.A0653-5/21 LC87F7032A LC87F7032A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P70/INT0/T0LCP/AN5 P71/INT1/T0HCP/AN6 P72/INT2/T0IN/AN7 P73/INT3/T0IN/AN8 VDD2 VSS2 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH CUP1 CUP2 RES XT1 XT2 VSS1 CF1 CF2 VDD1 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/DBGP0 P06/DBGP1 P07/DBGP2 PWM 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 S23/PC7/RX S22/PC6/TX S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15 S14 S13 S12 S11 S10 S9 S8 Pin Assignment 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 S7 S6 S5 S4 S3 S2 S1 S0 COM3 COM2 COM1 COM0 V3 V2 V1 VDC Top view SANYO: TQFP64J(7×7) SANYO: QIP64E(14×14) “Lead-free Type” “Lead-free Type” No.A0653-6/21 LC87F7032A System Block Diagram Interrupt control IR PLA ROM Correct Stand-by control Flash ROM RC MRC Clock generator CF PC X’tal SIO0 Bus interface ACC SIO1 Port 0 B register Timer 0 (High-speed clock counter) Port 1 C register Timer 1 ALU Base timer Port 7 PSW LCD controller INT0 to 3 Noise rejection filter ADC RAR RAM Timer 4 Timer 5 Timer 6 Stack pointer UART Timer 7 Watchdog timer PWM On-chip debugger No.A0653-7/21 LC87F7032A Pin Description Pin name I/O Function Option VSS1,VSS2 - • Power supply (-) No VDD1,VDD2 - • Power supply (+) No VDC - • Power supply (+) No • Capacitor connecting terminals for step-up/step-down No CUP1,CUP2 - PWM I/O • PWM input/output port No PORT0 I/O • 8bit input/output port Yes P00 to P07 • Data direction programmable in nibble units • Use of pull-up resistor can be specified in nibble units • Input for HOLD release • Input for port 0 interrupt • Input for AD Converter: AN0(P00) to AN4(P04) • On chip debugger terminal (P05, P06, P07) PORT1 I/O P10 to P17 • 8bit input/output port Yes • Data direction programmable for each bit • Use of pull-up resistor can be specified for each bit individually • Other pin functions P10 SIO0 data output P11 SIO0 data input or bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input or bus input/output P15 SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/buzzer output PORT7 I/O P70 to P73 • 4bit Input/output port No • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit individually • Input for AD Converter (AN5 to AN8) • Other functions P70: INT0 input/HOLD release input/timer0L capture input/output for watchdog timer/AN5 P71: INT1 input/HOLD release input/timer0H capture input/AN6 P72: INT2 input/HOLD release input/timer 0 event input/timer0L capture input/AN7 P73: INT3 input (noise rejection filter attached)/timer 0 event input/timer0H capture input/AN8 • Interrupt detection selection Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising and H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable falling S0 to S15 O • Segment output for LCD No S16/PC0 to I/O • Segment output for LCD No S23/PC7 • Can be used as general purpose input/output port (PC) • UART terminal (S22, S23 ) COM0 to O • Common output for LCD No COM3 V1 to V3 • LCD output bias power supply No RES I/O I • Reset terminal No XT1 I • Input for 32.768kHz crystal oscillation No • When not in use, connect to VDD1 XT2 I/O • Output for 32.768kHz crystal oscillation No • When not in use, set to oscillation mode and leave open CF1 I • Input terminal for ceramic oscillator No • When not in use, connect to VDD1 CF2 O • Output terminal for ceramic oscillator No • When not in use, leave open No.A0653-8/21 LC87F7032A Port Output Configuration Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode. Terminal P00 to P07 Option applies to: Options each bit 1 CMOS Output Form Programmable Pull-up resistor 2 Nch-open drain None 1 CMOS Programmable 2 Nch-open drain Programmable Programmable (Note 1) P10 to P17 each bit P70 - None Nch-open drain P71 to P73 - None CMOS Programmable S16(PC0) to each bit 1 CMOS None S23(PC7) 2 P-ch Open Drain 3 N-ch Open Drain Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07). * 1: Connect as follows to reduce noise on VDD. VSS1 and VSS2 must be connected together and grounded. * 2: The power supply for the internal memory is VDD1. VDD1 and VDD2 are used as the power supply for ports. When VDD1 and VDD2 are not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore, when VDD1 and VDD2 are not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD1 and VDD2 are not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented. Back up capacitors LSI1 VDD1 Power supply VDD2 V1 V2 V3 CUP1 VDC CUP2 VSS1 VSS2 No.A0653-9/21 LC87F7032A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = 0V Parameter Symbol Pins Specification Conditions VDD[V] Supply voltage VDD max VDD1,VDD2,V2 Supply voltage VLCD For LCD VDD1=VDD2=V2 -0.3 1/2 VDD V2 -0.3 VDD V3 -0.3 3/2 VDD -0.3 VDD+0.3 -0.3 VDD+0.3 Input/Output voltage VIO(1) • Ports 0, 1, 7 Low level output current High level output current • Port C, PWM Total output Ports 0, 1, 7, C, • CMOS output selected PWM • Current at each pin ΣIOAH(1) Port 7, PWM Total of all pins ΣIOAH(2) Port 0 Total of all pins -25 ΣIOAH(3) Port 1 Total of all pins -25 ΣIOAH(4) Port C Total of all pins -15 IOPL(1) Ports 02 to 07 Current at each pin current Peak output current unit V1 XT1,CF1, RES current max +4.6 VI IOPH(1) typ -0.3 Input voltage Peak output min -4 -10 mA 6 Ports 1, 7, C, PWM IOPL(2) Ports 00, 01 Current at each pin 15 Total output ΣIOAL(1) Port 7, PWM Total of all pins 10 current ΣIOAL(2) Port 0 Total of all pins 35 ΣIOAL(3) Port 1 Total of all pins 25 ΣIOAL(4) Port C Total of all pins 15 Pd max TQFP64J(7×7) Ta=-20 to +70°C Allowable power dissipation Operating ambient Storage ambient temperature 185 QIP64E(14 ×14) Topr temperature Tstg V mW 410 -20 +70 -55 +125 °C No.A0653-10/21 LC87F7032A Recommended Operating Range at Ta = -20°C to +70°C, VSS1 = VSS2 = 0V Parameter Symbol Pins Specification Conditions VDD[V] Operating VDD(1) supply voltage VDD(2) VDD1=VDD2=V2 0.75µs≤tCYC≤200µs range Supply voltage 0.75µs≤tCYC≤200µs expect on-board write VHD VDD1 range in hold min typ max unit 3.0 3.6 2.4 3.6 2.2 3.6 Keep RAM and register data in HOLD mode. mode Input high VIH(1) voltage • Ports 1, 71 to 73 Output disable • Port 70 2.4 to 3.6 input/interrupt VIH(2) • Ports 0, C Output disable • PWM VIH(3) Port 70 VIH(4) XT1, CF1, RES VIL(1) • Ports 1, 71 to 73 Output disable Watchdog timer Input low Voltage 2.4 to 3.6 0.3VDD VDD +0.7 0.3VDD +0.7 VDD 2.4 to 3.6 0.9VDD VDD 2.4 to 3.6 0.75VDD VDD 2.4 to 3.6 VSS 0.2VDD 2.4 to 3.6 VSS 0.2VDD 2.4 to 3.6 VSS 2.4 to 3.6 VSS 0.25VDD 2.4 to 3.6 0.75 200 2.4 to 3.6 0.1 4 2.4 to 3.6 0.1 8 V Output disable • Port 70 input/interrupt VIL(2) • Ports 0, C Output disable • PWM VIL(3) Port 70 Output disable Watchdog timer VIL(4) Operation XT1, CF1, RES tCYC cycle time External FEXCF(1) CF1 • CF2 open system clock • system clock divider: 1/1 frequency • external clock DUTY=50±5% Oscillation FmCF CF1, CF2 oscillation range See Fig. 1. FmRC RC oscillation target: VDD=3.00V, Ta=25°C FsX’tal XT1, XT2 -1.0 2.4 to 3.6 2.4 to 3.6 4 0.3 0.5 32.768kHz crystal resonator oscillation µs MHz 4MHz ceramic resonator frequency (Note2-1) 0.8VDD 0.7 KHz 2.4 to 3.6 32.768 See Fig. 2. Note 2-1: The parts value of oscillation circuit is shown in table 1 and table 2. No.A0653-11/21 LC87F7032A Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= 0V Parameter Symbol Pins Specification Conditions VDD[V] High level input IIH(1) current • Ports 0, 1, 7 • Output disabled • Port C, PWM • RES • Pull-up resister OFF. • VIN=VDD min typ max unit 2.4 to 3.6 1 2.4 to 3.6 1 2.4 to 3.6 8 (Including OFF state leak current of the output Tr.) IIH(2) Low level input XT1, XT2 When configured as an input port IIH(3) CF1 VIN=VDD VIN=VDD IIL(1) • Ports 0, 1, 7 • Output disabled • Port C, PWM • RES • Pull-up resister OFF. current • VIN=VSS 2.4 to 3.6 -1 2.4 to 3.6 -1 µA (Including OFF state leak current of the output Tr.) IIL(2) XT1, XT2 When configured as an input port VIN=VSS High level output IIL(3) CF1 VIN=VSS VOH(1) Ports 0, 1, 7 IOH=-0.4mA CMOS voltage -8 3.0 to 3.6 VDD -0.4 VOH(2) output option IOH=-0.2mA 2.4 to 3.6 VDD -0.4 VOH(3) Port C IOH=-0.1mA 2.4 to 3.6 VDD -0.4 VOH(4) PWM IOH=-1.6mA 3.0 to 3.6 VDD -0.4 IOH=-0.8mA 2.4 to 3.6 VDD -0.4 Low level output VOL(1) voltage VOL(2) VOL(3) Ports 0, 1, 7,PWM P00, P01 VOL(4) LCD output voltage 2.4 to 3.6 IOL=1.6mA 3.0 to 3.6 0.4 IOL=0.8mA 2.4 to 3.6 0.4 IOL=5.0mA 3.0 to 3.6 0.4 IOL=2.5mA 2.4 to 3.6 0.4 VOL(5) Port C IOL=0.1mA 2.4 to 3.6 0.4 VODLS S0 to S23 IO=0mA V1, V2, V3 2.4 to 3.6 0 ±0.2 2.4 to 3.6 0 ±0.2 2.4 to 3.6 25 regulation V LCD level output VODLC COM0 to COM3 IO=0mA V1, V2, V3 LCD level output Resistance of Rpu • Ports 0, 1, 7 Hysterisis voltage VHYS(1) • Ports 1, 7 • RES Pin capacitance CP All pins VOH=0.9VDD pull-up MOS Tr. 50 200 kΩ 2.4 to 3.6 0.1VDD V 2.4 to 3.6 10 pF • All other terminals connected to VSS. • f=1MHz • Ta=25°C No.A0653-12/21 LC87F7032A Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock VDD Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. tSCKH(1) 2.4 to 3.6 pulse width tSCKHA(1) tCYC 4 (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. Output clock Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 2.4 to 3.6 pulse width tSCKHA(2) 1/2 • Continuous data transmission/ reception mode tSCKH(2) • CMOS output selected +2tCYC • See Fig. 6. Data setup time Serial input unit 1 • Continuous data transmission/ reception mode tsDI(1) SB0(P11), SI0(P11) tSCKH(2) +(10/3) tCYC tCYC • Must be specified with respect to rising edge of SIOCLK. 2.4 to 3.6 0.03 2.4 to 3.6 0.03 • See Fig. 6. Data hold time Output clock Input clock Output Serial output max 1 • See Fig. 6. Serial clock typ 2 pulse width High level min thDI(1) tdD0(1) delay time SO0(P10), SB0(P11) • Continuous data transmission/ reception mode 2.4 to 3.6 (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode (Note 4-1-3) tdD0(3) 2.4 to 3.6 (1/3)tCYC +0.05 µs 1tCYC +0.05 (Note 4-1-3) 2.4 to 3.6 (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. No.A0653-13/21 LC87F7032A 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock Frequency tSCK(3) Low level tSCKL(3) SCK1(P15) See Fig. 6. 2.4 to 3.6 pulse width High level Frequency SCK1(P15) • CMOS output selected tSCKL(4) 2 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time SB1(P14), SI1(P14) • Must be specified with respect to rising edge of SIOCLK. 2.4 to 3.6 0.03 2.4 to 3.6 0.03 • See Fig. 6. Data hold time Output delay Serial output tsDI(2) unit 1 2.4 to 3.6 pulse width High level max 1 • See Fig. 6. Low level typ tCYC tSCKH(3) tSCK(4) min 2 pulse width Output clock Serial clock VDD thDI(2) tdD0(4) time SO1(P13), SB1(P14) µs • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state (1/3)tCYC 2.4 to 3.6 +0.05 change in open drain output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2= 0V Parameter Symbol Pins High/low tPIH(1) INT0(P70), • Condition that interrupt is accepted level pulse tPIL(1) INT1(P71), • Condition that event input to timer 0 is Specification Conditions VDD[V] width INT2(P72) min 2.4 to 3.6 1 2.4 to 3.6 2 INT3(P73) • Condition that interrupt is accepted tPIL(2) (Noise rejection ratio is 1/1.) • Condition that event input to timer 0 is accepted tPIH(3) INT3(P73) • Condition that interrupt is accepted tPIL(3) (Noise rejection ratio is • Condition that event input to timer 0 is INT3(P73) • Condition that interrupt is accepted tPIL(4) (Noise rejection ratio is • Condition that event input to timer 0 is tPIL(6) RES unit tCYC 2.4 to 3.6 64 2.4 to 3.6 256 2.4 to 3.6 200 accepted tPIH(4) 1/128.) max accepted tPIH(2) 1/32.) typ accepted • Condition that reset is accepted µs No.A0653-14/21 LC87F7032A AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Resolution N AN0(P00) to Absolute ET AN4(P04), accuracy AN5(P70) to Conversion AN8(P73) tCAD time min. max. unit 8 bit (Note 6-1) ±1.5 AD conversion time=32×tCYC (When ADCR2=0) (Note 6-2) 24 320 (tCYC= (tCYC= 0.75µs) 10µs) 48 640 AD conversion time 64×tCYC (When ADCR2=1) (Note 6-2) Analog input typ. (tCYC= (tCYC= 0.75µs) 10µs) VSS VDD VAIN voltage range Analog port IAINH VAIN=VDD input current IAINL VAIN=VSS 1 -1 LSB µs V µA Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register. Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2= 0V Parameter Symbol Pins Specification Conditions VDD[V] consumption VDD1= VDD2= • FmX’tal=32.768kHz crystal oscillation current V2 • System clock: CF 4MHz oscillation Normal mode IDDOP(1) (Note 7-1) min typ max unit • FmCF=4MHz ceramic resonator oscillation 2.4 to 3.6 1.7 4.2 2.4 to 3.6 0.6 1.4 • Internal RC oscillation stopped. • Divider: 1/1 IDDOP(2) • FmCF=1MHz ceramic resonator oscillation • FmX’tal=32.768kHz crystal oscillation • System clock: CF 1MHz oscillation • Internal RC oscillation stopped. mA • Divider: 1/1 IDDOP(3) • FmCF=0Hz (No oscillation) • FmX’tal=32.768kHz crystal oscillation • System clock: RC oscillation 2.4 to 3.6 0.4 0.9 2.4 to 3.6 0.3 0.6 2.4 to 3.6 20 59 • Divider: 1/1 IDDOP(4) • FmCF=0Hz (No oscillation) • FmX’tal=32.768kHz crystal oscillation • System clock: RC oscillation • Divider: 1/2 IDDOP(5) • FmCF=0Hz (No oscillation) • FmX’tal=32.768kHz crystal oscillation • System clock: variable RC oscillation 1MHz • Divider: 1/1 IDDOP(6) µA • FmCF=0Hz (No oscillation) • FmX’tal=32.768kHz crystal oscillation • System clock: 32.768kHz 2.4 to 3.6 15 45 • Internal RC oscillation stopped. • Divider: 1/2 Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored. Continued on next page. No.A0653-15/21 LC87F7032A Continued from preceding page. Parameter Symbol Pins Specification Conditions VDD[V] HALT mode IDDHALT(1) consumption VDD1= VDD2=V2 min typ max unit HALT mode • FmCF=4MHz Ceramic resonator oscillation current • FmX’tal=32.768kHz crystal oscillation (Note 7-1) • System clock: CF 4MHz oscillation 2.4 to 3.6 0.8 2.1 2.4 to 3.6 0.3 1.4 • Internal RC oscillation stopped. • Divider: 1/1 IDDHALT(2) HALT mode • FmCF=1MHz Ceramic resonator oscillation • FmX’tal=32.768kHz crystal oscillation • System clock:CF 1MHz oscillation • Internal RC oscillation stopped. mA • Divider: 1/1 IDDHALT(3) HALT mode • FmCF=0Hz(Oscillation stop) • FmX’tal=32.768kHz crystal oscillation 2.4 to 3.6 0.20 0.5 2.4 to 3.6 0.16 0.4 2.4 to 3.6 7.5 32 2.4 to 3.6 5.5 27 • System clock: RC oscillation • Divider: 1/1 IDDHALT(4) HALT mode • FmCF=0Hz(Oscillation stop) • FmX’tal=32.768kHz crystal oscillation • System clock: RC oscillation • Divider: 1/2 IDDHALT(5) HALT mode • FmCF=0Hz(Oscillation stop) • FmX’tal=32.768kHz crystal oscillation • System clock: variable RC oscillation 1MHz • Divider: 1/1 IDDHALT(6) HALT mode • FmCF=0Hz(Oscillation stop) • FmX’tal=32.768kHz crystal oscillation • System clock: 32.768kHz µA • Internal RC oscillation stopped. • Divider: 1/2 HOLD mode IDDHOLD(1) consumption current Timer HOLD HOLD mode • CF1=VDD or open IDDHOLD(2) 0.03 10 2.4 to 3.6 3.8 24 Date/time clock mode HOLD mode consumption • CF1=VDD or open current 2.4 to 3.6 (when using external clock) (when using external clock) • FmX’tal=32.768kHz crystal oscillation Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored. No.A0653-16/21 LC87F7032A F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2= 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Onboard IDDFW(1) VDD1 programming min typ max unit • 128-byte programming • Erasing current included 3.0 to 3.6 15 40 mA 3.0 to 3.6 20 40 ms current Programming tFW(1) • 128-byte programming time • Erasing current included • Time for setting up 128-byte data is excluded. UART (Full Duplex) Operating Conditions at Ta = +20°C to +70°C, VSS1 = VSS2= 0V Parameter Symbol Pin/Remarks Specification Conditions VDD[V] Transfer rate UBR UTX(S22), 2.4 to 3.6 URX(S23) min. typ. 16/3 max. unit 8192/3 tCYC Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Stop bit Start bit Start of reception Receive data (LSB first) End of reception UBR No.A0653-17/21 LC87F7032A Main System Clock Oscillation Circuit Characteristics The characteristics in the table bellow is based on the following conditions: Use the standard evaluation board SANYO has provided. Use the peripheral parts with indicated value externally. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator Circuit parameters Frequency 4.00MHz Manufacturer Murata Type Oscillator SMD CSTCR4M00G53-R0 Lead CSTLS4M00G53-B0 (15) C1 Operating Oscillation supply voltage stabilizing time Notes range typ max [Ω] [V] [ms] [ms] 1k 2.4 to 3.6 0.2 0.6 Built in 2.2k 2.4 to 3.6 0.2 0.6 C1, C2 C2 Rd1 [pF] [pF] (15) (15) (15) The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (See Fig. 4.) Subsystem Clock Oscillator Circuit Characteristics The characteristics in the table bellow is based on the following conditions: Use the standard evaluation board SANYO has provided. Use the peripheral parts with indicated value externally. The peripheral parts value is a recommended value of oscillator manufacturer Table 2 Subsystem Clock Oscillation Circuit Characteristics Using Crystal Oscillator Circuit Constant Frequency 32.768kHz Manufacturer Epson Toyocom Oscillator MC-146 Operating Oscillation supply Stabilization Time C3 C4 Rf Rd2 voltage range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 3 3 Open 0 2.4 to 3.6 1 3 Notes Applicable CL value=7.0pF The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (See Fig. 4.) Note: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF2 CF1 XT1 Rd1 C1 CF C2 XT2 Rf C3 Rd2 C4 X’tal Figure 1 Ceramic Oscillator Circuit Figure 2 Crystal Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A0653-18/21 LC87F7032A VDD Power supply VDD limit OV Reset time RES Internal RC Resonator oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Reset Unfixed Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD reset signal Without HOLD Release HOLD reset signal VALID Internal RC Resonator oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operation mode HOLD HALT HOLD Release Signal and Oscillation Stable Time Figure 4 Oscillation Stabilizing Time No.A0653-19/21 LC87F7032A VDD RRES Note: Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. RES CRES Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transmission period (SIO0 only) tSCK tSCKH tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transmission period (SIO0 only) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial Input/Output Wave Form tPIL tPIH Figure 7 Pulse Input Timing Condition No.A0653-20/21 LC87F7032A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2007. Specifications and information herein are subject to change without notice. PS No.A0653-21/21