Ordering number : ENA1840
LC877917A
CMOS IC
16K-byte ROM and 512-byte RAM integrated
8-bit 1-chip Microcontroller
Overview
The SANYO LC877917A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 250ns, integrates on a single chip a number of hardware features such as 16K-byte ROM, 512-byte RAM, a LCD
controller/driver, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be
divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a calendar function (RTC), a
synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO
interface, a UART interface (full duplex), a 12-bit/8-bit 7-channel AD converter, high-speed clock counter, a system
clock frequency divider, a power on reset function and a 21-source 10-vector interrupt feature.
Features
ROM
• 16384×8 bits
RAM
512 × 9 bits
Minimum Bus Cycle
• 250ns (4MHz) VDD=2.4V to 3.6V
Note: The bus cycle time here refers to the ROM read speed.
Minimum instruction cycle time
• 750ns (4MHz) VDD=2.4 to 3.6V
Temperature range
• -40°C to +85°C
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.0.97
O0610HKIM 20100914-S00003 No.A1840-1/29
LC877917A
Ports
• Input/output ports
Data direction programmable for each bit individually:
Other function
LCD ports (segment output):
• LCD ports & General I/O ports
Segment output:
Common output:
Bias terminals for LCD driver
Other functions
Input/output ports:
• Oscillator pins:
• Reset pin:
• Power supply:
21 (P0n, P1n, P30, P70-P73)
8 (P1n)
32 (S00-S31)
4 (COM0-COM3)
5 (V1-V3, CUP1, CUP2)
36 (LPAn, LPBn, LPCn, LPLn, P1n)
4 (CF1, CF2, XT1, XT2)
1 (RES)
5 (VSS1-2, VDD1-2, V2)
1 (VDC)
LCD Controller
(1) Seven display modes are available
(2) Duty 1/3duty, 1/4duty
(3) Bias 1/2bias, 1/3bias
(4) Segment output can be switched to general purpose input/output ports.
(5) LCD frame rate frequency: 16 to 85.3Hz (programmable)
(6) LCD power range
1) 1/3bias
V1 : 1.2V to 1.8V
V2 : 2.4V to 3.6V
V3 : 3.6V to 5.4V
Please use the LCD panel for V2 (=VDD)× 1.5[V], when you select 1/3bias.
For example, if the power supply voltage is 3.0V, the LCD panel must be 4.5V.
2) 1/2bias
V1 : 1.2V to 1.8V
V2 : 2.4V to 3.6V
V3 : 2.4V to 3.6V
(connect V2 and V3)
Please use the LCD panel for V2 (=VDD)[V], when you select 1/3bias.
For example, if the power supply voltage is 3.0V, the LCD panel must be 3.0V.
Timers
• Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
• Timer 1: PWM / 16 bit timer/ counter with toggle output function
Mode 0: 2 channel 8 bit timer/ counter (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer/ counter (with toggle output) Toggle output from lower 8 bits is also possible.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.
• Timer 4: 8-bit timer with 6-bit prescaler
• Timer 5: 8-bit timer with 6-bit prescaler
• Timer 6: 8-bit timer with 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with 6-bit prescaler (with toggle output)
• Base Timer
(1) The clock signal can be selected from any of the following:
Sub-clock (32.768kHz crystal oscillator / Slow RC oscillation), system clock, and prescaler output from timer 0.
(2) Interrupts of five different time intervals are possible.
No.A1840-2/29
LC877917A
High-speed Clock Counter
(1) Can count clocks with a maximum clock rate of 8MHz (at a main clock of 4MHz).
(2) Can generate output real-time.
Serial-interface
• SIO 0: 8 bit synchronous serial interface
(1) Synchronous 8-bit serial I/O (2- or 3-wire system, clock rates of (4/3) to (512/3) tCYC)
(2) Continuous data transmission/reception (Variable length data transmission in bit units from 1 to 256 bits,
clock rates of (4/3) to (512/3) tCYC)
(3) Bi-phase modulation (Manchester, Bi-phase-Space) data transmission
(4) LSB first / MSB first is selectable
(5) SPI_function: serial interface that can release HOLD/X’tal HOLD mode after receiving 1-byte (8-bit clock).
• SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
• Operating mode: Programmable transfer mode, fixed-rate transfer mode
• Transmission data conversion: Normal (NRZ), Manchester encoding
AD converter: 12 bits/8 bits × 7 channels
• 12 bits/8 bits AD converter resolution selectable
Remote Control Receiver Circuit (Connected to P73 / INT3 / T0IN terminal)
• Noise rejection function (Noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC)
Watchdog Timer
• Watchdog timer can produce interrupt or system reset.
• Watchdog timer has two types.
(1) Use an external RC circuit
(2) Use the microcontroller’s basetimer
• Watchdog timer that used basetimer can select only one period (1 / 2 / 4 / 8 s) by the user option.
Buzzer Output
• The buzzer output can transmitted from P17 by using basetimer.
Real Time Clock (RTC)
(1) Used with a basetimer, it can be used as a century + year + month + day + hour + minute + second counter.
(2) Calendar counts up to December 31, 2799 with automatic leap-year calculation.
(3) Gregorian calendar capable of keeping GMT (Greenwich Mean Time).
Internal Reset Function
• Power-On-Reset (POR) function
− POR resets the system when the power supply voltage is applied.
No.A1840-3/29
LC877917A
Interrupts: 21 sources, 10 vectors
(1) Three priority (Low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower priority interrupt request is postponed.
(2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L
4
0001BH
H or L
INT3/Base timer/RTC
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1-receive
8
0003BH
H or L
SIO1/UART-send
9
00043H
H or L
ADC/T6/T7/SPI
10
0004BH
H or L
Port 0/T4/T5
• Priority levels X > H > L
• For equal priority levels, vector with lowest address takes precedence
Subroutine Stack Levels: 256 levels max. Stack is located in RAM.
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• On-chip fast RC oscillation (Typical: 500kHz) for system clock use.
• On-chip slow RC oscillation (Typical: 50kHz) for system clock use.
• CF oscillation (4MHz) for system clock use. (Rf built in, Rd external)
• Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in)
• Frequency variable RC oscillation circuit (internal): For system clock.
(1) Adjustable in ±4% (typ.) step from a selected center frequency.
(2) Measures oscillation clock using a input signal from XT1 as a reference.
System Clock Divider
• Low power consumption operation is available.
• Minimum instruction cycle time (750ns, 1.5μs, 3.0μs, 6.0μs, 12μs, 24μs, 48μs, 96μs, 192μs can be switched by
program. (when using 4MHz main clock)
System Clock Output
• The system clock output can transmitted from P04.
No.A1840-4/29
LC877917A
Standby Function
• HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (Some parts of serial transfer operation stop.)
(1) Oscillation circuits are not stopped automatically.
(2) Released by the system reset or interrupts.
• HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
(1) CF, RC and crystal oscillation circuits stop automatically.
(2) Released by any of the following conditions.
1) Low level input to the reset pin
2) Watchdog timer interrupt
3) Specified level input to one of INT0, INT1, INT2
4) Port 0 interrupt
5) SPI interrupt by receiving 1-byte (8-bit clock)
• X’tal HOLD mode
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
(1) CF and RC oscillation circuits stop automatically.
(2) Crystal oscillator operation is kept in its state at HOLD mode inception.
(3) Released by any of the following conditions.
1) Low level input to the reset pin
2) Watchdog timer interrupt
3) Specified level input to one of INT0, INT1, INT2
4) Port 0 interrupt
5) Base-timer interrupt
6) RTC interrupt
7) SPI interrupt by receiving 1-byte (8-bit clock)
Shipping Form
• QIP64E (14×14) (Lead-/Halogen-free type)
• TQFP64J (7×7) (Lead-/Halogen-free type)
• SQFP64 (10×10) (Lead-/Halogen-free type)
• CHIP
Development Tools
• On-chip debugger: TCB87 TypeB+LC87F7932B
No.A1840-5/29
LC877917A
Package Dimensions
Package Dimensions
unit : mm (typ)
3159A
unit : mm (typ)
3289
17.2
14.0
9.0
17
33
49
32
64
17
7.0
64
14.0
32
1
1
0.35
0.8
16
0.4
16
0.15
0.16
9.0
48
49
0.5
7.0
0.8
33
17.2
48
0.125
(0.5)
0.1
0.1
3.0max
1.2max
(2.7)
(1.0)
(1.0)
SANYO : QIP64E(14X14)
SANYO : TQFP64J(7X7)
Package Dimensions
unit : mm (typ)
3190A
12.0
0.5
10.0
48
33
64
12.0
32
10.0
49
17
1
16
0.5
0.18
0.15
0.1
1.7max
(1.5)
(1.25)
SANYO : SQFP64(10X10)
No.A1840-6/29
LC877917A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
S23/LPC7
S22/LPC6
S21/LPC5
S20/LPC4
S19/LPC3
S18/LPC2
S17/LPC1
S16/LPC0
S15/LPB7
S14/LPB6
S13/LPB5
S12/LPB4
S11/LPB3
S10/LPB2
S09/LPB1
S08/LPB0
Pin Assignment
LC877917A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P70/INT0/T0LCP/AN5
P71/INT1/T0HCP/AN6
P72/INT2/T0IN/NKIN
P73/INT3/T0IN
VDD2
VSS2
P10/SO0/S24
P11/SI0/SB0/S25
P12/SCK0/S26
P13/SO1/S27
P14/SI1/SB1/S28
P15/SCK1/S29
P16/T1PWML/S30
P17/T1PWMH/BUZ/S31
CUP1
CUP2
RES
XT1
XT2
VSS1
CF1
CF2
VDD1
P00/UTX1/AN0
P01/RTX1/AN1
P02/AN2
P03/AN3
P04/CKO/AN4
P05
P06/T6O
P07/T7O
P30
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S07/LPA7
S06/LPA6
S05/LPA5
S04/LPA4
S03/LPA3
S02/LPA2
S01/LPA1
S00/LPA0
COM3/LPL3
COM2/LPL2
COM1/LPL1
COM0/LPL0
V3
V2
V1
VDC
Top view
SANYO: QIP64E (14×14) “Lead-/Halogen-free type”
SANYO: TQFP64J (7×7) “Lead-/Halogen-free type”
SANYO: SQFP64 (10×10) “Lead-/Halogen-free type”
Chip Size: 2.25mm×2.23mm
Pad Size/Pitch:
84μm
80μm
96μm
84μm
Jacket Open
63μm
Pad Metal
79μm
No.A1840-7/29
LC877917A
PIN No.
NAME
PIN NO.
NAME
1
P70/INT0/T0LCP/AN5
33
S08/LPB0
2
P71/INT1/T0HCP/AN6
34
S09/LPB1
3
P72/INT2/T0IN/NKIN
35
S10/LPB2
4
P73/INT3/T0IN
36
S11/LPB3
5
VDD2
37
S12/LPB4
6
VSS2
38
S13/LPB5
7
P10/SO0/S24
39
S14/LPB6
8
P11/SI0/SB0/S25
40
S15/LPB7
9
P12/SCK0/S26
41
S16/LPC0
10
P13/SO1/S27
42
S17/LPC1
11
P14/SI1/SB1/S28
43
S18/LPC2
12
P15/SCK1/S29
44
S19/LPC3
13
P16/T1PWML/S30
45
S20/LPC4
14
P17/T1PWMH/BUZ/S31
46
S21/LPC5
15
CUP1
47
S22/LPC6
16
CUP2
48
S23/LPC7
17
VDC
49
RES
18
V1
50
XT1
19
V2
51
XT2
20
V3
52
VSS1
21
COM0/LPL0
53
CF1
22
COM1/LPL1
54
CF2
23
COM2/LPL2
55
VDD1
24
COM3/LPL3
56
P00/UTX1/AN0
25
S00/LPA0
57
P01/RTX1/AN1
26
S01/LPA1
58
P02/AN2
27
S02/LPA2
59
P03/AN3
28
S03/LPA3
60
P04/CKO/AN4
29
S04/LPA4
61
P05
30
S05/LPA5
62
P06/T6O
31
S06/LPA6
63
P07/T7O
32
S07/LPA7
64
P30
No.A1840-8/29
LC877917A
System Block Diagram
Interrupt Control
IR
Stand-by Control
PLA
ROM
Fast RC
Slow RC
Clock
Generator
CF
PC
VMRC
X’tal
WDT
ACC
Reset control
RES
B Register
Reset circuit
C Register
(POR)
Bus Interface
ALU
SIO0
Port 0
SIO1
Port 1
Timer 0
Port 3
Timer 1
Port 7
Base Timer
UART1
LCD Controller
RTC
INT0 - 3
Noise Rejection Filter
Timer 6
Timer 4
Timer 7
Timer 5
ADC
PSW
RAR
RAM
Stack Pointer
Watch Dog Timer
No.A1840-9/29
LC877917A
Pin Assignment
Pin name
I/O
Function
Option
VSS1, VSS2
-
• Power supply (-)
No
VDD1, VDD2, V2
-
• Power supply (+)
No
VDC
-
• Internal voltage
No
CUP1, CUP2
PORT0
I/O
P00 to P07
• Capacitor connecting terminals for step-up/step-down
No
• 8bit input/output port
Yes
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Input for HOLD release
• Input for port 0 interrupt
• Other pin functions
P00: UART1-send
P01: UART1-receive
P04: System clock output (CKO)
P06: Timer6 toggle output
P07: Timer7 toggle output
AD converter input ports: AN0 (P00) – AN4 (P04)
PORT1
I/O
• 8bit input/output port
Yes
P10/S24 to
• Data direction programmable for each bit
P17/S31
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10: SIO0 data output
P11: SIO0 data input or bus input/output
P12: SIO0 clock input/output
P13: SIO1 data output
P14: SIO1 data input or bus input/output
P15: SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
Segment output for LCD: S24 (P10) – S31 (S17)
PORT3
I/O
P30
• 1bit Input/output port
Yes
• Data direction programmable
• Use of pull-up resistor can be specified
PORT7
P70 to P73
I/O
• 4bit Input/output port
No
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/NKIN
P73: INT3 input (noise rejection filter attached)/timer 0 event input/Timer0H capture input
AD converter input ports: AN5 (P70), AN6 (P71)
• Interrupt detection selection
Rising
Falling
Rising and falling
H level
L level
INT0
enable
enable
disable
enable
enable
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
Continued on next page.
No.A1840-10/29
LC877917A
Continued from preceding page.
Pin name
S00/LPA0 to
I/O
I/O
S07/LPA7
S08/LPB0 to
I/O
I/O
• Segment output for LCD
No
• Segment output for LCD
No
• Can be used as general purpose input/output port (LPC)
I/O
COM3/LPL3
V1 to V3
No
• Can be used as general purpose input/output port (LPB)
S23/LPC7
COM0/LPL0 to
Option
• Can be used as general purpose input/output port (LPA)
S15/LPB7
S16/LPC0 to
Function description
• Segment output for LCD
• Common output for LCD
No
• Can be used as general purpose input/output port (LPL)
I/O
RES
I
XT1
I/O
• LCD output bias power supply
No
• Reset terminal
No
• Input for 32.768kHz crystal oscillation
No
• When not in use, connect to VDD1
XT2
I/O
• Output for 32.768kHz crystal oscillation
No
• When not in use, set to oscillation mode and leave open
CF1
I
• Input terminal for ceramic oscillator
No
• When not in use, connect to VDD1
CF2
O
• Output terminal for ceramic oscillator
No
• When not in use, leave open
Port Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Terminal
P00 to P07
P10/S24 to P17/S31
P30
Option applies to:
each bit
each bit
-
Options
Output Form
Pull-up resistor
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
Programmable
P70
-
None
Nch-open drain
P71 to P73
-
None
CMOS
Programmable
S00(LPA0) to
-
None
CMOS
None
S23(LPC7)
P-ch Open Drain
N-ch Open Drain
COM0(LPL0) to
-
None
COM3(LPL3)
CMOS
None
P-ch Open Drain
N-ch Open Drain
XT1
-
None
XT2
-
None
Input only
None
32.768kHz crystal oscillator output
None
Nch-open drain when selected as normal port
No.A1840-11/29
LC877917A
User Option Table
Option Name
Port output type
Option to be Applied on
P00 to P07
P10 to P17
P30
Basetimer
Mask-ROM
Flash-ROM
Option Selected
Version*1
Version
in Units of
{
{
1 bit
{
{
1 bit
{
{
1 bit
Option Selection
CMOS
Nch-open drain
CMOS
Nch-open drain
CMOS
Watchdog timer period
Nch-open drain
1s
watchdog timer
{
2s
{
-
4s
8s
Program start
address
-
*2
00000h
{
-
07E00h
*1: Mask option selection-No change possible after mask is completed.
*2: Program start address of the mask version is 00000h.
*Note 1: Connect as follows to reduce noise on VDD.
VSS1 and VSS2 must be connected together and grounded.
*Note 2: The power supply for the internal memory is V2. VDD1, VDD2 and V2 are used as the power supply for ports.
When VDD1 and VDD2 are not backed up, the port level does not become “H” even if the port latch is in the
“H” level. Therefore, when VDD1 and VDD2 are not backed up and the port latch is “H” level, the port level
is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from
VDD to GND in the input buffer.
If VDD1 and VDD2 are not backed up, output “L” by the program or pull the port to “L” by the external
circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is
prevented.
Back up capacitors
LSI
VDD1
Power
supply
VDD2
V1
V2
V3
CUP1
VDC
CUP2
VSS1 VSS2
No.A1840-12/29
LC877917A
Circuit Example
(1)1/3bias, 1/4duty
S23
S00
P10
P11
P12
P13
P14
P15
P16
P17
C1
C2
C3
C4
C5
2.4V to 3.6V
VDD1
VDD2
RRES
+
CDEN
RES
P70
P71
P72
P73
CRES
VSS1
VSS2
P30
CF
CDC
XT1
I/O
V2
V3
XT2
I/O
VDC
V1
LC877917A
CF1
I/O
CUP1
CUP2
P00
P01
P02
P03
P04
P05
P06
P07
CF2
I/O
2 4SEG×4C OM
COM3
COM0
LCD pan el
*1: Crystal oscillator
*2: Internal RC oscillation
*3: Ceramic oscillator
X'tal
CGC
*2
CDX
X'tal
Crystal oscillation
CGX
Trimmer capacitor
CDX
Capacitor for X’tal
CF
Ceramic oscillation
CGC
Capacitor for CF
CDC
Capacitor for CF
CGX
*1
C1 to C5
Capacitor (0.1μF is recommended)
CDEN
Electrolytic capacitor
RRES
Resistor for RES
CRES
Capacitor for RES
No.A1840-13/29
LC877917A
(2)1/2bias, 1/3duty
S23
S00
P10
P11
P12
P13
P14
P15
P16
P17
2.4V to 3.6V
VDD1
VDD2
RRES
+
CDEN
RES
P70
P71
P72
P73
CRES
VSS1
VSS2
P30
CF
CDC
XT1
I/O
V2
V3
XT2
I/O
C2
C3
C4
VDC
V1
LC877917A
CF1
I/O
C1
CUP1
CUP2
P00
P01
P02
P03
P04
P05
P06
P07
CF2
I/O
2 4SEG×3C OM
COM2
COM0
LCD pan el
*1: Crystal oscillator
*2: Internal RC oscillation
*3: Ceramic oscillator
X'tal
CGC
*2
CDX
CGX
*1
X'tal
Crystal oscillation
CGX
Trimmer capacitor
CDX
Capacitor for X’tal
CF
Ceramic oscillation
CGC
Capacitor for CF
CDC
Capacitor for CF
C1 to C4
Capacitor (0.1μF is recommended)
CDEN
Electrolytic capacitor
RRES
Resistor for RES
CRES
Capacitor for RES
No.A1840-14/29
LC877917A
Absolute Maximum Ratings at Ta=25°C and VSS1=VSS2=0V
Parameter
Symbol
Pins
Specification
Conditions
VDD[V]
Supply voltage
VDD max
VDD1, VDD2, V2
Supply voltage
VLCD
For LCD
Input voltage
VI
Input/Output
VIO(1)
voltage
VDD1=VDD2=2V
min
typ
max
unit
-0.3
+4.3
V1
-0.3
1/2VDD
V2
-0.3
VDD
V3
-0.3
2/3VDD
XT1, CF1, RES
-0.3
VDD+0.3
-0.3
VDD+0.3
V
• Port0, 1, 3, 7
• LPA, LPB, LPC
• LPL, XT2
Peak
IOPH(1)
Port 0, 1
output
High level output current
current
• CMOS output selected
• Current at each pin
IOPH(2)
Port 3
• CMOS output selected
IOPH(3)
LPA, LPB, LPC
• CMOS output selected
LPL
• Current at each pin
-20
-4
IOPH(4)
Port71 to P73
• Current at each pin
Total
∑IOAH(1)
Port 0
Total of all pins
-20
output
∑IOAH(2)
Port 3, 7
Total of all pins
-30
current
∑IOAH(3)
Port 1
Total of all pins
-20
∑IOAH(4)
Port 1, 3, 7
Total of all pins
-45
∑IOAH(5)
LPA, LPB, LPC,
Total of all pins
LPL
Low level output current
-10
-5
-30
mA
Peak
IOPL(1)
Port 0, 1
Current at each pin
20
output
IOPL(2)
Port 3
Current at each pin
30
IOPL(3)
Port 7
Current at each pin
10
IOPL(4)
LPA, LPB, LPC,
Current at each pin
current
6
LPL
Total
output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
Port 0
Total of all pins
40
Port 3, 7
Total of all pins
50
Port 1
Total of all pins
40
Port 1, 3, 7
Total of all pins
65
LPA, LPB, LPC,
Total of all pins
60
LPL
Maximum
Pd max
power
QIP64E (14×14)
Ta = -40 to +85°C
267
TQFP64J (7×7)
124
SQFP64 (10×10)
192
consumption
Operating
Topr
temperature
-40
85
range
Storage
mW
°C
Tstg
temperature
-55
125
range
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A1840-15/29
LC877917A
Allowable Operating Conditions at Ta=-40 to +85°C, VSS1=VSS2=0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Operating
VDD(1)
VDD1=VDD2=V2
0.75μs≤tCYC≤200μs
supply voltage
Normal mode
(Note 2-1)
4.28μs≤tCYC≤200μs
Power save mode
Memory
VHD
VDD1=VDD2=V2
sustaining
min
typ
max
unit
2.4
3.6
2.4
3.6
2.2
3.6
RAM and register contents
sustained in HOLD mode.
supply voltage
High level
VIH(1)
input voltage
Port 0, 3
Output disabled
LPA, LPB, LPC, LPL
VIH(2)
Port 1
• Output disabled
Port 71 to 73
• When INT1VTSL=0
P70 port input
(P71 only)
2.4 to 3.6
2.4 to 3.6
0.3VDD
VDD
+0.7
0.3VDD
+0.7
VDD
0.85VDD
VDD
2.4 to 3.6
0.9VDD
VDD
2.4 to 3.6
0.75VDD
VDD
2.4 to 3.6
VSS
0.2VDD
2.4 to 3.6
VSS
0.2VDD
2.4 to 3.6
VSS
0.45VDD
2.4 to 3.6
VSS
2.4 to 3.6
VSS
/ interrupt side
VIH(3)
P71 interrupt side
• Output disabled
• When INT1VTSL=1
VIH(4)
P70 watchdog timer
Output disabled
Side
Low level input
VIH(5)
XT1, XT2, CF1, RES
VIL(1)
Port 0, 3
voltage
Output disabled
LPA, LPB, LPC, LPL
VIL(2)
Port 1
• Output disabled
Port 71 to 73
• When INT1VTSL=0
P70 port input
(P71 only)
2.4 to 3.6
V
/ interrupt side
VIL(3)
P71 interrupt side
• Output disabled
• When INT1VTSL=1
VIL(4)
P70 watchdog timer
Output disabled
side
VIL(5)
Instruction
XT1, XT2, CF1, RES
0.8VDD
-1.0
0.25VDD
tCYC
cycle time
2.4 to 3.6
200
μs
(Note 2-2)
External
FEXCF(1)
CF1
system clock
• CF2 pin open
• System clock frequency
frequency
division ratio = 1/1
2.4 to 3.6
0.1
4
• External system clock
MHz
duty = 50±5%
• CF2 pin open
• System clock frequency
2.4 to 3.6
0.2
8
division ratio = 1/2
Oscillation
FmCF(1)
CF1, CF2
frequency
• 4MHz ceramic oscillation
• See Fig. 1.
2.4 to 3.6
4
MHz
range
FmRC(1)
Internal Fast RC oscillation
2.4 to 3.6
350
500
650
(Note 2-3)
FsRC(1)
Internal Slow RC oscillation
2.4 to 3.6
25
50
75
FsX’tal
XT1, XT2
kHz
• 32.768kHz crystal
oscillation
2.4 to 3.6
32.768
• See Fig. 2.
Frequency
OpVMRC(1)
variable RC
oscillation
When VMSL4M=0
(Note 2-4)
OpVMRC(2)
When VMSL4M=1
usable range
Frequency
VmADJ(1)
variable RC
3.0 to 3.6
8
10
12
2.4 to 3.6
3.5
4
4.5
2.4 to 3.6
8
24
64
MHz
Each step of VMRAJn
(Wide range)
%
oscillation
adjustment
range
VmADJ(2)
Each step of VMFAJn
(Small range)
2.4 to 3.6
1
4
8
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Note 2-4: Normal Power mode only.
No.A1840-16/29
LC877917A
Electrical Characteristics at Ta=-40 to +85°C, VSS1=VSS2=0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
current
Port 0, 1, 3, 7
• Output disabled
LPA, LPB, LPC
• Pull-up resistor off
LPL
• VIN=VDD
min
typ
max
unit
2.4 to 3.6
1
2.4 to 3.6
1
2.4 to 3.6
1
2.4 to 3.6
15
(Including output Tr's off
leakage current)
IIH(2)
RES
VIN=VDD
IIH(3)
XT1, XT2
• For input port specification
• VIN=VDD
Low level input
IIH(4)
CF1
VIN=VDD
IIL(1)
Port 0, 1, 3, 7
• Output disabled
LPA, LPB, LPC
• Pull-up resistor off
LPL
• VIN=VSS
current
2.4 to 3.6
-1
2.4 to 3.6
-1
2.4 to 3.6
-1
μA
(Including output Tr's off
leakage current)
IIL(2)
RES
VIN=VSS
IIL(3)
XT1, XT2
• For input port specification
• VIN=VSS
IIL(4)
CF1
VIN=VSS
2.4 to 3.6
-15
High level output
VOH(1)
Port 0, 1
IOH=-0.4mA
3.0 to 3.6
VDD-0.4
voltage
VOH(2)
IOH=-0.2mA
2.4 to 3.6
VDD-0.4
IOH=-1.6mA
3.0 to 3.6
VDD-0.4
IOH=-1mA
2.4 to 3.6
VDD-0.4
IOH=-0.4mA
3.0 to 3.6
VDD-0.4
IOH=-0.2mA
2.4 to 3.6
VDD-0.4
2.4 to 3.6
VDD-0.4
VOH(3)
Port 3
VOH(4)
VOH(5)
Port 71 to 73
VOH(6)
VOH(7)
LPA, LPB, LPC
IOH=-0.1mA
LPL
Low level output
VOL(1)
voltage
VOL(2)
VOL(3)
Port 0, 1
Port 3
VOL(4)
IOL=1.6mA
3.0 to 3.6
0.4
IOL=1mA
2.4 to 3.6
0.4
IOL=5mA
3.0 to 3.6
0.4
IOL=2.5mA
2.4 to 3.6
0.4
VOL(5)
Port 7
IOL=1.6mA
3.0 to 3.6
0.4
VOL(6)
XT2
IOL=1mA
2.4 to 3.6
0.4
VOL(7)
LPA, LPB, LPC
IOL=0.1mA
2.4 to 3.6
0.4
LPL
LCD output voltage
VODLS
S00 to S31
regulation
• IO=0mA
• V1, V2, V3
2.4 to 3.6
0
±0.2
2.4 to 3.6
0
±0.2
2.4 to 3.6
18
V
LCD level output
VODLC
COM0 to COM3
• IO=0mA
• V1, V2, V3
LCD level output
Resistance of pull-
Rpu(1)
Port 0, 1, 3, 7
Hysterisis voltage
VHYS(1)
Port 1, 7
RES
Pin capacitance
CP
All pins
VOH=0.9VDD
up MOS Tr.
50
150
kΩ
2.4 to 3.6
0.1VDD
V
2.4 to 3.6
10
pF
• For pins other than that
under test: VIN=VSS
• f=1MHz
• Ta=25°C
No.A1840-17/29
LC877917A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig. 6.
Input clock
tSCKH(1)
pulse width
tSCKHA(1)
typ
max
unit
2
1
pulse width
High level
min
1
• Continuous data
2.4 to 3.6
tCYC
transmission/reception
mode
4
Serial clock
• See Fig. 6.
• (Note 4-1-2)
Frequency
tSCK(2)
Low level
tSCKL(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
1/2
Output clock
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
2.4 to 3.6
tSCKHA(2)
• Continuous data
transmission/reception
tSCKH(2)
mode
+2tCYC
• CMOS output selected
tSCKH(2)
+(10/3)
tCYC
tCYC
• See Fig. 6.
Serial input
Data setup time
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
2.4 to 3.6
0.03
2.4 to 3.6
0.03
SIOCLK.
Data hold time
Input clock
Output delay
• See Fig. 6.
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception
mode
2.4 to 3.6
(1/3)tCYC
+0.05
μs
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
Output clock
Serial output
tsDI(1)
tdD0(3)
2.4 to 3.6
1tCYC
+0.05
(Note 4-1-3)
2.4 to 3.6
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1840-18/29
LC877917A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
min
See Fig. 6.
tSCK(4)
Low level
tSCKL(4)
1
SCK1(P15)
• CMOS output selected
2
• See Fig. 6.
1/2
2.4 to 3.6
pulse width
High level
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
unit
tCYC
tSCKH(3)
Frequency
max
1
2.4 to 3.6
pulse width
High level
typ
2
pulse width
Output clock
Serial clock
VDD[V]
SB1(P14),
tsDI(2)
• Must be specified with
SI1(P14)
respect to rising edge of
2.4 to 3.6
0.03
2.4 to 3.6
0.03
SIOCLK.
• See Fig. 6.
thDI(2)
Data hold time
Output delay time
tdD0(4)
SO1(P13),
• Must be specified with
μs
respect to falling edge of
Serial output
SB1(P14)
SIOCLK.
• Must be specified as the
time to the beginning of
(1/3)tCYC
2.4 to 3.6
+0.05
output state change in
open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1
2.4 to 3.6
1
2.4 to 3.6
2
max
unit
enabled.
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
constant is 1/32
tCYC
2.4 to 3.6
64
2.4 to 3.6
256
2.4 to 3.6
200
enabled.
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
constant is 1/128
RES
typ
are enabled.
tPIH(2)
tPIL(5)
min
enabled.
Resetting is enabled.
μs
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Option selected voltage
POR release voltage
PORR
Detection voltage
POUKS
unknown state
min
typ
• See Fig. 8.
(Note 6-1)
max
unit
1.79
V
0.7
0.95
Note 6-1: POR is in an unknown state before transistors start operation.
No.A1840-19/29
LC877917A
AD Converter Characteristics at VSS1 = VSS2 = 0V
<12bits AD Converter Mode at Ta=-40 to +85°C> <Normal power mode only>
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
AN0(P00) to
Resolution
N
Absolute
ET
Conversion time
3.0 to 3.6
AN4(P04),
(Note 7-1)
AN6(P71)
TCAD
typ
max
unit
12
3.0 to 3.6
AN5(P70) to
accuracy
min
bit
±16
LSB
• See Conversion time
calculation formulas.
3.0 to 3.6
64
115
μs
3.0 to 3.6
VSS
VDD
V
(Note 7-2)
Analog input
VAIN
voltage range
Analog port input
IAINH
VAIN=VDD
3.0 to 3.6
current
IAINL
VAIN=VSS
3.0 to 3.6
1
-1
μA
<8bits AD Converter Mode at Ta=-40 to +85°C> <Normal power mode only>
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN4(P04),
Conversion time
3.0 to 3.6
(Note 7-1)
AN6(P71)
TCAD
typ
max
Unit
8
bit
±1.5
3.0 to 3.6
AN5(P70) to
accuracy
min
LSB
• See Conversion time
calculation formulas.
3.0 to 3.6
40
90
μs
3.0 to 3.6
VSS
VDD
V
(Note 7-2)
Analog input
VAIN
voltage range
Analog port input
IAINH
VAIN=VDD
3.0 to 3.6
current
IAINL
VAIN=VSS
3.0 to 3.6
1
-1
μA
Conversion Time Calculation Formulas:
12bits AD Converter Mode : TCAD(Conversion time) = ((52/(division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode : TCAD(Conversion time) = ((32/(division ratio))+2)×(1/3)×tCYC
External
Operating supply
oscillation
voltage range
(FmCF)
(VDD)
CF-4MHz
3.0V to 3.6V
System division ratio
Cycle time
(SYSDIV)
(tCYC)
1/1
750ns
AD division
AD conversion time
(TCAD)
ratio
(ADDIV)
12bit AD
8bit AD
1/8
104.5μs
64.5μs
Note 7-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 7-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion
mode.
No.A1840-20/29
LC877917A
Current Consumption Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin
Specification
Conditions
VDD[V]
Current
IDDOP(1)
consumption
during normal
VDD1=
VDD2=V2
min
typ
max
unit
• FmCF=4MHz Ceramic resonator
oscillation
• FsX’tal=32.768kHz crystal oscillation
operation
(Normal operation)
(Note 8-1)
• System clock: CF 4MHz oscillation
2.4 to 3.6
1.2
2.8
2.4 to 3.6
135
400
2.4 to 3.6
43
150
mA
• Internal RC oscillation stopped.
• Divider: 1/1
• Normal power mode
IDDOP(2)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: Fast RC oscillation
• Divider: 1/1
• Normal power mode
IDDOP(3)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: Fast RC oscillation
• Divider: 1/1
• Power save mode
IDDOP(4)
μA
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: Slow RC oscillation
2.4 to 3.6
23
105
2.4 to 3.6
14
80
2.4 to 3.6
1.2
2.8
mA
2.4 to 3.6
14
73
μA
• Divider :1/1
• Normal power mode
IDDOP(5)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: Slow RC oscillation
• Divider: 1/1
• Power save mode
IDDOP(6)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal Oscillation
(Normal operation)
• Internal RC oscillation stopped.
• System clock: VMRC oscillation
(4MHz)
• Divider: 1/1
• Normal power mode
IDDOP(7)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
• Normal XT Amp mode
• Normal power mode
Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1840-21/29
LC877917A
Continued from preceding page.
Parameter
Symbol
Pin
Specification
Conditions
VDD[V]
Current
IDDOP(8)
consumption
during normal
VDD1=
VDD2=V2
min
typ
max
unit
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
operation
• System clock: 32.768kHz
(Note 8-1)
• Internal RC oscillation stopped.
2.4 to 3.6
8
55
2.4 to 3.6
8.5
43
2.4 to 3.6
2.3
12
• Divider: 1/1
• Normal XT amp mode
• Power save mode
IDDOP(9)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Low amp operation)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
μA
• Divider: 1/1
• Low XT amp mode
• Normal power mode
IDDOP(10)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Low amp operation)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
• Low XT Amp mode
• Power save mode
Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1840-22/29
LC877917A
Continued from preceding page.
Parameter
Symbol
Pin
Specification
Conditions
VDD[V]
Current
IDDHALT(1)
consumption
during HALT
VDD1=
VDD2=V2
min
typ
max
unit
HALT mode
• FmCF=4MHz Ceramic resonator
oscillation
mode
• FsX’tal=32.768kHz crystal oscillation
(Note 8-1)
(Normal operation)
2.4 to 3.6
510
1370
2.4 to 3.6
52
185
2.4 to 3.6
24
110
2.4 to 3.6
15
85
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped
• Divider: 1/1
• Normal power mode
IDDHALT(2)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: Fast RC oscillation
• Divider: 1/1
• Normal power mode
IDDHALT(3)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: Fast RC oscillation
• Divider: 1/1
• Power save mode
IDDHALT(4)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
μA
• System clock: Slow RC oscillation
• Divider: 1/1
• Normal power mode
IDDHALT(5)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
2.4 to 3.6
12
76
2.4 to 3.6
350
995
2.4 to 3.6
8.1
61
• System clock: Slow RC oscillation
• Divider: 1/1
• Power save mode
IDDHALT(6)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• Internal RC oscillation stopped.
• System clock: VMRC oscillation
(4MHz)
• Divider: 1/1
• Normal power mode
IDDHALT(7)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Normal operation)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
• Normall XT Amp mode
• Normal power mode
Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1840-23/29
LC877917A
Continued from preceding page.
Parameter
Symbol
Pin
Specification
Conditions
VDD[V]
Current
IDDHALT(8)
consumption
during HALT
VDD1=
VDD2=V2
min
typ
max
unit
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
mode
(Normal operation)
(Note 8-1)
• System clock: 32.768kHz
2.4 to 3.6
6.2
53
2.4 to 3.6
3.0
30
2.4 to 3.6
1.0
9.2
• Internal RC oscillation stopped.
• Divider: 1/1
• Normal XT Amp mode
• Power save mode
IDDHALT(9)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Low amp operation)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
• Low XT Amp mode
• Normal power mode
IDDHALT(10)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
(Low amp operation)
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
• Low XT Amp mode
• Power save mode
Current
IDDHOLD(1)
• CF1=VDD or open
consumption
(when using external clock)
during HOLD
μA
HOLD mode
2.4 to 3.6
0.05
26
2.4 to 3.6
5.7
56
2.4 to 3.6
0.47
25
2.4 to 3.6
11
75
mode
Current
IDDHOLD(2)
Date/time clock
consumption
HOLD mode
during
• CF1=VDD or open
Date/time clock
(when using external clock)
HOLD mode
• FmX’tal=32.768kHz crystal oscillation
• Divider: 1/1
• LCD display off
• Normal XT Amp mode
IDDHOLD(3)
Date/time clock
HOLD mode
• CF1=VDD or open
(when using external clock)
• FmX’tal=32.768kHz crystal oscillation
• Divider: 1/1
• LCD display off
• Low XT Amp mode
IDDHOLD(4)
Date/time clock
HOLD mode
• CF1=VDD or open
(when using external clock)
• FmX’tal=Slow RC oscillation
• Divider: 1/1
• LCD display off
Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
No.A1840-24/29
LC877917A
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Transfer rate
UBR
UTX(P00),
2.4 to 3.6
URX(P01)
Data length:
Stop bits :
Parity bits:
min
typ
16/3
max
unit
8192/3
tCYC
7/8/9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Start of
transmission
Stop bit
End of
transmission
Transmit data (LSB first)
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Start bit
Start of
reception
Stop bit
Receive data (LSB first)
End of
reception
UBR
No.A1840-25/29
LC877917A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
4.00MHz
Murata
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf1
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
Remarks
CSTCR4M00G53-R0
(15)
(15)
Open
1k
2.4 to 3.6
0.04
-
Internal
CSTLS4M00G53-B0
(15)
(15)
Open
1k
2.4 to 3.6
0.03
-
C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after
VDD goes above the operating voltage lower limit (see Figure 4).
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed.
• Till the oscillation gets stabilized after the HOLD mode reset.
• Till the oscillation gets stabilized after the HOLD mode reset with CFSTOP(the OCR register bit0)=0.
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
9
9
Open
-
2.4 to 3.6
1.0
2.0
Remarks
CL=7.0pF
Epson
32.768KHz
Toyocom
Normal XT
mode
MC-306
CL=7.0pF
2
2
Open
-
2.4 to 3.6
2.0
3.0
Low Amp XT
mode
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode with EXTOSC (the OCR register bit6)=1 is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as
possible because they are vulnerable to the influences of the circuit pattern.
CF2
CF1
Rf1
C1
XT2
XT1
Rf2
Rd1
C2
C3
Rd2
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1840-26/29
LC877917A
VDD
VDD limit
Power supply
0V
Reset time
RES
Internal RC
Resonator oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Execute oscillation enable command
Operating mode
Reset
Unfixed
Instruction execution mode
Reset Time and Oscillation Stabilizing Time
HOLD reset signal
Without HOLD
Release
HOLD reset signal VALID
Internal RC
Resonator oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operation mode
HOLD
HALT
HOLD Release Signal and Oscillation Stable Time
Note: External oscillation circuit is selected.
Figure 4 Oscillation Stabilization Times
No.A1840-27/29
LC877917A
VDD
Note:
External circuits for reset may vary
depending on the usage of POR. Please refer
to the user’s manual for more information.
RRES
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transmission period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transmission period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial Input/Output Wave Form
tPIL
tPIH
Figure 7 Pulse Input
No.A1840-28/29
LC877917A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
1000μs or longer
Reset period
Unknown-state
(POUKS)
RES
Figure 8 Waveform observed when POR is used
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a).
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 1000μs or longer.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of July, 2010. Specifications and information herein are subject
to change without notice.
PS No.A1840-29/29