KAF 4320 D

KAF-4320
2084 (H) x 2085 (V) Full
Frame CCD Image Sensor
Description
The KAF−4320 Image Sensor is a high performance monochrome
area CCD (charge-coupled device) image sensor designed for a wide
range of image sensing applications.
The sensor incorporates true two-phase CCD technology,
simplifying the support circuits required to drive the sensor as well as
reducing dark current without compromising charge capacity.
The sensor also utilizes the TRUESENSE Transparent Gate Electrode
to improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
The full imaging array is read out of four outputs, each of which is
driven by a low impedance two stage source follower that provides
a high conversion gain. This combination enables low noise at a net
readout rate of 12 MHz (3 MHz per output).
Table 1. GENERAL SPECIFICATIONS
Parameter
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Figure 1. KAF−4320 Full Frame CCD
Image Sensor
Typical Value
Architecture
Full Frame CCD
Total Number of Pixels
2092 (H) × 2093 (V)
Number of Active Pixels
2084 (H) × 2085 (V) = approx. 4.3 Mp
Pixel Size
24 mm (H) × 24 mm (V)
• True Two Phase Full Frame Architecture
• TRUESENSE Transparent Gate Electrode
Active Image Size
50.02 mm (H) × 50.02 mm (V)
70.7 mm (Diagonal)
645 Optical Format
Applications
Die Size
52.3 mm (H) × 52.7 mm (V)
Output Sensitivity
10 mV/e−
Saturation Signal
500,000 electrons
Readout Noise
20 electrons (3 MHz)
Outputs
4
Dark Current
< 15 pA/cm2
Dark Current Doubling
Temperature
6.4°C
Dynamic Range
20,000 : 1
Blooming Suppression
None
Maximum Date Rate
3 MHz
Package
PGA Package
Cover Glass
Clear
Features
for High Sensitivity
• Medical Imaging
• Scientific Imaging
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
KAF−4320/D
KAF−4320
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAF−4320 IMAGE SENSOR
Part Number
Description
Marking Code
KAF−4320−AAA−JP−B1
Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Grade 1
KAF−4320−AAA−JP−B2
Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Grade 2
KAF−4320−AAA−JP−AE
Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Engineering Sample
KAF−4320−AAA
Lot Number
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KAF−4320−16−3−A−EVK
Description
Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−4320
DEVICE DESCRIPTION
Architecture
H1
H2
1 4 4
H2
H1
RD
R
VDD
VOUT4
VLG
GND
OG
H1L
1042
1042
RD
R
VDD
VOUT3
VLG
VSUB
OG
H1L
4 4 1
4
V1
V2
V1
V2
V1
V2
V1
V2
KAF−4320
2084 (H) × 2085 (V)*
24 × 24 mm Pixels
4
GUARD
4
GUARD
V2
V1
V2
V1
RD
R
VDD
VOUT1
VLG
VSUB
OG
H1L
V2
V1
V2
V1
RD
R
VDD
VOUT2
VLG
VSUB
OG
H1L
4 Dark (Last VCCD Phase = TF2 → H1)
1 4 4
1042
1042
4 4 1
H1
H2
H2
H1
*The center row is predominately a 24 mm × 25 mm polysilicon pixel that splits evenly into each half of the array. Thus, each quadrant will
consist of 1046 (H) × 1047 (V) rows where the last row will contain roughly half the signal.
½ Row 1047
25 mm
Row 1045
24 mm
Row 1046
24 mm
10 mm
½ Row 1047
Row 1046
Row 1045
Figure 2. Block Diagram
24 mm
24 mm
14 mm
Poly
++
ITO
+++++
++
+++++
++++
+++++
Top Half
++
+++++
++
Bottom Half
Pixel Optical Boundary
Figure 3. Horizontal Seam Cross-Section
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KAF−4320
Image Acquisition
floating diffusion. Once the signal has been sampled by the
system electronics, the reset gate (fR) is clocked to remove
the signal and the floating diffusion is reset to the potential
applied by VRD. (See Figure 4). More signal at the floating
diffusion reduces the voltage seen at the output pin. In order
to activate the output structure, an off-chip load must be
added to the VOUT pin of the device such as shown in
Figure 6.
If charge binning is desired, the charge can be combined
at the output node or it can be combined in the fH1L gate
and then presented to the output node.
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the sensor. These photon induced
electrons are collected locally by the formation of potential
wells at each photogate or pixel site. The number of
electrons collected is linearly dependent on light level and
exposure time and non-linearly dependent on wavelength.
When the pixel’s capacity is reached, excess electrons will
leak into the adjacent pixels within the same column. This
is termed blooming. During the integration period, the fV1
and fV2 register clocks are held at a constant (low) level.
See Figure 17.
Dark Reference Pixels
There are 4 light shielded pixels at the beginning of each
line. There are 4 dark lines at the start of every frame and 4
dark lines at the end of each frame. Since there are outputs
at each of the four corners, the light shield will affect the
beginning of each line from each output, and for the first four
lines from each of the outputs. Under normal circumstances,
these pixels do not respond to light. However, dark reference
pixels in close proximity to an active pixel can scavenge
signal depending on light intensity and wavelength and
therefore will not represent the true dark signal.
Charge Transport
Referring again to Figure 17, the integrated charge from
each photogate is transported to the output using a two-step
process. Each line (row) of charge is first transported from
the vertical CCD to the horizontal CCD register using the
fV1 and fV2 register clocks. The horizontal CCD is
presented a new line on the falling edge of fV2 while fH1
is held high. The horizontal CCD then transports each line,
pixel by pixel, to the output structure by alternately clocking
the fH1 and fH2 pins in a complementary fashion. On each
falling edge of fH1L a new charge packet is transferred onto
a floating diffusion and sensed by the output amplifier.
Dummy Pixels
Within the horizontal shift register are 4−1/2 leading
pixels that are not associated with a column of pixels within
the vertical register. These pixels contain only horizontal
shift register dark current signal and do not respond to light.
A few leading dummy pixels may scavenge false signal
depending on operating conditions.
Output Structure
Charge presented to the floating diffusion is converted
into a voltage and current amplified in order to drive off-chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the
H2
H1
H2
HCCD
Charge
Transfer
H1
VDD
VOG
R
VRD
Floating
Diffusion
VOUT
VLG
Source
Follower
#1
Figure 4. Output Architecture
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4
Source
Follower
#2
KAF−4320
Physical Description
Gnd
fR
OG
fH1L
fH1
Gnd
fH2
Gnd
Gnd
Gnd
Gnd
Gnd
fH2
fH1
OG
fH1L
fR
Gnd
Pin Description and Device Orientation
52 51 50 49 48 47 46 45 44
61 60 59 58 57 56 55 54 53
VRD
62
43
VRD
VLG
63
42
VLG
VSS
64
41
VSS
GND
65
40
GND
VOUT4
66
39
VOUT3
VDD
67
38
VDD
fV2
68
37
fV2
fV1
69
36
fV1
GND
70
35
GND
fV1
71
34
fV1
fV2
72
33
fV2
GUARD
73
32
GUARD
fV2
74
31
fV2
fV1
75
30
fV1
GND
76
29
GND
fV1
77
28
fV1
fV2
78
27
fV2
VDD
79
26
VDD
VOUT1
80
25
VOUT2
GND
81
24
GND
VSS
82
23
VSS
VLG
83
22
VLG
VRD
84
21
VRD
Figure 5. Pinout Diagram
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5
fR
Gnd
Gnd
Gnd
OG
fH2
11 12 13 14 15 16 17 18 19 20
fH1L
fH1
10
fH1
fH1L
9
fH2
8
Gnd
7
Gnd
6
Gnd
5
N/C
4
N/C
3
Gnd
2
fR
Gnd
1
OG
Pin 1
KAF−4320
Table 4. PIN DESCRIPTION
Pin
Name
Substrate (Ground)
43
VRD
Reset Drain
Reset Clock
44
GND
Substrate (Ground)
VOG
Output Gate Bias
45
fR
4
fH1L
Horizontal CCD Clock − Last Phase
46
VOG
Output Gate Bias
5
fH1
Horizontal CCD Clock − Phase 1
47
fH1L
Horizontal CCD Clock − Last Phase
6
fH2
Horizontal CCD Clock − Phase 2
48
fH1
Horizontal CCD Clock − Phase 1
7
GND
Substrate (Ground)
49
fH2
Horizontal CCD Clock − Phase 2
8
GND
Substrate (Ground)
50
GND
Substrate (Ground)
9
GND
Substrate (Ground)
51
GND
Substrate (Ground)
10
N/C
No Connect
52
GND
Substrate (Ground)
11
N/C
No Connect
53
GND
Substrate (Ground)
12
GND
Substrate (Ground)
54
GND
Substrate (Ground)
13
GND
Substrate (Ground)
55
GND
Substrate (Ground)
14
GND
Substrate (Ground)
56
fH2
Horizontal CCD Clock − Phase 2
15
fH2
Horizontal CCD Clock − Phase 2
57
fH1
Horizontal CCD Clock − Phase 1
16
fH1
Horizontal CCD Clock − Phase 1
58
fH1L
Horizontal CCD Clock − Last Phase
17
fH1L
Horizontal CCD Clock − Last Phase
59
VOG
Output Gate Bias
18
VOG
Output Gate Bias
60
fR
19
fR
Reset Clock
61
GND
Substrate (Ground)
20
GND
Substrate (Ground)
62
VRD
Reset Drain
VLG
Source Follower Load Gate Bias
Pin
Name
1
GND
2
fR
3
Description
Description
Reset Clock
Reset Clock
21
VRD
Reset Drain
63
22
VLG
Source Follower Load Gate Bias
64
VSS
Amplifier Supply Return
23
VSS
Amplifier Supply Return
65
GND
Substrate (Ground)
24
GND
Substrate (Ground)
66
VOUT4
Amplifier Output
25
VOUT2
Amplifier Output
67
VDD
Amplifier Supply
26
VDD
Amplifier Supply
68
fV2
Vertical CCD Clock − Phase 2
27
fV2
Vertical CCD Clock − Phase 2
69
fV1
Vertical CCD Clock − Phase 1
28
fV1
Vertical CCD Clock − Phase 1
70
GND
Substrate (Ground)
29
GND
Substrate (Ground)
71
fV1
Vertical CCD Clock − Phase 1
30
fV1
Vertical CCD Clock − Phase 1
72
fV2
Vertical CCD Clock − Phase 2
31
fV2
Vertical CCD Clock − Phase 2
73
GUARD
32
GUARD
Guard Ring
74
fV2
Vertical CCD Clock − Phase 2
33
fV2
Vertical CCD Clock − Phase 2
75
fV1
Vertical CCD Clock − Phase 1
34
fV1
Vertical CCD Clock − Phase 1
76
GND
Substrate (Ground)
35
GND
Substrate (Ground)
77
fV1
Vertical CCD Clock − Phase 1
36
fV1
Vertical CCD Clock − Phase 1
78
fV2
Vertical CCD Clock − Phase 2
37
fV2
Vertical CCD Clock − Phase 2
79
VDD
Amplifier Supply
VOUT1
Amplifier Output
Guard Ring
38
VDD
Amplifier Supply
80
39
VOUT3
Amplifier Output
81
GND
Substrate (Ground)
40
GND
Substrate (Ground)
82
VSS
Amplifier Supply Return
41
VSS
Amplifier Supply Return
83
VLG
Source Follower Load Gate Bias
Source Follower Load Gate Bias
84
VRD
Reset Drain
42
VLG
1. Like named pins (e.g. VSS) should be connected to the same supply.
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KAF−4320
IMAGING PERFORMANCE
Electro-Optical Specifications
All values measured at 25°C, and nominal operating conditions. These parameters exclude defective pixels.
Table 5. SPECIFICATIONS
Description
Saturation Signal
Vertical CCD Capacity
Horizontal CCD Capacity
Output Node Capacity
Symbol
Min.
Nom.
Max.
−
−
500,000
650,000
850,000
550,000
−
−
−
−
−
−
NSAT
Quantum Efficiency (see Figure 6)
Units
Notes
Verification
Plan
e−/pix
1
Design10
Design10
Photoresponse Non-Linearity
PRNL
−
< 1.0
2.0
%
2
Design10
Photoresponse Non-Uniformity
PRNU
−
0.8
2.0
%
3
Design10
G
−
0.2
5
%
8
Die9
JDARK
−
2,507
54,015
e−/pix/sec
4
Die9
−
6.3
7
°C
5
Die9
6
Design10
Channel to Channel Gain Difference
Dark Signal
Dark Signal Doubling Temperature
Design10
DSNU
−
300
540
e−/pix/sec
DR
86
87.5
−
dB
Output Amplifier DC Offset
VODC
VRD − 4
VRD − 3
VRD − 2
V
Die9
Output Amplifier Sensitivity
VOUT/Ne−
9
10
11
mV/e−
Design10
ZOUT
−
150
−
W
Die9
ne−
−
17
24
electrons
Dark Signal Non-Uniformity
Dynamic Range
Output Amplifier Output Impedance
Noise Floor
7
Design10
1. The maximum output video amplitude limits the charge capacity and dynamic range. The maximum charge capacity is determined from
a photon transfer measurement and is defined as the point where the mean-variance fails to demonstrate the theoretical behavior.
2. Worst case deviation from straight line fit, between 0.1% and 95% of VSAT.
3. One Sigma deviation of a 1042 × 1042 sample (data from one output) when the CCD is illuminated uniformly at half of saturation, excluding
defective pixels. [100 ⋅ (Std Deviation / Average)]
4. Average of all pixels with no illumination at 25°C.
5. Average dark signal of any of 16 × 16 blocks within the sensor (each block is 130 × 130 pixels).
6. The dynamic range limited by the noise of the output amplifier (i.e. at temperatures less than –10°C), pixel frequency = 3 MHz, and
bandwidth = 10 MHz.
7. Noise floor of the CCD amplifier assuming correlated double sampling, pixel frequency = 3 MHz, and bandwidth = 10 MHz.
8. DG = abs (100 ⋅ (1 – [response of a channel] / [average response of all four channels])). The specified gain difference is the combination
of all the gain errors on the CCD sensor and the analog signal processing in the test system.
9. A parameter that is measured on every sensor during production testing.
10. A parameter that is quantified during the design verification activity.
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KAF−4320
TYPICAL PERFORMANCE CURVES
KAF−4320
1
0.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
400
500
600
700
800
900
1,000
1,100
Wavelength (nm)
Figure 6. Typical Spectral Response
KAF−4320 Dark Current
1,000
Measured
TDBL = 6.4°C
100
e−/Pix/Sec
Absolute Quantum Efficiency
0.8
10
1
−20
−10
0
10
20
Temperature (5C)
Figure 7. Dark Current Temperature Dependence
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8
30
1,200
KAF−4320
Linearity
Figure 8 shows a typical result from measuring the signal
response as a function of integration time, while the
illumination level is constant. The data is fit in log space to
give equal weighting between low and high signal levels.
A perfectly linear system would have a slope of 1.00 in log
space. The slope in the fit is allowed to deviate from the ideal
by a small amount. Typical values of the slope are between
1.00 and 1.02. The deviation from linear is defined as:
Ť
% Dev + 100 @
[Measured Value − Fit Value]
Fit Value
1,000,000
Measured
Fit
100,000
% Dev from Fit
Signal (e−/Pixel)
10,000
1,000
100
10
1
0.1
0.01
1
10
100
1,000
Time (ms)
Figure 8. Linearity
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9
10,000
100,000
Ť
KAF−4320
CCD Output
The following figures show typical CCD video at the
output of the CCD and at the input of the analog to digital
converter (A/D) in the test system. Bandwidth limiting is
applied at the A/D input to minimize the noise floor.
Figure 9. CCD Output: Small Signal
Figure 10. CCD Output: Large Signal
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10
KAF−4320
Noise
between the expected and measured results for the CCD
alone and the CCD in the system at 1 MHz and 3 MHz.
The values in the table are in electrons referred to the CCD
amplifier input.
The CCD amplifier noise floor, the CCD dark current
during readout, and other system components such as the
analog-digital converter dictate the total system noise.
CCD Amplifier
The noise contributed by the output amplifier is
determined from the amplifier’s noise power spectrum,
the system bandwidth, and any other analog processing.
Correlated double sampling is a standard analog processing
technique used with CCDs and it is assumed that it is used
for all of the rest of the calculations and results in this
document.
Table 6.
Frequency
CCD Measured
Noise
CCD + System Datel
ADS93x Measured
1.00E+06
12
16.2
3.00E+06
17.3
22.6
Temperature Dependance of the Noise Floor
The temperature dependence of the noise floor is dictated
primarily by the dark current generated during the readout
time for the CCD. Figure 12 and Figure 13 show the
expected dynamic range as a function of temperature for two
pixel rates, 3 MHz and 1 MHz. The dynamic range was
calculated using the measured amplifier and system noise
values, the expected dark current performance, and the
saturation signal. At 25°C, the dark current shot noise can
contribute from 12 to 50 electrons and dominate the noise
floor. The maximum dynamic range can be achieved at
temperatures < −10°C for these read out frequencies.
System Noise
The total noise will be the combination of the CCD noise
and the noise contributed by other components in the
processing circuitry. The total noise, dominated by the CCD
and the A/D converter is also shown in Figure 11.
The measured vales were obtained using a system that
employed Datel 16 bit analog to digital converters,
the ADS931 and ADS933. The system noise obtained
matched the Datel specifications exactly and was similar
and slightly lower than the CCD noise contribution.
The table below shows the results and good agreement
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11
KAF−4320
Noise vs. Frequency
Pixel Rate Dependency of Noise
25
Noise (electrons)
20
15
10
CCD Noise − Measured
CCD + System − Measured
5
CCD Noise Measured
0
0.0E+00
1.0E+06
2.0E+06
3.0E+06
4.0E+06
Pixel Rate (MHz)
Figure 11. Noise vs. Pixel Rate
Performance vs. Temperature
KAF−4320 System Dynamic Range
16
15.5
Dynamic Range (Bits)
15
14.5
14
13.5
13
12.5
Total System
CCD
0
20
12
−50
−40
−30
−20
−10
10
Temperature (5C)
Total System Noise: CCD Readout Dark Current + CCD Amplifier + A/D Converter
(Datel 933 16 Bit Converter)
Figure 12. Noise vs. Temperature − 3 MHz Pixel Rate
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12
30
KAF−4320
KAF−4320 System Dynamic Range
16
15.5
Dynamic Range (Bits)
15
14.5
14
13.5
13
12.5
Total System
CCD
0
20
12
−50
−40
−30
−20
−10
10
Temperature (5C)
Total System Noise: CCD Readout Dark Current + CCD Amplifier + A/D Converter
(Datel 933 16 Bit Converter)
Figure 13. Noise vs. Temperature − 1 MHz Pixel Rate
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13
30
KAF−4320
DEFECT DEFINITIONS
Table 7. SPECIFICATIONS (Cosmetic tests performed at T = 25°C)
Grade
Point Defects
Cluster Defects
Columns
Double Columns
C1
< 50
< 20
0
0
C2
< 100
< 20
<4
0
Point Defects
Dark: A pixel which deviates by more than 6% from
neighboring pixels when illuminated to 70% of saturation.
Bright: A pixel with a dark current greater than
5,000 e−/pixel/sec at 25°C.
Neighboring Pixels
The surrounding 128 × 128 pixels or ±64 columns/rows.
Defect Separation
Column and cluster defects are separated by no less than
two (2) pixels in any direction (excluding single pixel
defects).
Cluster Defect
A grouping of not more than 5 adjacent point defects.
Cluster defects are separated by no less than 2 pixels from
other column and cluster defects.
Column Defect
A grouping of > 5 contiguous point defects along a single
column.
Column defects are separated by no less than 5 pixels from
other column defects.
A column containing a pixel with dark current
> 100,000 e−/pix/sec (Bright column).
A column that does not meet the minimum vertical CCD
charge capacity (Low charge capacity column).
A column that loses > 3,500 e− under 2 ke− illumination
(Trap defect).
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KAF−4320
OPERATION
Table 8. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Diode Pin Voltages
VDIODE
0
25
V
1, 2
Gate Pin Voltages − Type 1
VGATE1
−17
17
V
1, 3, 6
Gate Pin Voltages − Type 2
VGATE2
0
17
V
1, 4, 6
IOUT
−
−10
mA
5
CLOAD
−
15
pF
5
Output Bias Current
Output Load Capacitance
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to pin VSUB or between each pin in this group.
2. Includes pins: VRD, VDD, VSS, VOUT.
3. Includes pins: fV1, fV2, fH1, fH2, fH1L.
4. Includes pins: VOG, VLG, fR.
5. Avoid shorting output pins to ground or any low impedance source during operation.
6. This sensor contains gate protection circuits to provide protection against ESD events. The circuits will turn on when greater than 18 volts
appears between any two gate pins. Permanent damage can result if excessive current is allowed to flow under these conditions.
Equivalent Input Circuits
Many of the pins contain a form of gate protection to
prevent damage from electrostatic discharge. These take the
form of zener diodes that prevent the voltage differences
between gates from becoming large enough to damage the
sensor. Isolated gates such as fR and VLG require only
protection between the gate and the sensor substrate.
fH1
fV1
fH2
fV2
fH1L
Sub
VOG
Sub
fR
Sub
Sub
VLG
Figure 14. Equivalent Input Circuits
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KAF−4320
Table 9. DC BIAS OPERATING CONDITIONS
Symbol
Minimum
Nominal
Maximum
Units
Maximum DC
Current (mA)
Notes
Reset Drain
VRD
−
18.5
−
V
0.01
2
Output Amplifier Return
VSS
−
2.0
−
V
1
3
Output Amplifier Supply
VDD
−
21
−
V
IOUT
2
Substrate
GND
−
0
−
V
−
Output Gate
VOG
−
0
−
V
0.01
Output Amplifier Load Gate
VLG
VSS
VSS + 1.0
VSS + 1.2
V
0.01
GUARD
−
10
−
V
−
3
IOUT
−
−5
−10
mA
−
1
Description
Guard Ring
Amplifier Output Current
3
1. An output load sink must be applied to VOUT to provide a constant current source and activate the output amplifier − see Figure 15.
2. Voltage tolerance is 2% (actual voltage should be nominal ± tolerance).
3. Voltage tolerance is 5% (actual voltage should be nominal ± tolerance).
VDD
0.1 mF
~5ma
VOUT
2N3904 or Equivalent
Buffered Output
140 W
1 kW
Figure 15. Example Output Structure Load Diagram
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KAF−4320
AC Operating Conditions
Table 10. CLOCK LEVELS
Description
Vertical CCD Clock − Phase 1
Vertical CCD Clock − Phase 2
Horizontal CCD Clock − Phase 1
Horizontal CCD Clock − Last Gate
Horizontal CCD Clock − Phase 2
Reset Clock
1.
2.
3.
4.
5.
6.
7.
Effective
Capacitance
Symbol
Level
Nominal
Units
fV1
Low
−8.0
V
4, 5
Clock Amplitude
8.0
75 nF
(Each of fV1 Pins 30, 34, 71, 75)
Low
−8.0
V
4, 5
Clock Amplitude
8.0
75 nF
(Each of fV2 Pins 31, 33, 72, 74)
V
150 nF
(Each of fH1 Pins 5, 16, 48, 57)
3, 6
V
10 pF
3
V
100 pF
3, 7
V
5 pF
3
fV2
fH1
fH1L
fH2
fR
Low
0
Clock Amplitude
10.0
Low
−3.0
Clock Amplitude
10.0
Low
−3.0
Clock Amplitude
10.0
Low
2.0
Clock Amplitude
12.0
Notes
All pins draw less than 10 mA DC current.
Capacitance values relative to VSUB.
Voltage tolerance is 2% (actual voltage should be nominal ± tolerance).
Voltage tolerance is 5% (actual voltage should be nominal ± tolerance).
Total clock capacitance is 4 ⋅ 75 nF = 300 nF.
Total clock capacitance is 4 ⋅ 150 pF = 600 pF.
Total clock capacitance is 4 ⋅ 100 pF = 400 pF.
AC Timing Conditions
Table 11. AC TIMING CONDITIONS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
fH1, fH2 Clock Frequency
fH
−
3
3
MHz
1, 2, 3
Pixel Period (1 Count)
te
333
333
−
ns
fH1, fH2 Set-up Time
tfHS
10
10
−
ms
fV1, fV2 Clock Pulse Width
tfV
30
30
−
ms
2
Reset Clock Pulse Width
tfR
−
20
−
ns
4
tREADOUT
470.3
470.3
−
ms
5
Integration Time
tINT
−
−
−
Line Time
tLINE
449.6
449.6
−
Readout Time
6
ms
7
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Crossover of register clocks should be between 40−60% of
amplitude.
4. fR should be clocked continuously.
5. tREADOUT = (1046 ⋅ tLINE)
6. Integration time (tINT) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot
noise.
7. tLINE = (3 ⋅ tfV) + tfHS + (1050⋅ te).
8. When combining the image from the upper half of the device with that from the lower half, line 1047 from each must be added together and
gained (approx. 1.2X) to match the other 1046 lines.
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17
KAF−4320
this figure were generated using a 50 W output impedance
clock driver. Excessively fast clocks can result in a higher
noise floor.
Pixel Rate Clock Waveforms
For best performance, the horizontal clocks should be
damped, similar to those shown in Figure 16. The clocks in
Figure 16. Clock Example
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KAF−4320
TIMING
Normal Read Out
Frame Timing − per Quadrant (Each Output Contains One Half of the Line)
tINT
tREADOUT
1 Frame = 1046 Lines
fV1
Line
fV2
1
2
1045
1046
fH1,
fH1L
fH2
Line Timing
Pixel Timing
tfV
tfR
fR
fV1
tfV
fH1,
fH1L
fV2
tfHS
te
fH1,
fH1L
fH2
te
fH2
1 Count
VPIX
1050 Counts
VOUT
fR
VSAT
VDARK
VODC
VSUB
Line Content − per Quadrant (Each Output Contains
One Half of the Line)
1−4 5−8
Photoactive
VSAT
VDARK
9−1050
VPIX
VODC
VSUB
Dummy Pixels
Saturated pixel video output
Video output signal in no-light situation
(not zero due to JDARK and HCLOCK feedthrough)
Pixel video output signal level,
more electrons = more positive*
Video level offset with respect to VSUB
Analog ground
* See Image Acquisition section.
Dark Reference
Figure 17. Timing Diagrams
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KAF−4320
Power Dissipation
voltage drop is VDD – VSS. The second stage sources much
more current, approximately 5 mA while the voltage drop
on the sensor is much smaller, VDD – VOUT where
VOUT ~ VRD.
The power dissipated by the CCD clocks is calculated
using the formula:
Power + C @ V 2 @ f
Total Power
The table below shows the power dissipated at three
different pixel frequencies. For each of these cases the
amplifier operating conditions are held constant so its
contribution is not frequency dependent. The time for the
vertical clock transfers is also held constant
(90 microseconds per line) but the line time changes
depending on the pixel rate.
Where C is the capacitance in farads, V is the clock
amplitude in volts, and f is the frequency in Hz.
Amplifier Power
The power dissipated by amplifiers is calculated by
Power = I ⋅ V where I is the current and V is the voltage drop
on the CCD. The sensor contains two stage source followers.
The first stage draws approximately 250 micro amps and the
Table 12. TOTAL POWER
Pixel Rate
500 kHz
1 MHz
3 MHz
Notes
Amplifiers
120 mW
120 mW
120 mW
Total of 4 Outputs
HCCD
60 mW
120 mW
360 mW
VCCD
62 mW
121 mW
297 mW
Total
241 mW
361 mW
776 mW
Contributor
CCD Surface Flatness
The flatness of the die is defined as a peak-to-peak
distortion in the image sensor surface. The parallelism
between the image sensor surface and any of the package
components
is
not
specified
or
guaranteed.
The non-parallelism is removed when measuring the
distortion in the image sensor surface.
Table 13.
Die Flatness
Peak-to-Peak Distortion
Minimum
Nominal
Maximum
Unit
−
8.8
12.0
microns
Some examples of profiles of some typical image sensors surfaces are shown below.
Figure 18. Die Flatness Data
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20
KAF−4320
Figure 19. Die Flatness Data
Figure 20. Die Flatness Data
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KAF−4320
STORAGE AND HANDLING
Table 14. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
TST
−100
80
°C
1
Operating Temperature
TOP
−70
50
°C
1. Image sensors with temporary cover glass should be stored at room temperature (nominally 25°C) in dry nitrogen.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
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KAF−4320
MECHANICAL INFORMATION
Completed Assembly
Figure 21. Completed Assembly (1 of 2)
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KAF−4320
Figure 22. Completed Assembly (2 of 2)
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KAF−4320
ON Semiconductor and the
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