KAF 6303 D

KAF-6303
3072 (H) x 2048 (V) Full
Frame CCD Image Sensor
Description
The KAF−6303 Image Sensor is a high performance CCD
(charge-coupled device) with 3072 (H) × 2048 (V) photo active pixels
designed for a wide range of image sensing applications.
The sensor incorporates true two-phase CCD technology,
simplifying the support circuits required to drive the sensor as well as
reducing dark current without compromising charge capacity.
The sensor also utilizes the TRUESENSE Transparent Gate Electrode
to improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Full Frame CCD
Total Number of Pixels
3088 (H) × 2056 (V)
Number of Active Pixels
3072 (H) × 2048 (V) = approx. 6.3 Mp
Pixel Size
9 mm (H) × 9 mm (V)
Active Image Size
27.65 mm (H) × 18.48 mm (V)
33.4 mm (Diagonal)
APS−H Optical Format
Figure 1. KAF−6303 Full Frame CCD
Image Sensor
Features
• True Two Phase Full Frame Architecture
• TRUESENSE Transparent Gate Electrode
Chip Size
29.0 mm (H) × 19.1 mm (V)
Saturation Signal
100,000 e−
Output Sensitivity
10 mV/e−
Quantum Efficiency
(450, 550, 650 mm)
40%, 52%, 65%
Readout Noise (10 MHz)
15 e− rms
Dark Current
(Accumulation Mode)
< 10 pA/cm2
Dark Current Doubling Rate
6°C
Dynamic Range
(Saturation Signal/Dark Noise)
76 dB
Maximum Date Rate
10 MHz
Package
CERDIP Package (Sidebrazed)
Cover Glass
Clear or AR Coated, 2 Sides
•
•
for High Sensitivity
100% Fill Factor
Low Dark Current
Applications
• Medical Imaging
• Scientific Imaging
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
KAF−6303/D
KAF−6303
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAF−6303 IMAGE SENSOR
Part Number
Description
Marking Code
KAF−6303−AAA−CD−B2
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 2
KAF−6303−AAA−CD−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAF−6303−AAA−CP−B2
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Grade 2
KAF−6303−AAA−CP−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Sample
KAF−6303−AAA
Serial Number
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KAF−6303−12−5−A−EVK
Description
Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−6303
DEVICE DESCRIPTION
Architecture
4 Dark Lines
fV1
fV2
KAF−6303
Usable Active Image Area
3072 (H) × 2048 (V)
9 × 9 mm Pixels
3:2 Aspcet Ratio
VRD
fR
VDD
VOUT
VSS
Sub
ÉÉ
GUARD
3072 Active Pixels/Line
6 Dark
10 Dark
10 Inactive
ÉÉ
4 Dark Lines
fH1
fH2
2 Inactive
VOG
Figure 2. Block Diagram
contain only horizontal shift register dark current signal and
do not respond to light. A few leading dummy pixels may
scavenge false signal depending on operating conditions.
The sensor consists of 3,088 parallel (vertical) CCD shift
registers each 2,056 elements long. These registers act as
both the photosensitive elements and as the transport circuits
that allow the image to be sequentially read out of the sensor.
The elements of these registers are arranged into
a 3,072 × 2,048 photosensitive array surrounded by a light
shielded dark reference of 16 columns and 8 rows.
The parallel (vertical) CCD registers transfer the image one
line at a time into a single 3,100 element (horizontal) CCD
shift register. The horizontal register transfers the charge to
a single output amplifier. The output amplifier is a two-stage
source follower that converts the photo-generated charge to
a voltage for each pixel.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the sensor. These photon-induced
electrons are collected locally by the formation of potential
wells at each photogate or pixel site. The number of
electrons collected is linearly dependent on light level and
exposure time and non-linearly dependent on wavelength.
When the pixel’s capacity is reached, excess electrons will
leak into the adjacent pixels within the same column. This
is termed blooming. During the integration period, the fV1
and fV2 register clocks are held at a constant (low) level.
See Figure 8.
Dark Reference Pixels
Surrounding the peripheral of the device is a border of
light shielded pixels. This includes 6 leading and 10 trailing
pixels on every line excluding dummy pixels. There are also
4 full dark lines at the start of every frame and 4 full dark
lines at the end of each frame. Under normal circumstances,
these pixels do not respond to light. However, dark reference
pixels in close proximity to an active pixel, or the outer
bounds of the chip (including the first two lines out), can
scavenge signal depending on light intensity and
wavelength and therefore will not represent the true dark
signal.
Charge Transport
Referring again to Figure 8, the integrated charge from
each photogate is transported to the output using a two-step
process. Each line (row) of charge is first transported from
the vertical CCD’s to the horizontal CCD register using the
fV1 and fV2 register clocks. The horizontal CCD is
presented a new line on the falling edge of fV2 while fH1
is held high. The horizontal CCD’s then transport each line,
pixel by pixel, to the output structure by alternately clocking
the fH1 and fH2 pins in a complementary fashion. On each
falling edge of fH2, a new charge packet is transferred onto
a floating diffusion and sensed by the output amplifier.
Dummy Pixels
Within the horizontal shift register are 10 leading and 2
trailing additional shift phases that are not associated with
a column of pixels from the vertical register. These pixels
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3
KAF−6303
Horizontal Register
Output Structure
Charge presented to the floating diffusion (FD) is
converted into a voltage and current amplified in order to
drive off-chip loads. The resulting voltage change seen at the
output is linearly related to the amount of charge placed on
FD. Once the signal has been sampled by the system
electronics, the reset gate (fR) is clocked to remove the
signal and FD is reset to the potential applied by VRD. More
signal at the floating diffusion reduces the voltage seen at the
output pin. In order to activate the output structure,
an off-chip load must be added to the VOUT pin of the
device. See Figure 3.
15 V
0.1 mF
~5ma
VOUT
2N3904 or Equivalent
Buffered Output
140 W
1 kW
Figure 3. Typical Output Structure Load Diagram
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4
KAF−6303
Physical Description
Pin Description and Device Orientation
VSUB 1
26 VSUB
Pin 1
VOUT 2
25 VOG
Pixel 1,1
VDD
3
24 GUARD
VRD
4
23 fV1
fR
5
22 fV1
VSS 6
21 fV2
N/C 7
20 fV2
N/C 8
19 fV2
N/C 9
18 fV2
fH1 10
17 fV1
fH2 11
16 fV1
N/C 12
15 VSUB
VSUB 13
14 VSUB
Figure 4. Pinout Diagram
NOTE: The KAF−1603 is mechanically the same and electrically identical to the KAF−0402 sensor. It is also mechanically the same as the
KAF−0261 and KAF−3200 sensors. There are some electrical differences since the KAF−0261 has two outputs and two additional clock
inputs. The KAF−3200 requires that pin 11 be a “No connect” and be electrically floating. Refer to their specifications for details.
Table 4. PIN DESCRIPTION
Pin
Name
Substrate (Ground)
14
VSUB
Substrate (Ground)
Video Output
15
VSUB
Substrate (Ground)
Amplifier Supply
16
fV1
Vertical CCD Clock − Phase 1
VRD
Reset Drain
17
fV1
Vertical CCD Clock − Phase 1
5
fR
Reset Clock
18
fV2
Vertical CCD Clock − Phase 2
6
VSS
Amplifier Supply Return
19
fV2
Vertical CCD Clock − Phase 2
7
N/C
No Connection (Open Pin)
20
fV2
Vertical CCD Clock − Phase 2
8
N/C
No Connection (Open Pin)
21
fV2
Vertical CCD Clock − Phase 2
9
N/C
No Connection (Open Pin)
22
fV1
Vertical CCD Clock − Phase 1
10
fH1
Horizontal CCD Clock − Phase 1
23
fV1
Vertical CCD Clock − Phase 1
11
fH2
Horizontal CCD Clock − Phase 2
24
GUARD
Guard Ring
12
N/C
No Connection (Open Pin)
25
VOG
Output Gate
13
VSUB
Substrate (Ground)
26
VSUB
Substrate (Ground)
Pin
Name
1
VSUB
2
VOUT
3
VDD
4
Description
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5
Description
KAF−6303
IMAGING PERFORMANCE
Table 5. SPECIFICATIONS
(All values measured at 25°C, and nominal operating conditions. These parameters exclude defective pixels.)
Description
Unit
Notes
Verification
Plan
e-/Pixel
1
Design11
Min.
Nom.
Max.
85,000
170,000
190,000
100,000
200,000
220,000
120,000
240,000
240,000
RR
RG
RB
52
42
30
65
52
40
75
62
48
Photoresponse Non-Linearity
PRNL
−
1.0
2.0
%
2
Design11
Photoresponse Non-Uniformity
PRNU
−
1.0
3.0
%
3
Die10
Dark Signal
JDARK
−
−
15
3.5
50
10
e-/Pix/Sec
pA/cm2
4
Die10
5.0
6.3
7.5
°C
DSNU
−
10
50
e-/Pix/Sec
5
Die10
Dynamic Range
DR
70
76
−
dB
6
Design11
Charge Transfer Efficiency
CTE
0.99997
0.99999
−
Output Amplifier DC Offset
VODC
9.5
10.5
11.5
V
7
Die10
Output Amplifier Bandwidth
f−3dB
−
45
−
MHz
8
Design11
Output Amplifier Sensitivity
VOUT/Ne-
9
10
11
mV/e-
Design11
ZOUT
175
200
2,520
W
Design11
20
e-
Saturation Signal
Vertical CCD Capacity
Horizontal CCD Capacity
Output Node Capacity
Quantum Efficiency
Red
Green
Blue
Symbol
NSAT
Dark Signal Doubling Temperature
Dark Signal Non-Uniformity
Output Amplifier Output Impedance
Noise Floor
Design11
%QE
ne-
−
15
Design11
Die10
9
Die10
1. For pixel binning applications, electron capacity up to 330,000 can be achieved with modified CCD inputs. Each sensor may have to be
optimized individually for these applications. Some performance parameters may be compromised to achieve the largest signals.
2. Worst-case deviation from straight line fit, between 1% and 90% of VSAT.
3. One Sigma deviation of a 128 × 128 sample when CCD illuminated uniformly.
4. Average of all pixels with no illumination at 25°C.
5. Average dark signal of any of 12 × 8 blocks within the sensor (each block is 128 × 128 pixels).
6. 20Log (NSAT / ne-) at nominal operating frequency and 25°C.
7. Video level offset with respect to ground.
8. Last output amplifier stage only. Assumes 10 pF off-chip load.
9. Output noise at 25°C, nominal operating frequency, and tINT = 0.
10. A parameter that is measured on every sensor during production testing.
11. A parameter that is quantified during the design verification activity.
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6
KAF−6303
TYPICAL PERFORMANCE CURVES
Spectral Response
0.7
0.6
Quantum Efficiency
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
Wavelength (nm)
Figure 5. Typical Spectral Response
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7
900
1,000
1,100
KAF−6303
DEFECT DEFINITIONS
Table 6. SPECIFICATIONS (All tests performed at T = 25°C)
Point Defect
Cluster Defect
Column Defect
Classification
Total
Zone A
Total
Zone A
Total
Zone A
C2
≤ 90
≤ 45
≤ 36
≤ 18
0
0
Neighboring Pixels
The surrounding 128 × 128 pixels or ±64 columns/rows.
Point Defects
Dark: A pixel which deviates by more than 6% from
neighboring pixels when illuminated to 70% of saturation.
Bright: A pixel with a dark current greater than
10,000 e−/pixel/sec at 25°C.
Defect Separation
Column and cluster defects are separated by no less than
two (2) pixels in any direction (excluding single pixel
defects).
Cluster Defect
A grouping of not more than 5 adjacent point defects.
Defect Region Exclusion
Defect region excludes the outer two (2) rows and
columns at each side/end of the sensor.
Column Defect
A grouping of > 5 contiguous point defects along a single
column.
A column containing a pixel with dark current
> 30,000 e−/pix/sec at 25°C (Bright column).
A column that does not meet the CTE specification for all
exposures less than the specified Max sat. signal level and
greater than 2 ke−.
A column that loses > 250 e− under 2 ke− illumination.
1, 2048
3072, 2048
1024, 1536
2048, 1536
Zone A
Center 1024 × 1024 Pixels
1024, 512
2048, 512
1, 1
3072, 1
Figure 6. Active Pixel Region
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8
KAF−6303
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Unit
Notes
Diode Pin Voltages
VDIODE
0
20
V
1, 2
Gate Pin Voltages − Type 1
VGATE1
−16
16
V
1, 3
Gate Pin Voltages − Type 2
VGATE2
0
16
V
1, 4
Inter-Gate Voltages
Vg−g
−
16
V
5
Output Bias Current
IOUT
−
−10
mA
6
CLOAD
−
15
pF
6
Storage Temperature
TST
0
70
°C
Humidity
RH
5
90
%
Output Load Capacitance
7
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to pin VSUB.
2. Includes pins: VRD, VDD, VSS, VOUT, GUARD.
3. Includes pins: fV1, fV2, fH1, fH2.
4. Includes pins: fR, VOG.
5. Voltage difference between overlapping gates. Includes: fV1 to fV2, fH1 to fH2, fV2 to fH1, fH2 to VOG.
6. Avoid shorting output pins to ground or any low impedance source during operation.
7. T = 25°C. Excessive humidity will degrade MTTF.
Table 8. DC BIAS OPERATING CONDITIONS
Description
Reset Drain
Symbol
Minimum
Nominal
Maximum
Unit
Maximum DC
Current (mA)
VRD
10.5
11.0
11.5
V
0.01
Output Amplifier Return
VSS
1.5
2.0
2.5
V
0.45
Output Amplifier Supply
VDD
14.5
15
15.5
V
IOUT
Substrate
VSUB
0
0
0
V
0.01
Output Gate
VOG
3.75
4.0
5.0
V
0.01
Guard Ring
VLG
8.0
10.0
12.0
V
0.01
Video Output Current
IOUT
−
−5
−10
mA
−
Notes
1
1. An output load sink must be applied to VOUT to activate output amplifier − see Figure 3.
AC Operating Conditions
Table 9. CLOCK LEVELS
Symbol
Level
Min.
Nom.
Max.
Unit
Effective
Capacitance
Vertical CCD Clock − Phase 1
fV1
Low
−10.5
−10
−9.5
V
82 nF (All fV1 Pins)
Vertical CCD Clock − Phase 1
fV1
High
0.5
1.0
1.5
V
82 nF (All fV1 Pins)
Vertical CCD Clock − Phase 2
fV2
Low
−10.5
−10.0
−9.5
V
820 nF (All fV2 Pins)
Vertical CCD Clock − Phase 2
fV2
High
0.5
1.0
1.5
V
820 nF (All fV2 Pins)
Horizontal CCD Clock − Phase 1
fH1
Low
−6.0
−3.0
−3.0
V
400 pF
Horizontal CCD Clock − Phase 1
fH1
High
4.0
7.0
7.0
V
400 pF
Horizontal CCD Clock − Phase 2
fH2
Low
−6.0
−3.0
−3.0
V
400 pF
Horizontal CCD Clock − Phase 2
fH2
High
4.0
7.0
7.0
V
400 pF
Reset Clock
fR
Low
−4.0
−3.0
−2.0
V
10 pF
Reset Clock
fR
High
3.5
4.0
5.0
V
10 pF
Description
1. All pins draw less than 10 mA DC current.
2. Capacitance values relative to VSUB.
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KAF−6303
TIMING
Table 10. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Unit
Notes
fH1, fH2 Clock Frequency
fH
−
4
15
MHz
1, 2, 3
fV1, fV2 Clock Frequency
fV
−
25
50
kHz
1, 2, 3
Pixel Period (1 Count)
te
67
250
−
ns
fH1, fH2 Set-up Time
tfHS
0.5
1
−
ms
fV1, fV2 Clock Pulse Width
tfV
10
20
−
ms
2
Reset Clock Pulse Width
tfR
10
20
−
ns
4
tREADOUT
531
1,719
−
ms
5
Integration Time
tINT
−
−
−
Line Time
tLINE
258.2
836
−
Readout Time
6
ms
7
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Cross-over of register clocks should be between 40−60%
of amplitude.
4. fR should be clocked continuously.
5. tREADOUT = (2056 ⋅ tLINE).
6. Integration time (tINT) is user specified. Longer integration times will degrade noise performance.
7. tLINE = (3 ⋅ tfV) + tfHS + 3100 + te.
Frame Timing
tINT
tREADOUT
1 Frame = 2056 Lines
fV1
fV2
Line
1
2
fH1
fH2
Figure 7. Frame Timing
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10
2055
2056
KAF−6303
Line Timing (Each Output)
Line Timing Detail
Pixel Timing Detail
1 Line
tfR
tfV
fR
fV1
tfV
fH1
fV2
te
tfHS
1 Count
te
fH2
fH1
VPIX
fH2
VOUT
3100 Counts
VSAT
VDARK
fR
VODC
VSUB
Line Content
1−10 11−16
VSAT
VDARK
17−3088
3089−3098 3099−3100
VPIX
Photoactive Pixels
VODC
VSUB
Dummy Pixels
Saturated pixel video output signal
Video output signal in no-light situation,
not zero due to JDARK
Pixel video output signal level,
more electrons = more negative*
Video level offset with respect to VSUB
Analog ground
* See Image Acquisition section (Page 3).
Dark Reference Pixels
Figure 8. Timing Diagrams
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11
KAF−6303
STORAGE AND HANDLING
Table 11. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Unit
Notes
Storage Temperature
TST
0
70
°C
1
Operating Temperature
TOP
−60
60
°C
1. Storage toward the maximum temperature will accelerate color filter degradation.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
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12
KAF−6303
MECHANICAL INFORMATION
Completed Assembly
Figure 9. Completed Assembly (1 of 2)
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13
KAF−6303
Figure 10. Completed Assembly (2 of 2)
ON Semiconductor and the
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For additional information, please contact your local
Sales Representative
KAF−6303/D