KAF 0261 D

KAF-0261
512 (H) x 512 (V) Full Frame
CCD Image Sensor
Description
The KAF−0261 Image Sensor is a high performance, charge
coupled device (CCD) designed for a wide range of image sensing
applications.
The sensor incorporates true two−phase CCD technology,
simplifying the support circuits required to drive the sensor as well as
reducing dark current without compromising charge capacity. The
sensor also utilizes a transparent gate electrode to improve sensitivity
compared to the use of a standard front side illuminated polysilicon
electrode.
Selectable on−chip output amplifiers allow operation to be
optimized for different imaging needs: Low Noise (when using the
high−sensitivity output) or Maximum Dynamic Range (when using
the low−sensitivity output).
The low dark current of the KAF−0261 makes this device suitable
for low light imaging applications without sacrificing charge capacity.
www.onsemi.com
Figure 1. KAF−0261 CCD Image Sensor
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Features
Architecture
Full Frame CCD
Number of Active Pixels
512 (H) x 512 (V)
Pixel Size
20 mm (H) x 20 mm (V)
Active Image Size
10.2 mm (H) x 10.2 mm (V)
Chip Size
11.3 mm (H) x 11.6 mm (V)
Optical Fill Factor
100%
Output Sensitivity
High Sensitivity Output
High Dynamic Range Output
10 mV/electron
2.0 mV/electron
Saturation Signal
High Sensitivity Output
High Dynamic Range
200,000 electrons
500,000 electrons
Readout Noise (1 MHz)
22 electrons rms
Dark Current
(25°C, Accumulation Mode)
< 30 pA/cm3
Dark Current Doubling Rate
6°C
Dynamic Range (Sat Sig/Dark Noise)
High Sensitivity Output
83 dB
High Dynamic Range Output Range
87 dB
Quantum Efficiency (450, 550, 650 nm)
35%, 55%, 58%
Maximum Data Rate
High Sensitivity Output
High Dynamic Range Output
5 MHz
2 MHz
Transfer Efficiency
> 0.99997
Package
CERDIP Package
Cover Glass
Clear or AR coated, 2 sides
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 3
• True Two Phase Full Frame Architecture
• Transparent Gate Electrode for High
•
•
•
•
•
Sensitivity
100% Fill Factor
Low Dark Current
User−selectable Outputs Allow either Low
Noise or High Dynamic Range Operation
Single Readout Register
These Devices are Pb−Free and are RoHS
Compliant
Applications
• Scientific Imaging
1
Publication Order Number:
KAF−0261/D
KAF−0261
Table 2. ORDERING INFORMATION
Part Number
Description
Marking Code
KAF−0261−AAA−CD−BA
Monochrome, No Microlens, CERDIP Package (sidebrazed),
Clear Cover Glass with AR coating (both sides), Standard Grade
KAF−0261−AAA
S/N
KAF−0261−AAA−CD−AE
Monochrome, No Microlens, CERDIP Package (sidebrazed),
Clear Cover Glass with AR coating (both sides), Engineering
Sample
KAF−0261−AAA−CP−BA
Monochrome, No Microlens, CERDIP Package (sidebrazed),
Taped Clear Cover Glass, no coatings, Standard Grade
KAF−0261−AAA−CP−AE
Monochrome, No Microlens, CERDIP Package (sidebrazed),
Taped Clear Cover Glass, no coatings, Engineering Sample
KEK−4H0081−KAF−0261−12−5
Evaluation Board (Complete Kit)
N/A
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KAF−0261
DEVICE DESCRIPTION
Architecture
4 Dark Lines
KAF−0261
öV1
öV2
Usable Active Image Area
512(H) x 512(V)
20 mm x 20mm pixels
öH22
Sub
Vdd 2
Vout 2
Vss
Guard
FD 2
4 Dark Lines
öH1
öH2
512 Active Pixels/Line
Vdd 1
Vout 1
öR
Vrd
Vog
öH21
8 Dark
2 Inactive
4 Dark
4 Inactive
FD 1
Figure 2. Block Diagram
technology. The vertical register consists of 20 mm x 20 mm
photocapacitor sensing elements (pixels) that also serves as
the transport mechanism. The pixels are arranged in a
512 (H) x 512 (V) array; an additional 12 columns (4 at the
left and 8 at the right) and 8 rows (4 each at top and bottom)
of non−imaging pixels are added as dark reference. There is
no storage array, so this device must be synchronized with
strobe illumination or shuttered during readout.
Shaded areas represent 4 non−imaging pixels at the
beginning and 8 non−imaging pixels at the end of each line.
There are also 4 non−imaging lines at the top and bottom of
each frame.
The KAF−0261 consists of one vertical (parallel) CCD
shift register, one horizontal (serial) CCD shift register and
a selectable high or low gain output amplifier (See Figure 1).
Both registers incorporate two−phase buried channel CCD
Sub
Vdd2
ö H22
ö H2
FD2
Vout2
Vdd1
FD1
Vlg
Vss
Vout1
öR
ö H1
ö H21
Vrd
Vog
Figure 3. Output Structure
Output Structure
whose potential varies linearly with the quantity of charge
in each packet. The amount of potential change is
determined by the simple expression Vfd = Q/Cfd.
The translation from electrons to voltages is called the
output sensitivity or charge−to−voltage conversion. After
the output has been sensed off−chip, the reset clock (fR)
removes the charge from the floating diffusion via the reset
drain (VRD). This, in turn, returns the floating diffusion
potential to the reference level determined by the reset drain
voltage.
The final gate of the horizontal register is split into two
sections, fH21 and fH22. The split gate structure allows the
user to select either of the two output amplifiers. To use the
high dynamic range single−stage output (Vout1), fH22 is
tied to a negative voltage to block charge transfer, and fH21
is tied to fH2 to transfer charge. To use the high sensitivity
two−stage output (Vout2), fH21 is tied to a negative voltage
and fH22 is tied to fH2. The charge packets are then
dumped onto the appropriate floating diffusion output node
www.onsemi.com
3
KAF−0261
Image Acquisition
Figure 7 illustrates how the integration of charge is
performed with fV1 and fV2 held low. Transfer to the
horizontal CCD begins when fV1 is brought high, causing
charge from the fV1 and fV2 gates to combine under the
fV1 gate. The fV1 and fV2 gates are now reversed in
polarity, causing the charge packets to ‘spill’ forward under
the fV2 gate of the next pixel. The falling edge of fV2 also
transfers the first line of charge into the horizontal CCD. A
second phase transition places the charge packets under the
fV1 electrode of the next pixel. The sequence completes
when fV1 is brought low. Clocking of the vertical register
in this way is known as accumulation mode clocking. Next,
the horizontal CCD reads out the first line of charge using
traditional complementary clocking (using fH1 and fH2
pins) as shown. The falling edge of fH2 forces a charge
packet over the output gate (OG) onto one of the output
nodes (floating diffusion) which is buffered by the output
amplifier. The cycle repeats until all lines are read.
An image is acquired when incident light, in the form of
photons, falls on the array of pixels in the vertical CCD
register and creates electron−hole pairs (or simply electrons)
within the silicon substrate. This charge is collected locally
by the formation of potential wells created at each pixel site
by induced voltages on the vertical register clock lines
(fV1, fV2). These same clock lines are used to implement
the transport mechanism as well. The amount of charge
collected at each pixel is linearly dependent on light level
and exposure time and non−linearly dependent on
wavelength until the potential well capacity is exceeded. At
this point charge will ‘bloom’ into vertically adjacent pixels.
Charge Transport
Integrated charge is transported to the output in a two−step
process. Rows of charge are first shifted line by line into the
horizontal CCD. ‘Lines’ of charge are then shifted to the
output pixel by pixel. The timing diagram illustrated in
www.onsemi.com
4
KAF−0261
DEVICE DESCRIPTION
Pin Description and Device Orientation
24
VLG
VOUT2 2
23
GUARD
VDD1/VDD2 3
22
φV1
VRD 4
21
φV1
φR 5
20
φV2
VSS 6
19
φV2
φH1 7
18
φV2
φH2 8
17
φV2
VOUT1 9
16
φV1
15
φV1
14
SUB
13
SUB
Pixel (1,1)
OG 1
φH21 10
φH22 11
Pixel (512,512)
N/C 12
Figure 4. Pinout Diagram
Table 3. PIN DESCRIPTION
12
N/C
13
VSUB
Substrate
Output Gate
14
VSUB
Substrate
15
fV1
Vertical (Parallel) CCD Clock − Phase 1
16
fV1
Vertical (Parallel) CCD Clock − Phase 1
17
fV2
Vertical (Parallel) CCD Clock − Phase 2
18
fV2
Vertical (Parallel) CCD Clock − Phase 2
19
fV2
Vertical (Parallel) CCD Clock − Phase 2
20
fV2
Vertical (Parallel) CCD Clock − Phase 2
21
fV1
Vertical (Parallel) CCD Clock − Phase 1
22
fV1
Vertical (Parallel) CCD Clock − Phase 1
23
GUARD
24
VLG
Pin
Name
Description
1
OG
2
VOUT2
Video Output from High Sensitivity Two−
Stage
3
VDD1 /
VDD2
Amplifier Supply for VOUT1 and VOUT2
Amplifiers
4
VRD
Reset Drain
5
fR
Reset Clock
6
VSS
Output Amplifier Return
7
fH1
Horizontal (Serial) CCD Clock − Phase 1
8
fH2
Horizontal (Serial) CCD Clock − Phase 2
9
VOUT1
Video Output from High Dynamic Range
Single−Stage Amplifier
10
fH21
Last Horizontal (Serial) CCD Phase −
Split Gate
11
fH22
Last Horizontal (Serial) CCD Phase −
Split Gate
No Connection
Guard Ring
First Stage Load Transistor Gate for
Two−Stage
1. Pins 15, 16, 21, and 22 must be connected together − only one
Phase 1−clock driver is required.
2. Pins 17, 18, 19, and 20 must be connected together − only one
Phase 2−clock driver is required.
www.onsemi.com
5
KAF−0261
IMAGING PERFORMANCE
Typical Operational Conditions
output is assumed and recommended. Many units are
expressed in electrons − to convert to voltage, multiply by
the amplifier sensitivity.
All values apply to nominal operating conditions with the
recommended timing. Correlated doubling sampling of the
Specifications
Table 4. ELECTRO−OPTICAL
Description
Optical Fill Factor
Photoresponse Non−uniformity
Quantum Efficiency
(450, 550, 650 nm)
Symbol
Min
FF
Typ
Max
Units
100
Notes
Verification Plan
Full Array
die10
See QE curve
(Figure 7)
design11
%
PRNU
5
% rms
QE
Table 5. CCD PARAMETERS COMMON TO BOTH OUTPUTS
Description
Sat. Signal − Vccd register
Dark Current
Symbol
Min
Typ
Ne−sat
450
500
Jd
Notes
Verification
Plan
ke−
2
design11
25°C
(mean of all pixels)
die10
30
750
pA/cm2
e−pixel/sec
6.3
7.5
°C
750
e−/pix/sec
DCDR
Dark Signal Non−uniformity
DSNU
Charge Transfer Efficiency
CTE
.99997
PRNL
1
Bs
none
Blooming Suppression
Units
15.3
400
Dark Current Doubling Temp
Photoresponse Non−linearity
5
Max
2
design11
%
4
die10
5
die10
9
Table 6. CCD PARAMETERS SPECIFIC TO HIGH GAIN OUTPUT AMPLIFIER
Description
Output Sensitivity
Symbol
Min
Vout/Ne−
Sat. Signal
Ne−sat
Total Sensor Noise
Typ
Max
10
Units
Notes
Verification Plan
design11
mV/electron
200
240
ke−
1
design11
ne−total
13
20
e−rms
7
design11
Horizontal CCD Frequency
fH
2
5
MHz
6
design11
Dynamic Range
DR
dB
8
design11
180
79
83
Table 7. CCD PARAMETERS SPECIFIC TO LOW GAIN (HIGH DYNAMIC RANGE) OUTPUT AMPLIFIER
Description
Output Sensitivity
Symbol
Min
Vout/Ne−
Typ
Max
Units
Notes
Verification Plan
design11
2
mV/electron
628K
ke−
3
design11
Sat. Signal
Ne−sat
Total Sensor Noise
ne−total
22
30
e−rms
7
die10
Horizontal CCD Frequency
fH
0.5
2
MHz
6
design11
Dynamic Range
DR
dB
8
design11
550K
85
87
1. Point where the output saturates when operated with nominal voltages.
2. Signal level at the onset of blooming in the vertical (parallel) CCD register.
3. Maximum signal level at the output of the high dynamic range output. This signal level will only be achieved when binning pixels containing
large signals.
4. None of 16 sub arrays (128 x 128) exceed the maximum dark current specification.
5. For 2 MHz data rate and T = 30°C to −40°C.
6. Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance.
7. At Tintegration = 0; data rate = 1 MHz; temperature = −30°C.
8. Uses 20LOG (Ne−sat / ne−total) where Ne−sat refers to the appropriate saturation signal.
9. Worst case deviation from straight line fit, between 1% and 90% of Vsat.
10. A parameter that is measured on every sensor during production testing.
11. A parameter that is quantified during the design verification activity.
www.onsemi.com
6
KAF−0261
TYPICAL PERFORMANCE CURVES (QE)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
Wavelength [nm]
Figure 5. Typical Spectral Response
www.onsemi.com
7
900
1000
KAF−0261
DEFECT SPECIFICATIONS
Table 8. MAXIMUM DEFECT COUNTS
Point Defect
Cluster Defect
Column Defect
10
4
0
Column Defect
A grouping of point defects along a single column. (Dark
Column)
A column that contains a pixel whose dark current
exceeds 150,000 electrons/pixel/second at 25°C. (Bright
Column)
A column that does not exhibit the minimum charge
capacity specification. (Low charge capacity)
A column that loses > 500 electrons when the array is
illuminated to a signal level of 2000 electrons/pix. (Trap like
defects)
Dark Defects
A pixel which deviates by more than 20% from
neighboring pixels when illuminated to 70% of saturation
Bright Defect
A pixel whose dark current
electrons/pixel/second at 25°C
exceeds
4500
Cluster Defect
A grouping of not more than 5 adjacent point defects
Neighboring Pixels
The surrounding 128 x 128 pixels of ±64 columns/rows
Defects are separated by no less than 3 pixels in any one
direction.
1,512
512,512
All pixels subject to defect specification
1,1
512,1
Figure 6. Active Pixel Region
www.onsemi.com
8
KAF−0261
OPERATION
Table 9. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Voltage
All Clocks
–16
+16
V
1
Voltage
OG
0
+8
V
2
Voltage
VRD, VSS, VDD, GUARD
0
+20
V
2
Current
Output Bias Current (IDD)
10
mA
10
pF
Capacitance
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Voltage between any two clocks or between any clock and Vsub.
2. Voltage with respect to Vsub.
WARNING: For maximum performance, built−in gate protection has been added only to the OG pin. These devices
require extreme care during handling to prevent electrostatic discharge (ESD) induced damage. Devices are
rated as Class 0 (<250 V per JESD22 Human Body Model test), or Class A (<200 V JESD22 Machine
Model test).
Table 10. DC BIAS OPERATING CONDITIONS
Description
Symbol
Minimum
Nominal
Maximum
Units
Pin Impedance
VSUB
0.0
0.0
0.0
V
Common
Output Amplifier Supply
VDD
15.0
+17.0
17.5
V
5 pF, 2 KW (Note 1)
Output Amplifier Return
VSS
1.4
+2.0
2.1
V
5 pF, 2 KW
Reset Drain
VRD
11.5
+12
12.5
V
5 pF, 1 MW
Output Gate
OG
4.0
4.5
5.0
V
5 pF, 10 MW
Guard Ring
GUARD
9.0
+10.0
15.0
V
350 pF, 10 MW
Load Gate
VLG
VSS − 1.0
VSS
VSS + 1.0
V
Substrate
1. Vdd = 17 volts for applications where the expected output voltage > 2.0 Volts. For applications where the expected useable output voltage
is < 2 Volts Vdd can be reduced to 15 Volts.
AC Operating Conditions
Table 11. CLOCK LEVELS
Description
Symbol
Level
Minimum
Nominal
Maximum
Units
Pin Impedance
Vertical Clock − Phase 1
fV1
Low
−10.2
−10.0
−9.0
V
13 nF, 10 MW
Vertical Clock − Phase 1
fV1
High
0.0
0
2.0
V
Vertical Clock − Phase 2
fV2
Low
−10.2
−10.0
−9.0
V
Vertical Clock − Phase 2
fV2
High
0.0
0
2.0
V
Horizontal Clock − Phase 1
fH1
Low
−2.2
−2.0
−1.8
V
Horizontal Clock − Phase 1
fH1
High
7.8
+8.0
8.2
V
Horizontal Clock − Phase 2
fH2
Low
−2.2
−2.0
−1.8
V
Horizontal Clock − Phase 2
fH2
High
7.8
+8.0
8.2
V
Reset Clock
fR
Low
2.0
3.0
3.5
V
Reset Clock
fR
High
10.0
www.onsemi.com
9
V
16 nF, 10 MW
160 pF, 10 MW
110 pF, 10 MW
10 pF, 10 MW
KAF−0261
Table 12. AMPLIFIER SELECTION
Using the High Gain
Output (Vout2)
Using the High Dynamic
Range Output (Vout1)
Symbol
Level
Min
Nom
Max
Horizontal Clock −
Phase 1
fH21
Low
−4
fH2 low
fH2 low
Horizontal Clock −
Phase 1
fH21
High
−4
fH2 low
fH2 low
Horizontal Clock −
Phase 2
fH22
Low
fH2
−4
fH2 low
fH2 low
V
Horizontal Clock −
Phase 2
fH22
High
fH2
−4
fH2 low
fH2 low
V
Description
Min
Nom
Max
Units
Pin Impedance
fH2
V
10 pF, 10 MW
fH2
V
10 pF, 10 MW
1. When using Vout1 fH21 is clocked identically with fH2 while fH22 is held at a static level. When using Vout2 fH21 and fH22 are exchanged
so that fH22 is identical to fH2 and fH21 is held at a static level. The static level should be the same voltage as fH2 low.
2. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may require adjustments of these
voltages. Pins shown with impedances greater than 1 MW are expected resistances. These pins are only verified to 1 MW.
3. fV1, 2 capacitances are accumulated gate oxide capacitance, and so are an over-estimate of the capacitance.
4. This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult ON Semiconductor in
those situations in which operating conditions meet or exceed minimum or maximum levels.
Timing
Table 13. REQUIREMENTS AND CHARACTERISTICS
Description
Nominal
Maximum
Units
Notes
fH1, fH2 Clock Frequency
fH
5
8
MHz
1, 2, 3
V1, V2 Clock Frequency
fV
100
125
kHz
1, 2, 3
Pixel Period (1 Count)
tpix
125
200
ns
fH1, fH2 Set−up Time
tfHS
500
1000
ns
fV1, fV2 Clock Pulse Width
tfV
4
5
ms
2
tfR
10
20
ns
4
treadout
40
64
ms
5
Reset Clock Pulse Width
Readout Time
Symbol
Integration Time
tint
Line Time
tline
Minimum
6
78
122
ms
7
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Crossover of register clocks should be between 40−60% of
amplitude.
4. fR should be clocked continuously.
5. treadout = (520 * tline)
6. Integration time (tint) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot
noise.
7. tline = (3 * tfV) + tfHS + 530 * tpix + tpix
www.onsemi.com
10
KAF−0261
Normal Readout Timing
Frame Timing
tint
tReadout
1 Frame = 520 Lines
ö
V1
ö
V2
ö
H1
ö
H2
Line
1
2
520
520
Pixel Timing Detail
Line Timing Detail
töR
1 line
töV
V1
öR
töV
öH1
V2
tpix
töHS
1 count
1(tpix)
H1
öH2
Vpix
H2
Vout
530 counts
Vsat
R
Vdark
Vodc
Vsub
V sat
V dark
V pix
V odc
V sub
Line Content
1−4
5−8
9 − 520
Photoactive Pixels
521−528
529−530
Saturated pixel video output signal
Video output signal in no light situation, not zero due to Jdark
Pixel video output signal level, more electrons =more negative*
Video level offset with respect to vsub
Analog Ground
* See Image Aquisition section
Dummy Pixels
Dark Reference Pixels
Figure 7. Timing Diagrams
NOTE: This device is suitable for a wide range of applications requiring a variety of different timing frequencies.
Therefore, only maximum and minimum values are shown above. Consult ON Semiconductor in those
situations, which require special consideration.
www.onsemi.com
11
KAF−0261
STORAGE AND HANDLING
Table 14. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
TST
−100
+80
°C
At Device
Operating Temperature
TOP
−70
+50
°C
At Device
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
www.onsemi.com
12
KAF−0261
MECHANICAL INFORMATION
Completed Assembly
Figure 8. Completed Assembly (1 of 2)
www.onsemi.com
13
KAF−0261
Figure 9. Completed Assembly (2 of 2)
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
14
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
KAF−0261/D