KAI-16000 4872 (H) x 3248 (V) Interline CCD Image Sensor Description The KAI−16000 is an interline transfer CCD offering 16 million pixels at up to 3 frames per second through 2 outputs. This image sensor is organized into an array of 4,872 (H) x 3,248 (V) with 7.4 micron square pixels and full 35 mm optical format. As an interline transfer CCD, the KAI−16000 includes additional features such as progressive scan readout, electronic shutter, low noise, high dynamic range, and blooming suppression. These features make the KAI−16000 the perfect sensor for applications in Industrial, Aerial, Security, and Scientific markets. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Interline CCD; Progressive Scan Total Number of Pixels 4960 (H) x 3324 (V) = 16.6M Number of Effective Pixels 4904 (H) x 3280 (V) = 16.1M Number of Active Pixels 4872 (H) x 3248 (V) = 15.8M Pixel Size 7.4 mm (H) x 7.4 mm (V) Active Image Size 36.1 mm (H) x 24.0 mm (V) 43.3 mm (diagonal), 35 mm Optical Format Aspect Ratio 3:2 Number of Outputs 1 or 2 Saturation Signal 30,000 electrons Output Sensitivity 30 mV/e− Quantum Efficiency KAI−16000−AXA KAI−16000−CXA (RGB) KAI−16000−FXA (RGB) 47% 29%, 38%, 44% 31%, 39%, 45% Read Noise (f = 30 MHz) 16 electrons Dark Current < 0.5 nA/cm2 Applications Dark Current Doubling Temperature 7°C Dynamic Range 65 dB Charge Transfer Efficiency 0.99999 Blooming Suppression > 100 X Smear < −80 dB • • • • Image Lag < 10 electrons Maximum Data Rate 30 MHz per channel Package 40 pin Grid Array Cover Glass AR coated, 2 sides or Clear Glass Figure 1. KAI−16000 CCD Image Sensor Features • • • • • • • 16 Million Pixel Resolution Electronic Shutter 35 mm Optical Format Progressive Scan Readout High Sensitivity Fast Frame Rate > 60 dB Dynamic Range Industrial Aerial Photography Security Scientific ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. NOTE: All parameters are specified at T = 40°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2016 February, 2016 − Rev. 6 1 Publication Order Number: KAI−16000/D KAI−16000 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description KAI−16000−AAA−JR−B1* Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass with AR coating (2 sides), Grade 1 KAI−16000−AAA−JR−B2* Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass with AR coating (2 sides), Grade 2 KAI−16000−AAA−JR−AE* Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass with AR coating (2 sides), Engineering Grade KAI−16000−AAA−JP−B1 Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, Grade 1 KAI−16000−AAA−JP−B2 Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, Grade 2 KAI−16000−AAA−JP−AE Monochrome, No Microlens, PGA Package, Taped Clear Cover Glass, Engineering Grade KAI−16000−AAA−JD−B1 Monochrome, No Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (2 sides), Grade 1 KAI−16000−AAA−JD−B2 Monochrome, No Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (2 sides), Grade 2 KAI−16000−AAA−JD−AE Monochrome, No Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (2 sides), Engineering Grade KAI−16000−AXA−JD−BX Monochrome, Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Special Grade KAI−16000−AXA−JD−B1 Monochrome, Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16000−AXA−JD−B2 Monochrome, Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16000−AXA−JD−AE Monochrome, Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Engineering Grade KAI−16000−AXA−JR−B1* Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass with AR coating (2 sides), Grade 1 KAI−16000−AXA−JR−B2* Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass with AR coating (2 sides), Grade 2 KAI−16000−AXA−JR−AE* Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass with AR coating (2 sides), Engineering Grade KAI−16000−AXA−JP−B1 Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass, Grade 1 KAI−16000−AXA−JP−B2 Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass, Grade 2 KAI−16000−AXA−JP−AE Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass, Engineering Grade KAI−16000−FXA−JD−B1 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16000−FXA−JD−B2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16000−FXA−JD−AE Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Engineering Grade *Not recommended for new designs. www.onsemi.com 2 Marking Code KAI−16000−AAA Serial Number KAI−16000−AXA Serial Number KAI−16000−FXA Serial Number KAI−16000 Table 2. ORDERING INFORMATION Part Number Description KAI−16000−CXA−JD−B1* Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16000−CXA−JD−B2* Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16000−CXA−JD−AE* Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Clear Cover Glass with AR coating (both sides), Engineering Grade Marking Code KAI−16000−CXA Serial Number *Not recommended for new designs. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 3 KAI−16000 DEVICE DESCRIPTION Architecture 4 Gray Rows or Dual Output Pixel 1,1 12 Dummy Pixels 4872 (H) x 3248 (V) Active Pixels 28 Black Columns G R B G B G G R G R 16 Buffer Rows 40 Gray Rows Fast Line Dump Left − 2480 Video L Single B G G R 16 Buffer Columns 16 Buffer Columns 12 Dummy Pixels 28 Black Columns 16 Buffer Rows B G 12 28 16 12 28 16 Fast Line Dump Right − 2480 4872 2436 2436 Video R 16 28 16 28 12 Figure 2. Sensor Architecture clocked out Video L and the right half of the image is clocked out Video R. For the Video L each row consists of 12 empty pixels followed by 28 light shielded pixels followed by 2452 photosensitive pixels. For the Video R each row consists of 12 empty pixels followed by 28 light shielded pixels followed by 2452 photosensitive pixels. When reconstructing the image, data from Video R will have to be reversed in a line buffer and appended to the Video L data. The gray rows are not entirely dark and so should not be used for a dark reference level. Use the dark columns on the left or right side of the image sensor as a dark reference. Of the dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. There are 40 light shielded gray rows followed 3280 photoactive rows and finally 4 more light shielded gray rows. The first 16 and the last 16 photoactive rows are buffer rows giving a total of 3248 lines of image data. In the single output mode all pixels are clocked out of the Video L output in the lower left corner of the sensor. The first 12 empty pixels of each line do not receive charge from the vertical shift register. The next 28 pixels receive charge from the left light shielded edge followed by 4904 photosensitive pixels and finally 28 more light shielded pixels from the right edge of the sensor. The first 16 and last 16 photosensitive pixels are buffer pixels giving a total of 4872 pixels of image data. In the dual output mode the clocking of the right half of the horizontal CCD is reversed. The left half of the image is www.onsemi.com 4 KAI−16000 PHYSICAL DESCRIPTION Pin Description and Device Orientation 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pixel 1,1 1 2 3 4 5 Figure 3. Package Pin Designations − Top View Table 3. PINOUT Pin Name Description Pin Name Description FDGL Fast Line Dump Gate, Left RDL Reset Drain, Left 1 VOUTL Video Output, Left 40 2 VDDL VDD, Left 39 3 GND Ground 38 SUB Substrate GND Ground 4 RESETL Reset Gate, Left 37 5 HLASTL Horizontal Clock, Last Stage, Left 36 V1 VCCD Gate 1, Phase 2 6 H2BL Horizontal Clock, Phase 2, Barrier, Left 35 V5 VCCD Gate 5, Phase 2 V9 VCCD Gate 9, Phase 2 7 H1BL Horizontal Clock, Phase 1, Barrier, Left 34 8 H1SL Horizontal Clock, Phase 1, Storage, Left 33 V3 VCCD Gate 3, Phase 2 V7 VCCD Gate 7, Phase 2 9 H2SL Horizontal Clock, Phase 2, Storage, Left 32 10 ESD ESD Protection Disable 31 V11 VCCD Gate 11, Phase 2 11 GND Ground 30 V2 VCCD Gate 2, Phase 1 V6 VCCD Gate 6, Phase 1 12 H2SR Horizontal Clock, Phase 2, Storage, Right 29 13 H1SR Horizontal Clock, Phase 1, Storage, Right 28 V10 VCCD Gate 10, Phase 1 14 H1BR Horizontal Clock, Phase 1, Barrier, Right 27 V4 VCCD Gate 4, Phase 1 Horizontal Clock, Phase 2, Barrier, Right 26 V8 VCCD Gate 8, Phase 1 15 H2BR 16 HLASTR Horizontal Clock, Last Stage, Right 25 V12 VCCD Gate 12, Phase 1 17 RESETR Reset Gate, Right 24 GND Ground Ground 23 SUB Substrate VDD, Right 22 RDR Reset Drain, Right Video Output, Right 21 FDGR 18 GND 19 VDDR 20 VOUTR www.onsemi.com 5 Fast Line Dump Gate, Right KAI−16000 IMAGING PERFORMANCE Table 4. TYPICAL OPERATION CONDITIONS Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions. Condition Description Notes Frame Time 908 msec 1 Horizontal Clock Frequency 20 MHz Light Source Continuous red, green and blue illumination centered at 450, 530 and 650 nm Operation Nominal operating voltages and timing 2, 3 1. Electronic shutter is not used. Integration time equals frame time. 2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP−8115. 3. For monochrome sensor, only green LED used. Table 5. SPECIFICATIONS Description Symbol Global Non−Uniformity Min. Nom. Max. Units Sample Plan 7 n/a 2.5 5.0 %rms Die Temperature Tested At (5C) Notes 27, 40 1 Maximum Photoresponse Nonlinearity NL n/a 2 % Design 2, 3 Maximum Gain Difference Between Outputs DG n/a 10 % Design 2, 3 Maximum Signal Error due to Nonlinearity Differences DNL n/a 1 % Design 2, 3 Horizontal CCD Charge Capacity HNe 100 ke− Design 50 ke− Die 27, 40 30 ke− Die 27, 40 Vertical CCD Charge Capacity VNe Photodiode Charge Capacity PNe 28 Horizontal CCD Charge Transfer Efficiency HCTE 0.99999 Vertical CCD Charge Transfer Efficiency VCTE 0.99999 Photodiode Dark Current Ipd n/a n/a 40 0.01 350 0.1 e/p/s nA/cm2 Die 40 Vertical CCD Dark Current Ivd n/a n/a 400 0.12 1711 0.5 e/p/s nA/cm2 Die 40 Dark Current Doubling Temperature DT n/a 7 n/a °C Design Image Lag Lag n/a <10 50 e− Design Antiblooming Factor Xab 100 300 n/a Vertical Smear Smr n/a −80 −75 dB Design Read Noise ne−T 16 e−rms Design 5 Dynamic Range DR 65 dB Design 5, 6 Output Amplifier DC Offset Vodc Output Amplifier Bandwidth F−3db Output Amplifier Impedance ROUT Output Amplifier Sensitivity DV/DN 4 n/a Design Design 9.5 14 140 100 4 130 200 30 1. 2. 3. 4. Design V Die MHz Design W Die mV/e− Design 27, 40 27, 40 Per color Value is over the range of 10% to 90% of photodiode saturation. Value is for the sensor operated without binning. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of Vab is set such that the photodiode charge capacity is 30,000 electrons. 5. At 30 MHz 6. Uses 20LOG (PNe/ ne−T) 7. “Die” indicates a parameter that is measured on every sensor during the production testing. “Design” designates a parameter that is quantified during the design verification activity. www.onsemi.com 6 KAI−16000 Table 6. KAI−16000−AAA Description Symbol Peak Quantum Efficiency QEmax Peak Quantum Efficiency Wavelength lQE Min. n/a Nom. Max. Units Sample Plan 1 11 n/a % Design 500 n/a nm Design Temperature Tested At (5C) Notes 1. “Die” indicates a parameter that is measured on every sensor during the production testing. “Design” designates a parameter that is quantified during the design verification activity. Table 7. KAI−16000−AXA Description Symbol Peak Quantum Efficiency QEmax Peak Quantum Efficiency Wavelength lQE Min. n/a Nom. Max. Units Sample Plan 1 45 n/a % Design 500 n/a nm Design Temperature Tested At (5C) Notes 1. “Die” indicates a parameter that is measured on every sensor during the production testing. “Design” designates a parameter that is quantified during the design verification activity. Table 8. KAI−16000−FXA (Gen2) Description Symbol Peak Quantum Efficiency Blue Green Red QEmax Peak Quantum Efficiency Wavelength Blue Green Red lQE Min. n/a n/a n/a Nom. Max. Units Sample Plan 1 45 39 31 n/a n/a n/a % Design 460 525 600 n/a n/a n/a nm Design Temperature Tested At (5C) Notes Temperature Tested At (5C) Notes 1. “Design” designates a parameter that is quantified during the design verification activity. Table 9. KAI−16000−CXA (Gen1) Description Symbol Peak Quantum Efficiency Blue Green Red QEmax Peak Quantum Efficiency Wavelength Blue Green Red lQE Min. n/a n/a n/a Nom. Max. Units Sample Plan 1 44 38 29 n/a n/a n/a % Design 2 470 540 620 n/a n/a n/a nm Design 2 1. “Design” designates a parameter that is quantified during the design verification activity. 2. This color filter set configuration (Gen1) is not recommended for new designs. NOTE: n/a = not applicable www.onsemi.com 7 KAI−16000 TYPICAL PERFORMANCE CURVES Monochrome with Microlens Quantum Efficiency Absolute Quantum Efficiency 0.50 Measured with AR coated cover glass 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 300 400 500 600 700 800 900 1000 1100 Wavelength (nm) Figure 4. Monochrome with Microlens Quantum Efficiency Monochrome without Microlens Quantum Efficiency Absolute Quantum Efficiency 0.14 Measured without AR coated cover glass 0.12 0.10 0.08 0.06 0.04 0.02 0.00 300 400 500 600 700 800 900 Wavelength (nm) Figure 5. Monochrome without Microlens Quantum Efficiency www.onsemi.com 8 1000 1100 KAI−16000 Color with Microlens Quantum Efficiency Figure 6. Color with Microlens Quantum Efficiency www.onsemi.com 9 KAI−16000 Angular Quantum Efficiency For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD. For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens 100 Vertical 90 Relative Quantum Efficiency (%) 80 70 60 50 Horizontal 40 30 20 10 0 −30 −20 −10 0 10 Angle (degress) Figure 7. Monochrome with Microlens Angular Quantum Efficiency www.onsemi.com 10 20 30 KAI−16000 DEFECT DEFINITIONS Operational Conditions All defect tests performed at tint = tframe = 908 msec Table 10. SPECIFICATIONS Description Definition Class X Monochrome with Microlens Only Class 1 Class 2 Monochrome Class 2 Color Notes 150 150 300 300 2 1500 1500 3000 3000 3 Major dark field defective bright pixel Defect ≥ 245 mV Major bright field defective dark pixel Defect ≥ 15% Minor dark field defective bright pixel Defect ≥ 126 mV Cluster defect A group of 2 to “N” contiguous major defective pixels, but no more than “W” adjacent defects horizontally. 0 30 N = 20 W=4 30 N = 20 W=4 30 N = 20 W=4 1, 2 Column defect A group of more than 10 contiguous major defective pixels along a single column 0 0 4 15 1, 2 1. Column and cluster defects are separated by no less than two (2) pixels in any direction (excluding single pixel defects). 2. Tested at 27°C and 40°C. 3. Tested at 40°C. NOTE: Class X sensors are offered strictly “as available”. ON Semiconductor cannot guarantee delivery dates. Please call for availability. Defect Map The defect map supplied with each sensor is based upon testing at an ambient (27°C) temperature. Minor point defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. www.onsemi.com 11 KAI−16000 TEST DEFINITIONS Test Regions of Interest Image Area ROI: Pixel (1, 1) to Pixel (4872, 3248) Only the active pixels are used for performance and defect tests. Overclocking The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 8 for a pictorial representation of the regions. H Horizontal Overclock Pixel 1,1 Vertical Overclock Figure 8. Overclock Regions of Interest www.onsemi.com 12 V KAI−16000 Tests Global Non−Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 630 mV). Prior to this test being performed GlobalNon−Uniformity + 100 the substrate voltage has been set such that the charge capacity of the sensor is 900 mV. Global non−uniformity is defined as ǒActiveAreaStandardDeviation Ǔ ActiveAreaSignal Units: %rms. Active Area Signal = Active Area Average − Dark Column Average Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 630 mV. Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 900 mV. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 384 sub regions of interest, each of which is 203 by 203 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the “Defect Definitions” section. Dark defect threshold = Active Area Signal * threshold Bright defect threshold = Active Area Signal * threshold The sensor is then partitioned into 384 sub regions of interest, each of which is 203 by 203 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: • Average value of all active pixels is found to be • • • • 630 mV Dark defect threshold: 630 mV * 15% = 95 mV Bright defect threshold: 630 mV * 15% = 95 mV Region of interest #1 selected. This region of interest is pixels 1, 1 to pixels 203, 203. ♦ Median of this region of interest is found to be 630 mV. ♦ Any pixel in this region of interest that is ≥ (630 + 95 mV) 725 mV in intensity will be marked defective. ♦ Any pixel in this region of interest that is ≤ (630 − 95 mV) 535 mV in intensity will be marked defective. All remaining 384 sub regions of interest are analyzed for defective pixels in the same manner. www.onsemi.com 13 KAI−16000 OPERATION Table 11. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Operating Temperature TOP −50 70 °C 1 Humidity RH 5 90 % 2 Output Bias Current Iout 0.0 −40 mA 3 Off−chip Load CL 10 pF Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25°C. Excessive humidity will degrade MTTF. 3. Total for all outputs. Maximum current is −20 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Operation at these values will reduce MTTF. Table 12. MAXIMUM VOLTAGE RATINGS BETWEEN PINS Description Minimum Maximum Units RL, RR, H1SL, H1BL, H2SL, H2BL, H1SR, H1BR, H2SR, H2BR, HLASTL, HLASTR to ESD 0 17 V −17 17 V 0 25 V Pin to Pin with ESD Protection VDDL, VDDR to GND Notes 1 1. Pins with ESD protection are: RL, RR, H1SL, H1BL, H2SL, H2BL, H1SR, H1BR, H2SR, H2SR, HLASTL, and HLASTR Power−Up Sequence 1. Substrate 2. ESD Protection Disable 3. All other clocks and biaeses Table 13. DC BIAS OPERATING CONDITIONS Description Maximum DC Current (mA) Symbol Pins Minimum Nominal Maximum Units RD RDL, RDR +11.5 +12.0 +12.0 V Output Amplifier Supply VDD VDDL, VDDR +14.5 +15.0 +15.5 V Ground GND GND 0.0 0.0 0.0 V Substrate SUB SUB +8.0 VAB +16.0 V 1, 5 ESD Protection Disable ESD ESD −9.25 −9.0 −8.75 V 2 Output Bias Current Iout VOUTL, VOUTR −5.0 −10.0 mA 3 Reset Drain Notes 4 1. The operating of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of Vab is set such that the photodiode charge capacity is 30,000 electrons. 2. VESD must be at least 1 V more negative than H1_lo and H2_lo during sensor operation AND during camera power turn on. 3. An output load sink must be applied to Vout to activate output amplifier. 4. The maximum DC current is for one output unloaded. This is the maximum current that the first two stages of one output amplifier will draw. This value is with Vout disconnected. 5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions www.onsemi.com 14 KAI−16000 AC Operating Conditions Table 14. CLOCK LEVELS Description Pins Symbol Minimum Nominal Maximum Units Vertical CCD Clock High V1, V3, V5, V7, V9, V11 V_2hi +8.5 +9.0 +9.5 V Vertical CCD Clocks Midlevel V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12 V_1mid, V_2mid −0.2 0.0 +0.2 V Vertical CCD Clocks Low V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12 V_1lo, V_2lo −9.5 −9.0 −8.5 V Horizontal CCD Clocks Amplitude, Phase 1 Storage H1SaH1SL, H1BL, H2SL, H2BL, H1SR, H1BR, H2SR, H2BRK H_amp +4.5 +5.0 +5.5 V Horizontal CCD Clocks Low H1SL, H1BL, H2SL, H2BL, H1SR, H1BR, H2SR, H2BR H_lo −5.0 −4.5 −4.0 V Horizontal Last CCD Amplitude HLASTL, HLASTR HLAST_amp +4.5 +5.0 +5.5 V Horizontal Last CCD Low HLASTL, HLASTR HLAST_lo −5.0 −4.5 −4.0 V Reset Clock Amplitude RESETL, RESETR R_amp +4.5 +5.0 +5.5 V Reset Clock Low RESETL, RESETR R_lo −3.5 −3.0 −2.5 V SUB Vshutter +44 +48 +52 V Fast Dump High FDL, FDR FD_hi +4.5 +5.0 +5.5 V Fast Dump Low FDL, FDR FD_lo −9.5 −9.0 −8.5 V Electronic Shutter Voltage 1. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions The figure below shows the DC bias (SUB) and AC clock (Vshutter) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. Vshutter SUB GND GND Figure 9. www.onsemi.com 15 Notes 1 KAI−16000 Table 15. CLOCK LINE CAPACITANCES Capacitance Units Notes Vertical CCD Phase 1 to GND Clocks 108 nF 1, 3 Vertical CCD Phase 2 to GND 118 nF 1, 4 Vertical CCD Phase 1 to Vertical CCD Phase 2 56 nF 3, 4 H1S to GND 27 pF 2 H2S to GND 27 pF 2 H1B to GND 13 pF 2 H2B to GND 4 pF 2 H1S to H2B and H2S 13 pF 2 H1B to H2B and H2S 13 pF 2 H2S to H1B and H1S 13 pF 2 H2B to H1B and H1S 13 pF 2 HLAST to GND 20 pF 2 RESET to GND 10 pF FD to GND 20 pF 1. Gate capacitance to GND is voltage dependent. Value is for nominal VCCD clock voltages. 2. For nominal HCCD clock voltages, these values are for half of the imager (H1SL, H1BL, H2SL, H2BL and H1BINL or H1SR, H1BR, H2SR, H2BR and H1BINR). 3. Vertical CCD Phase 1: V2, V4, V6, V8, V10, V12 4. Vertical CCD Phase 2: V1, V3, V5, V7, V9, V11 www.onsemi.com 16 KAI−16000 TIMING Table 16. REQUIREMENTS AND CHARACTERISTICS Description VCCD to HCCD Delay VCCD Transfer Time HCCD to VCCD Delay Symbol Minimum Nominal THD 4 6 ms TVCCD 4 6 ms THL Maximum Units 50 ns TV3rd 10 12 ms VCCD Pedestal Time T3P 200 600 ms VCCD Delay T3D 12 20 ms 50 ns 60 ms Photodiode Transfer Time VCCD Delay Before Pedestal VCCD Delay Before 1st Line Reset Pulse Time TDEL TD1L 10 TR 3.25 ms THDS 6 ms Shutter Pulse TIme TS 4 ms Shutter Pulse Delay TSD 1.5 ms HCCD Clock Period TH 33.3 ns VCCD Rise/Fall Time TVR 0.2 ms Fast Dump Gate Leading Delay TFDL 0.5 ms Fast Dump Gate Trailing Delay TFDT 0.5 ms VCCD Line Clock Leading Edge Delay TVL 0.2 0.3 0.4 ms VCCD Line Clock Trailing Edge Delay TVT 0.0 0.2 0.4 ms VCCD to HCCD Delay − Shutter Main Timing − Continuous Mode Vertical Frame Timing Line Timing Repeat for 3324 Lines Figure 10. Main Timing − Continuous Mode www.onsemi.com 17 Notes KAI−16000 Frame Timing − Continuous Mode V2, V4, V6, V8, V10, V12 V_1mid V_1lo T3P T3D V_2hi V1, V3, V5, V7, V9, V11 V_2mid TD1L TV3rd V_2lo TDEL H_amp H1SL, H1BL, H1SR, H2BR H_lo H_amp H2SL, H2BL, H2SR, H1BR H_lo HLAST_amp HLASTL, HLASTR HLAST_lo Figure 11. Framing Timing www.onsemi.com 18 KAI−16000 Line Timing Continuous Mode Line Timing Single Output TL V2, V4, V6, V8, V10, V12 TVCCD V1, V3, V5, V7, V9, V11 THD H1SL, H1BL, H1SR, H2BR H2SL, H2BL, H2SR, H1BR HLASTL, HLASTR 4970 4971 4972 4941 4942 4943 4944 4945 4946 39 40 41 42 43 44 11 12 13 14 pixel count 1 2 R Figure 12. Line Timing Single Output Line Timing Double Output TL V2, V4, V6, V8, V10, V12 TVCCD V1, V3, V5, V7, V9, V11 THD H1SL, H1BL, H1SR, H1BR H2SL, H2BL, H2SR, H2BR HLASTL, HLASTR 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 39 40 41 42 43 44 11 12 13 14 pixel count 1 2 R Figure 13. Line Timing Dual Output www.onsemi.com 19 KAI−16000 Line Timing Detail Single Output V_1mid V2, V4, V6, V8, V10, V12 V_1lo V_2mid V1, V3, V5, V7, V9, V11 TVCCD V_2lo THL THD H_amp H1SL, H1BL, H1SR, H2BR H_lo H_amp H2SL, H2BL, H2SR, H1BR H_lo HLAST_amp HLASTL, HLASTR HLAST_lo Figure 14. Line Timing Detail Single Output Line Timing Detail Edge Alignment V2, V4, V6, V8, V10, V12 TVL TVT High 100% 90% 50% 10% V1, V3, V5, V7, V9, V11 Low 0% Figure 15. Line Timing Detail Edge Alignment www.onsemi.com 20 KAI−16000 Pixel Timing H_amp H1SL, H1BL, H1SR, H2BR H_lo H_amp H2SL, H2BL, H2SR, H1BR H_lo HLAST_amp HLASTL, HLASTR HLAST_lo TR R_amp RR, RL R_lo Figure 16. Pixel Timing www.onsemi.com 21 KAI−16000 Fast Line Dump Timing FD_hi FDR, FDL FD_lo TFDL V1, V3, V5, V7, V9, V11 TFDT TVCCD TVCCD TVCCD V2, V4, V6, V8, V10, V12 THD H1SL, H1BL, H1SR, H2BR Figure 17. Fast Line Dump Timing www.onsemi.com 22 KAI−16000 Electronic Shutter Timing VES TS SUB VSUB GND TSD THDS V2, V4, V6, V8, V10, V12 V1, V3, V5, V7, V9, V11 H1SL, H1BL, H1SR, H2BR H2SL, H2BL, H2SR, H1BR HLASTL, HLASTR Figure 18. Electronic Shutter Timing Electronic Shutter Integration Time Definition V1, V3, V5, V7, V9, V11 Integration Time VShutter VSUB Figure 19. Integration Time Definition www.onsemi.com 23 KAI−16000 STORAGE AND HANDLING Table 17. STORAGE CONDITIONS Description Temperature Humidity Symbol Minimum Maximum Units Notes T −55 80 °C 1 RH 5 90 % 2 1. Long−term exposure toward the maximum temperature will accelerate color filter degradation. 2. T = 25°C. Excessive humidity will degrade MTTF. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. www.onsemi.com 24 KAI−16000 MECHANICAL DRAWINGS Completed Assembly Figure 20. Completed Assembly (1 of 2) www.onsemi.com 25 KAI−16000 Figure 21. Completed Assembly (2 of 2) www.onsemi.com 26 KAI−16000 Cover Glass Coat Both Sides 0.020R [0.50] (Typ. 8 plcs.) Chamfer 0.020" [0.50] Ref. AR coat area (Typ. 4 plcs.) Epoxy: NC0-150 HB Thk. 0.002" - 0.005" Chamfer 0.008" [0.20] 8 plcs.) Notes: Double Sided AR Coated Glass 1. Multi−Layer Anti−Reflective Coating on 2 sides: Double Sided Reflectance: Range (nm) 420 − 450 nm < 2% 450 − 630 nm < 1% 630 − 680 nm < 2% 2. Dust, Scratch Specification − 20 microns max. 3. Substrate − Schott D263T eco or equivalent 4. Epoxy: NCO−150HB Thickness: 0.002” − 0.005” Clear Glass 1. Materials: Substrate − Schott D263T eco or equivalent 2. No epoxy 3. Dust, Scratch Count − 20 microns max. 4. Reflectance: 420 − 435 nm < 10% 435 − 630 nm < 10% 630 − 680 nm < 10% Figure 22. Glass Drawing www.onsemi.com 27 (Typ. KAI−16000 Glass Transmission Figure 23. MAR and Clear Glass Transmission ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 28 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAI−16000/D