KAI-16050 4896 (H) x 3264 (V) Interline CCD Image Sensor Description The KAI−16050 Image Sensor is a 16−megapixel CCD in an APS−H optical format. Based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, the sensor features broad dynamic range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs for full resolution readout up to 8 frames per second. A vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. The sensor is available with the TRUESENSE Sparse Color Filter Pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The sensor shares common PGA pin−out and electrical configurations with other devices based on the TRUESENSE 5.5 micron Interline Transfer CCD Platform, allowing a single camera design to be leveraged to support multiple members of this sensor family. Figure 1. KAI−16050 CCD Image Sensor Table 1. GENERAL SPECIFICATIONS Parameter Architecture Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Active Image Size Typical Value Interline CCD; Progressive Scan 4964 (H) x 3332 (V) 4920 (H) x 3288 (V) 4896 (H) x 3264 (V) 5.5 mm (H) x 5.5 mm (V) 26.93 mm (H) x 17.95 mm (V) 32.36 mm (diag.) APS−H Format Aspect Ratio Number of Outputs Charge Capacity Output Sensitivity Quantum Efficiency Pan (−AXA, −QXA, −PXA) R, G, B (−FXA, −QXA) R, G, B (−CXA, −PXA) Read Noise (f = 40 MHz) Dark Current Photodiode VCCD Dark Current Doubling Temp. Photodiode VCCD Dynamic Range Charge Transfer Efficiency Blooming Suppression Smear Image Lag Maximum Pixel Clock Speed Maximum Frame Rates Quad Output Dual Output Single Output Package Cover Glass 3:2 1, 2, or 4 20,000 electrons 34 mV/e− www.onsemi.com Features • Bayer Color Pattern, TRUESENSE Sparse • • • • • • • 43% 28%, 35%, 38% 29%, 35%, 37% 12 electrons rms 2 electrons/s 140 electrons/s Color Filter Pattern, and Monochrome Configurations Progressive Scan Readout Flexible Readout Architecture High Frame Rate High Sensitivity Low Noise Architecture Excellent Smear Performance Package Pin Reserved for Device Identification Applications • Industrial Imaging and Inspection • Traffic • Security 7°C 9°C 64 dB 0.999999 > 300 X Estimated −100 dB < 10 electrons 40 MHz ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. 8 fps 4 fps 2 fps 72 pin PGA AR coated, 2 Sides NOTE: All parameters are specified at T = 40°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2015 August, 2015 − Rev. 7 1 Publication Order Number: KAI−16050/D KAI−16050 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description Marking Code KAI−16050−AXA−JD−B1 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16050−AXA Serial Number KAI−16050−AXA−JD−B2 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16050−AXA−JD−AE Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI−16050−FXA−JD−B1 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16050−FXA−JD−B2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16050−FXA−JD−AE Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI−16050−QXA−JD−B1 Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16050−QXA−JD−B2 Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16050−QXA−JD−AE Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI−16050−FXA Serial Number KAI−16050−QXA Serial Number Table 3. EVALUATION SUPPORT Catalog Number Product Name Description 4H2207 G2−FPGA−BD−14−40−A−GEVK FPGA Board for IT−CCD Evaluation Hardware 4H2209 KAI−72PIN−HEAD−BD−A−GEVB 72 Pin Imager Board for IT−CCD Evaluation Hardware 4H2211 LENS−MOUNT−KIT−B−GEVK Lens Mount Kit for IT−CCD Evaluation Hardware See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAI−16050 Table 4. NOT RECOMMENDED FOR NEW DESIGNS Description Marking Code KAI−16050−CXA−JD−B1 Part Number Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16050−CXA Serial Number KAI−16050−CXA−JD−B2 Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16050−CXA−JD−AE Gen1 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI−16050−PXA−JD−B1 Gen1 Color (TRUESENSE Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−16050−PXA−JD−B2 Gen1 Color (TRUESENSE Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 KAI−16050−PXA−JD−AE Gen1 Color (TRUESENSE Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade www.onsemi.com 3 KAI−16050−PXA Serial Number KAI−16050 DEVICE DESCRIPTION Architecture H2Bd H2Sd H1Bd H1Sd FDGcd 1 10 22 12 8 SUB FDGcd H2Bc H2Sc H1Bc H1Sc RDc Rc VDDc VOUTc 2448 2448 RDd Rd VDDd VOUTd 12 8 22 10 1 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ FLD 22 GND OGc H2SLc GND OGd H2SLd 12 V1T V2T V3T V4T V1T V2T V3T V4T DevID ESD 22 4896H x 3264V 5.5 mm x 5.5 mm Pixels 12 12 22 V1B V2B V3B V4B RDa Ra VDDa VOUTa ESD V1B V2B V3B V4B 12 Buffer ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 22 Dark FLD 1 10 22 12 8 2448 2448 H2Bb H2Sb H1Bb H1Sb FDGab SUB FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa (Last VCCD Phase = V1 → H1S) 12 8 22 10 1 RDb Rb VDDb VOUTb GND OGb H2SLb Figure 2. Block Diagram Dark Reference Pixels Active Buffer Pixels There are 22 dark reference rows at the top and 22 dark rows at the bottom of the image sensor. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the 22 dark columns on the left or right side of the image sensor as a dark reference. Under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non−uniformities. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron−hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non−linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Dummy Pixels Within each horizontal shift register there are 11 leading additional shift phases. These pixels are designated as dummy pixels and should not be used to determine a dark reference level. In addition, there is one dummy row of pixels at the top and bottom of the image. www.onsemi.com 4 KAI−16050 ESD Protection power−down sequences may cause damage to the sensor. See Power−Up and Power−Down Sequence section. Adherence to the power−up and power−down sequence is critical. Failure to follow the proper power−up and Bayer Color Filter Pattern SUB 1 10 22 12 8 H2Bd H2Sd H1Bd H1Sd FDGcd FDGcd H2Bc H2Sc H1Bc H1Sc RDc Rc VDDc VOUTc 2448 2448 RDd Rd VDDd VOUTd 12 8 22 10 1 FLD 22 GND OGc H2SLc GND OGd H2SLd 12 BG G R V1T V2T V3T V4T BG G R V1T V2T V3T V4T DevID ESD 22 4896H x 3264V 5.5 mm x 5.5 mm Pixels 12 V1B V2B V3B V4B 12 BG G R 22 ESD V1B V2B V3B V4B BG G R 12 Buffer RDa Ra VDDa VOUTa RDb Rb VDDb VOUTb 22 Dark FLD (Last VCCD Phase = V1 → H1S) 1 10 22 12 8 2448 12 8 22 10 1 SUB GND OGb H2SLb H2Bb H2Sb H1Bb H1Sb FDGab FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 2448 Figure 3. Bayer Color Filter Pattern TRUESENSE Sparse Color Filter Pattern SUB 1 10 22 12 8 H2Bd H2Sd H1Bd H1Sd FDGcd FDGcd H2Bc H2Sc H1Bc H1Sc RDc Rc VDDc VOUTc 2448 2448 RDd Rd VDDd VOUTd 12 8 22 10 1 FLD 22 GND OGc H2SLc GND OGd H2SLd 12 G P B P V1T V2T V3T V4T P G P B R P G P P R P G G P B P P G P B R P G P P R P G V1T V2T V3T V4T DevID ESD 22 12 V1B V2B V3B V4B RDa Ra VDDa VOUTa 12 5.5 mm x 5.5 mm Pixels G P B P P G P B R P G P P R P G G P B P P G P B R P G P 22 22 Dark FLD (Last VCCD Phase = V1 → H1S) 1 10 22 12 8 2448 2448 12 8 22 10 1 SUB H2Bb H2Sb H1Bb H1Sb FDGab Figure 4. TRUESENSE Sparse Color Filter Pattern www.onsemi.com 5 ESD V1B V2B V3B V4B P R P G 12 Buffer FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 4896H x 3264V RDb Rb VDDb VOUTb GND OGb H2SLb KAI−16050 PHYSICAL DESCRIPTION Pin Description and Device Orientation V3T V1T VDDd GND Rd H1Bd H2SLd H2Sd SUB N/C H2Sc H1Bc H2SLc Rc GND VDDc V1T V3T 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 DevID ESD RDb V4B OGb V2B RDd H2Bb V4T OGd V2T H2Bd H1Sb VOUTd H1Sd H1Sa FDGab FDGab FDGcd FDGcd H1Sc H2Bc OGc RDc VOUTc V2T V4T ESD Pixel (1,1) Figure 5. Package Pin Designations − Top View www.onsemi.com 6 V3B V1B VDDb GND H2SLa H1Ba Rb Ra VOUTb GND H2SLb VDDa H1Bb V1B H2Sb 9 11 13 15 17 19 21 23 25 27 29 31 33 35 N/C 7 SUB 5 H2Sa 3 H2Ba 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 OGa VOUTa 6 RDa V2B V3B V4B 1 4 KAI−16050 Table 5. PIN DESCRIPTION Pin Name 1 V3B Description Vertical CCD Clock, Phase 3, Bottom Pin Name Description 72 ESD ESD Protection Disable 71 V3T Vertical CCD Clock, Phase 3, Top 70 V4T Vertical CCD Clock, Phase 4, Top V1T Vertical CCD Clock, Phase 1, Top Vertical CCD Clock, Phase 2, Top 3 V1B Vertical CCD Clock, Phase 1, Bottom 69 4 V4B Vertical CCD Clock, Phase 4, Bottom 68 V2T VDDc Output Amplifier Supply, Quadrant c Video Output, Quadrant c 5 VDDa Output Amplifier Supply, Quadrant a 67 6 V2B Vertical CCD Clock, Phase 2, Bottom 66 VOUTc 7 GND Ground 65 GND Ground Video Output, Quadrant a 64 RDc Reset Drain, Quadrant c Rc Reset Gate, Quadrant c Output Gate, Quadrant c 8 VOUTa 9 Ra Reset Gate, Quadrant a 63 10 RDa Reset Drain, Quadrant a 62 OGc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a 61 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c 11 H2SLa 12 OGa Output Gate, Quadrant a 60 H2Bc 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a Horizontal CCD Clock, Phase 2, Barrier, Quadrant c 59 H1Bc 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a Horizontal CCD Clock, Phase 1, Barrier, Quadrant c 58 H1Sc 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a Horizontal CCD Clock, Phase 1, Storage, Quadrant c 57 H2Sc 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a Horizontal CCD Clock, Phase 2, Storage, Quadrant c 56 FDGcd Substrate 55 N/C Fast Line Dump Gate, Bottom 54 FDGcd No Connect 53 SUB Substrate Fast Line Dump Gate, Bottom 52 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d 17 SUB 18 FDGab Fast Line Dump Gate, Top No Connect Fast Line Dump Gate, Top 19 N/C 20 FDGab 21 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 51 H2Sd 22 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b Horizontal CCD Clock, Phase 2, Storage, Quadrant d 50 H2Bd 23 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b Horizontal CCD Clock, Phase 2, Barrier, Quadrant d 49 H1Bd 24 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b Horizontal CCD Clock, Phase 1, Barrier, Quadrant d 48 OGd Output Gate, Quadrant d 25 H2SLb Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b 47 H2SLd 26 OGb Output Gate, Quadrant b 46 RDd Reset Drain, Quadrant d 27 Rb Reset Gate, Quadrant b 45 Rd Reset Gate, Quadrant d VOUTd GND Ground Vertical CCD Clock, Phase 2, Top Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d 28 RDb Reset Drain, Quadrant b 44 29 GND Ground 43 30 VOUTb Video Output, Quadrant b 42 V2T VDDd V4T Vertical CCD Clock, Phase 4, Top Vertical CCD Clock, Phase 1, Top 31 VDDb Output Amplifier Supply, Quadrant b 41 32 V2B Vertical CCD Clock, Phase 2, Bottom 40 33 V1B Vertical CCD Clock, Phase 1, Bottom 39 V1T 38 DevID 37 V3T 34 V4B Vertical CCD Clock, Phase 4, Bottom 35 V3B Vertical CCD Clock, Phase 3, Bottom 36 ESD Video Output, Quadrant d Output Amplifier Supply, Quadrant d Device Identification Vertical CCD Clock, Phase 3, Top 1. Liked named pins are internally connected and should have a common drive signal. 2. N/C pins (19, 55) should be left floating. ESD Protection Disable www.onsemi.com 7 KAI−16050 IMAGING PERFORMANCE Table 6. TYPICAL OPERATION CONDITIONS Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions. Condition Description Notes Light Source Continuous red, green and blue LED illumination Operation Nominal operating voltages and timing For monochrome sensor, only green LED used. Table 7. SPECIFICATIONS All Configurations Description Dark Field Global Non−Uniformity Symbol Min. Nom. Max. Units DSNU − − 5 mVpp Die 27, 40 − 2 5 %rms Die 27, 40 1 − 10 30 %pp Die 27, 40 1 − 1 2 %rms Die 27, 40 1 Bright Field Global Non−Uniformity Bright Field Global Peak to Peak Non−Uniformity Temperature Tested At (5C) Sampling Plan PRNU Bright Field Center Non−Uniformity Notes Maximum Photoresponse Nonlinearity NL − 2 − % Design 2 Maximum Gain Difference Between Outputs DG − 10 − % Design 2 Maximum Signal Error due to Nonlinearity Differences DNL − 1 − % Design 2 Horizontal CCD Charge Capacity HNe − 50 − ke− Design Vertical CCD Charge Capacity VNe − 45 − ke− Design ke− Die Photodiode Charge Capacity PNe − 20 − 27, 40 Horizontal CCD Charge Transfer Efficiency HCTE 0.999995 0.999999 − Die Vertical CCD Charge Transfer Efficiency VCTE 0.999995 0.999999 − Die Photodiode Dark Current Ipd − 7 70 e/p/s Die 40 Vertical CCD Dark Current Ivd − 140 400 e/p/s Die 40 e− Design 3 Image Lag Lag − − 10 Antiblooming Factor Xab 300 − − Vertical Smear Smr − −100 − dB Design Read Noise ne−T − 12 − e−rms Design 4 Dynamic Range DR − 64 − dB Design 4, 5 Output Amplifier DC Offset Vodc − 9.4 − V Die Output Amplifier Bandwidth f−3db − 250 − MHz Die Output Amplifier Impedance ROUT − 127 − W Die − mV/e− Design Output Amplifier Sensitivity DV/DN − 34 Design 27, 40 6 27, 40 1. Per color 2. Value is over the range of 10% to 90% of photodiode saturation. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is 680 mV. 4. At 40 MHz 5. Uses 20LOG (PNe/ ne−T) 6. Assumes 5 pF load. www.onsemi.com 8 KAI−16050 Table 8. KAI−16050−AXA, KAI−16050−QXA, AND KAI−16050−PXA1 CONFIGURATIONS Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency QEmax − 43 − % Design Peak Quantum Efficiency Wavelength lQE − 470 − nm Design Description Temperature Tested At (5C) Notes 1. This color filter set configuration (Gen1) is not recommended for new designs. Table 9. KAI−16050−FBA AND KAI−16050−QBA GEN2 COLOR CONFIGURATIONS WITH MAR GLASS Description Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency Blue Green Red QEmax − 37 35 29 − % Design Peak Quantum Efficiency Wavelength Blue Green Red lQE − 460 530 605 − nm Design Temperature Tested At (5C) Notes Table 10. KAI−16050−CBA AND KAI−16050−PBA GEN1 COLOR CONFIGURATIONS WITH MAR GLASS Description Symbol Min. Nom. Max. Units Sampling Plan Temperature Tested At (5C) Notes Peak Quantum Efficiency Blue Green Red QEmax − 38 35 28 − % Design 1 Peak Quantum Efficiency Wavelength Blue Green Red lQE − 470 540 620 − nm Design 1 1. This color filter set configuration (Gen1) is not recommended for new designs. www.onsemi.com 9 KAI−16050 TYPICAL PERFORMANCE CURVES Quantum Efficiency Monochrome with Microlens Figure 6. Monochrome with Microlens Quantum Efficiency www.onsemi.com 10 KAI−16050 Color (Bayer RGB) with Microlens and MAR Cover Glass (Gen2 and Gen1 CFA) Figure 7. Color (Bayer) with Microlens Quantum Efficiency Color (TRUESENSE Sparse CFA) with Microlens (Gen2 and Gen1 CFA) Figure 8. Color (TRUESENSE Sparse CFA) with Microlens Quantum Efficiency www.onsemi.com 11 KAI−16050 Angular Quantum Efficiency For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD. For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens 100 Relative Quantum Efficiency (%) 90 Vertical 80 70 60 50 Horizontal 40 30 20 10 0 −40 −30 −20 −10 0 10 20 30 40 Angle (degrees) Figure 9. Monochrome with Microlens Angular Quantum Efficiency Dark Current versus Temperature 10000 Dark Current (e/s) 1000 VCCD 100 10 Photodiode 1 0.1 1000/T (K) 2.9 T (C) 72 3.0 3.1 3.2 3.3 3.4 60 50 40 30 21 Figure 10. Dark Current versus Temperature www.onsemi.com 12 KAI−16050 Power − Estimated 2.5 Power (W) 2.0 1.5 1.0 0.5 0.0 10 15 20 25 30 35 40 HCCD Frequency (MHz) Single Dual Quad Figure 11. Power Frame Rate (fps) Frame Rates 10.0 10.0 9.0 9.0 8.0 8.0 7.0 7.0 6.0 6.0 5.0 5.0 4.0 4.0 3.0 3.0 2.0 2.0 1.0 1.0 0.0 10 15 20 25 30 35 HCCD Frequency (MHz) Single Dual (Left/Right) Figure 12. Frame Rates www.onsemi.com 13 Quad 40 0.0 KAI−16050 DEFECT DEFINITIONS Table 11. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C Description 1. 2. 3. 4. Condition Notes Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout HCCD Clock Frequency 10 MHz Pixels Per Line 5120 1 Lines Per Frame 1760 2 Line Time 547.7 msec Frame Time 964.0 msec Photodiode Integration Time (PD_Tint) Mode A: PD_Tint = Frame Time = 964.0 msec, no electronic shutter used VCCD Integration Time 912.5 msec Temperature 40°C Light Source Continuous red, green and blue LED illumination Operation Nominal operating voltages and timing 3 4 Horizontal overclocking used. Vertical overclocking used. VCCD Integration Time = 1666 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 12. DEFECT DEFINITIONS FOR TESTING AT 405C Description Definition Grade 1 Grade 2 Mono Grade 2 Color Notes 150 300 300 1 1500 3000 3000 Major dark field defective bright pixel PD_Tint = Mode A → Defect ≥ 328 mV Major bright field defective dark pixel Defect ≥ 12% Minor dark field defective bright pixel PD_Tint = Mode A → Defect ≥ 164 mV Cluster defect A group of 2 to 19 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. 20 n/a n/a Cluster defect A group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally. n/a 30 30 Column defect A group of more than 10 contiguous major defective pixels along a single column 0 4 15 2 2 1. For the color devices (KAI−16050−CXA and KAI−16050−PXA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). www.onsemi.com 14 KAI−16050 Table 13. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C Description 1. 2. 3. 4. Condition Notes Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout HCCD Clock Frequency 10 MHz Pixels Per Line 5120 1 Lines Per Frame 3424 2 Line Time 547.7 msec Frame Time 1875.4 msec Photodiode Integration Time (PD_Tint) Mode A: PD_Tint = Frame Time = 1875.4 msec, no electronic shutter used VCCD Integration Time 912.5 msec Temperature 27°C Light Source Continuous red, green and blue LED illumination Operation Nominal operating voltages and timing 3 4 Horizontal overclocking used. Vertical overclocking used. VCCD Integration Time = 1666 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 14. DEFECT DEFINITIONS FOR TESTING AT 275C Description Definition Grade 1 Grade 2 Mono Grade 2 Color Notes 150 300 300 1 2 Major dark field defective bright pixel PD_Tint = Mode A → Defect ≥ 200 mV Major bright field defective dark pixel Defect ≥ 12% Cluster defect A group of 2 to 19 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. 20 n/a n/a Cluster defect A group of 2 to 38 contiguous major defective pixels, but no more than 5 adjacent defects horizontally. n/a 30 30 Column defect A group of more than 10 contiguous major defective pixels along a single column 0 4 15 2 1. For the color devices (KAI−16050−CXA and KAI−16050−PXA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). Defect Map defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. See Figure 13: Regions of interest for the location of pixel 1,1. The defect map supplied with each sensor is based upon testing at an ambient (27°C) temperature. Minor point www.onsemi.com 15 KAI−16050 TEST DEFINITIONS Test Regions of Interest Image Area ROI: Pixel (1, 1) to Pixel (4920, 3288) Active Area ROI: Pixel (13, 13) to Pixel (4908, 3276) Center ROI: Pixel (2411, 1595) to Pixel (2510, 1694) Only the Active Area ROI pixels are used for performance and defect tests. Overclocking The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 13 for a pictorial representation of the regions of interest. VOUTc 12 dark rows 12 buffer rows 12 buffer rows 12 dark rows VOUTa Figure 13. Regions of Interest www.onsemi.com 16 Horizontal Overclock 1, 1 22 dark columns Pixel 12 buffer columns 12 buffer columns 22 dark columns Pixel 13, 13 4896 x 3264 Active Pixels KAI−16050 Tests are found. The dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. Units: mVpp (millivolts peak to peak) Dark Field Global Non−Uniformity This test is performed under dark field conditions. The sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. The average signal level of each of the 864 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Global Non−Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. Global non−uniformity is defined as Signal of ROI[i] = (ROI Average in counts − Horizontal overclock average in counts) * mV per count Where i = 1 to 864. During this calculation on the 864 sub regions of interest, the maximum and minimum signal levels GlobalNon−Uniformity + 100 ǒActiveAreaStandardDeviation Ǔ ActiveAreaSignal pixels in size. The average signal level of each of the 864 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Units: %rms. Active Area Signal = Active Area Average − Dark Column Average Global Peak to Peak Non−Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. The sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 GlobalUniformity + 100 Signal of ROI[i] = (ROI Average in counts − Horizontal overclock average in counts) * mV per count Where i = 1 to 864. During this calculation on the 864 sub regions of interest, the maximum and minimum signal levels are found. The global peak to peak uniformity is then calculated as: MaximumSignal * MinimumSignal ActiveAreaSignal the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels of the sensor. Center uniformity is defined as: Units: %pp Center Non−Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mV). Prior to this test being performed Center ROI Uniformity + 100 ROI Standard Deviation ǒCenterCenter Ǔ ROI Signal to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Units: %rms. Center ROI Signal = Center ROI Average − Dark Column Average Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the “Defect Definitions” section. Dark defect threshold = Active Area Signal * threshold Bright defect threshold = Active Area Signal * threshold The sensor is then partitioned into 864 sub regions of interest, each of which is 136 by 136 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 476 mV. Prior www.onsemi.com 17 KAI−16050 Example for major bright field defective pixels: • Average value of all active pixels is found to be 476 mV • Dark defect threshold: 476 mV * 12 % = 57 mV • Region of interest #1 selected. This region of interest is pixels 13, 13 to pixels 148, 148. ♦ Median of this region of interest is found to be 470 mV. ♦ Any pixel in this region of interest that is ≤ (470 − 57 mV) 413 mV in intensity will be marked defective. • All remaining 836 sub regions of interest are analyzed for defective pixels in the same manner. www.onsemi.com 18 KAI−16050 OPERATION Table 15. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Operating Temperature TOP −50 +70 °C 1 Humidity RH +5 +90 % 2 Output Bias Current Iout 60 mA 3 Off−chip Load CL 10 pF Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25°C. Excessive humidity will degrade MTTF. 3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Table 16. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND Description Minimum Maximum Units Notes VDDa, VOUTa −0.4 17.5 V 1 RDa −0.4 15.5 V 1 V1B, V1T ESD − 0.4 ESD + 24.0 V V2B, V2T, V3B, V3T, V4B, V4T ESD − 0.4 ESD + 14.0 V FDGab, FDGcd ESD − 0.4 ESD + 15.0 V H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGa ESD − 0.4 ESD + 14.0 V ESD −10.0 0.0 V SUB −0.4 40.0 V 1 2 1. a denotes a, b, c or d 2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Power−Up and Power−Down Sequence Adherence to the power−up and power−down sequence is critical. Failure to follow the proper power−up and power−down sequences may cause damage to the sensor. Do not pulse the electronic shutter until ESD is stable V+ VDD SUB time ESD V− VCCD Low HCCD Low Activate all other biases when ESD is stable and sub is above 3V Figure 14. Power−Up and Power−Down Sequence Notes: 1. Activate all other biases when ESD is stable and SUB is above 3 V 2. Do not pulse the electronic shutter until ESD is stable 3. VDD cannot be +15 V when SUB is 0 V 4. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground will protect www.onsemi.com 19 KAI−16050 the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See the figure below. The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage. Example of external diode protection for SUB, VDD and ESD. a denotes a, b, c or d VDDa 0.0V SUB GND ESD Figure 16. ESD ESD − 0.4V All VCCD Clocks absolute maximum overshoot of 0.4 V Figure 15. Table 17. DC BIAS OPERATING CONDITIONS Pins Symbol Minimum Nominal Maximum Units Maximum DC Current Notes Reset Drain RDa RD +11.8 +12.0 +12.2 V 10 mA 1 Output Gate OGa OG −2.2 −2.0 −1.8 V 10 mA 1 Output Amplifier Supply VDDa VDD +14.5 +15.0 +15.5 V 11.0 mA 1,2 Ground GND GND 0.0 0.0 0.0 V −1.0 mA Substrate SUB VSUB +5.0 VAB VDD V 50 mA 3, 8 ESD Protection Disable ESD ESD −9.5 −9.0 Vx_L V 50 mA 6, 7, 9 VOUTa Iout −3.0 −7.0 −10.0 mA Description Output Bias Current 1, 4, 5 1. a denotes a, b, c or d 2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 17. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is the nominal PNe (see Specifications). 4. An output load sink must be applied to each VOUT pin to activate each output amplifier. 5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise. 6. Adherence to the power−up and power−down sequence is critical. See Power−Up and Power−Down Sequence section. 7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V 8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions 9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application. www.onsemi.com 20 VDDa RDa Ra KAI−16050 Idd HCCD Floating Diffusion Iout OGa VOUTa Iss Source Follower #1 Source Follower #2 Figure 17. Output Amplifier www.onsemi.com 21 Source Follower #3 KAI−16050 AC Operating Conditions Table 18. CLOCK LEVELS Description Vertical CCD Clock, Phase 1 V1B, V1T Vertical CCD Clock, Phase 2 V2B, V2T Vertical CCD Clock, Phase 3 V3B, V3T Vertical CCD Clock, Phase 4 V4B, V4T Horizontal CCD Clock, Phase 1 Storage H1Sa Horizontal CCD Clock, Phase 1 Barrier H1Ba Horizontal CCD Clock, Phase 2 Storage H2Sa Horizontal CCD Clock, Phase 2 Barrier H2Ba Horizontal CCD Clock, Last Phase 3 H2SLa Reset Gate Ra Electronic Shutter 5 Fast Line Dump Gate 1. 2. 3. 4. 5. 6. 7. Pins1 Symbol Level Minimum Nominal Maximum Units Capacitance2 V 180 nF (6) V 180 nF (6) V 180 nF (6) V 180 nF (6) V 600 pF (6) V 400 pF (6) V 580 pF (6) V 400 pF (6) V 20 pF (6) V 16 pF (6) V1_L Low −8.2 −8.0 −7.8 V1_M Mid −0.2 0.0 +0.2 V1_H High +11.5 +12.0 +12.5 V2_L Low −8.2 −8.0 −7.8 V2_H High −0.2 0.0 +0.2 V3_L Low −8.2 −8.0 −7.8 V3_H High −0.2 0.0 +0.2 V4_L Low −8.2 −8.0 −7.8 V4_H High −0.2 0.0 +0.2 H1S_L Low −5.2 (7) −4.0 −3.8 H1S_A Amplitude +3.8 +4.0 +5.2 (7) H1B_L Low −5.2 (7) −4.0 −3.8 H1B_A Amplitude +3.8 +4.0 +5.2 (7) H2S_L Low −5.2 (7) −4.0 −3.8 H2S_A Amplitude +3.8 +4.0 +5.2 (7) H2B_L Low −5.2 (7) −4.0 −3.8 H2B_A Amplitude +3.8 +4.0 +5.2 (7) H2SL_L Low −5.2 −5.0 −4.8 H2SL_A Amplitude +4.8 +5.0 +5.2 R_L 4 Low −3.5 −2.0 −1.5 R_H High +2.5 +3.0 +4.0 SUB VES High +29.0 +30.0 +40.0 V 12 nF (6) FDGa FDG_L Low −8.2 −8.0 −7.8 V 50 pF (6) FDG_H High +4.5 +5.0 +5.5 a denotes a, b, c or d Capacitance is total for all like named pins Use separate clock driver for improved speed performance. Reset low should be set to –3 volts for signal levels greater than 40,000 electrons. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions Capacitance values are estimated If the minimum horizontal clock low level is used (–5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude) to create a –5.2 V to 0.0 V clock. If a 5 V clock driver is used, the horizontal low level should be set to –5.0 V and the high level should be a set to 0.0 V. The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. VES VSUB GND GND Figure 18. www.onsemi.com 22 KAI−16050 Device Identification The device identification pin (DevID) may be used to determine which ON Semiconductor 5.5 micron pixel interline CCD sensor is being used. Table 19. DEVICE IDENTIFICATION Description Device Identification Pins Symbol Minimum Nominal Maximum Units Maximum DC Current Notes DevID DevID 144,000 180,000 216,000 W 50 mA 1, 2, 3 1. Nominal value subject to verification and/or change during release of preliminary specifications. 2. If the Device Identification is not used, it may be left disconnected. 3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent localized heating of the sensor due to current flow through the R_DeviceID resistor. Recommended Circuit Note that V1 must be a different value than V2. V1 V2 R_external DevID ADC R_DeviceID GND KAI−16050 Figure 19. Device Identification Recommended Circuit www.onsemi.com 23 KAI−16050 TIMING Table 20. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units Photodiode Transfer tpd 3 − − ms VCCD Leading Pedestal t3p 4 − − ms VCCD Trailing Pedestal t3d 4 − − ms VCCD Transfer Delay td 4 − − ms VCCD Transfer tv 4 − − ms vVCR 75 100 % 1 tVR, tVF 5 − 10 % 1, 2 FDG Delay tfdg 2 − − ms HCCD Delay ths 1 − − ms HCCD Transfer te 25.0 − − ns Shutter Transfer tsub 1 − − ms Shutter Delay thd 1 − − ms Reset Pulse tr 2.5 − − ns Reset – Video Delay trv − 2.2 − ns VCCD Clock Cross−over VCCD Rise, Fall Times Notes H2SL – Video Delay thv − 3.1 − ns Line Time tline 69.3 − − ms 131.4 − − 115.5 − − 231.1 − − Dual HCCD Readout 437.8 − − Single HCCD Readout Frame Time tframe 1. Refer to Figure 25: VCCD Clock Rise Time, Fall Time and Edge Alignment 2. Relative to the pulse width 3. Refer to timing diagrams as shown in Figures 21, 22, 23, 24 and 25. www.onsemi.com 24 Dual HCCD Readout Single HCCD Readout ms Quad HCCD Readout KAI−16050 Timing Diagrams The timing sequence for the clocked device pins may be represented as one of seven patterns (P1−P7) as shown in the table below. The patterns are defined in Figure 21 and Figure 22. Contact ON Semiconductor Imaging Application Engineering for other readout modes. Table 21. Quad Readout Dual Readout VOUTa, VOUTb Dual Readout VOUTa, VOUTc Single Readout VOUTa V1T P1T P1B P1T P1B V2T P2T P4B P2T P4B V3T P3T P3B P3T P3B V4T P4T P2B P4T P2B Device Pin V1B P1B V2B P2B V3B P3B V4B P4B P5 H1Sa H1Ba H2Sa 2 P6 H2Ba Ra P7 P5 H1Sb P5 H1Bb H2Sb P6 2 P6 P6 H2Bb P5 Rb P7 P7 1 or Off 3 P7 1 or Off 3 P5 P5 1 or Off 3 P5 P5 1 or Off 3 P6 P6 1 or Off 3 P6 P6 1 or Off 3 Rc P7 P7 1 or Off 3 P7 P7 1 or Off 3 H1Sd P5 P5 1 or Off 3 P5 P5 1 or Off 3 P6 P6 1 or Off 3 H1Sc H1Bc H2Sc 2 H2Bc H1Bd H2Sd 2 P6 H2Bd Rd # Lines/Frame (Minimum) # Pixels/Line (Minimum) P6 1 or Off 3 P6 P5 P7 P7 1 or Off 3 P7 1 or Off 3 P7 1 or Off 3 1666 3332 1666 3332 2492 4984 1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should be a multiple of the frequency used on the a and b register. 2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver. 3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the unused c/d register into the image area. www.onsemi.com 25 KAI−16050 Photodiode Transfer Timing A row of charge is transferred to the HCCD on the falling edge of V1 as indicated in the P1 pattern below. Using this timing sequence, the leading dummy row or line is combined with the first dark row in the HCCD. The “Last Line” is dependent on readout mode – either 1666 or 3332 minimum counts required. It is important to note that, in Pattern td 1 2 t3p 3 tpd 4 t3d P1T 5 6 general, the rising edge of a vertical clock (patterns P1−P4) should be coincident or slightly leading a falling edge at the same time interval. This is particularly true at the point where P1 returns from the high (3rd level) state to the mid−state when P4 transitions from the low state to the high state. td tv tv tv/2 tv/2 P2T tv/2 tv/2 P3T P4T tv P1B tv/2 tv tv/2 P2B P3B P4B ths P5 Last Line ths L1 + Dummy Line L2 P6 P7 Figure 20. Photodiode Transfer Timing Line and Pixel Timing Each row of charge is transferred to the output, as illustrated below, on the falling edge of H2SL (indicated as P6 pattern). The number of pixels in a row is dependent on Pattern P1T tline tv tv P1B ths P5 P6 readout mode – either 2492 or 4984 minimum counts required. te/2 te tr P7 VOUT Pixel 1 Pixel 34 Pixel n Figure 21. Line and Pixel Timing www.onsemi.com 26 KAI−16050 Pixel Timing Detail P5 P6 P7 VOUT thv trv Figure 22. Pixel Timing Detail Frame/Electronic Shutter Timing The resulting photodiode integration time is defined from the falling edge of SUB to the falling edge of V1 (P1 pattern). The SUB pin may be optionally clocked to provide electronic shuttering capability as shown below. tframe Pattern P1T/P4B SUB P6 thd tint tsub thd Figure 23. Frame/Electronic Shutter Timing VCCD Clock Edge Alignment VVCR 90% tV 10% tVF tVR tV tVF tVR Figure 24. VCCD Clock Rise Time, Fall Time and Edge Alignment www.onsemi.com 27 KAI−16050 Line and Pixel Timing − Vertical Binning by 2 tv tv tv ths P1T P2T P3T P4T P1B P2B P3B P4B ths P5 P6 P7 VOUT Pixel 1 Pixel n Pixel 34 Figure 25. Line and Pixel Timing − Vertical Binning by 2 Fast Line Dump Timing The FDG pins may be optionally clocked to efficiently remove unwanted lines in the image resulting for increased frame rates at the expense of resolution. Below is an example of a 2 line dump sequence followed by a normal readout line. Note that the FDG timing transitions should complete prior to the beginning of V1 timing transitions as illustrated below. Figure 26. Fast Line Dump Timing www.onsemi.com 28 KAI−16050 STORAGE AND HANDLING Table 22. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature TST −55 +80 °C 1 Humidity RH 5 90 % 2 1. Long term storage toward the maximum temperature will accelerate color filter degradation. 2. T = 25°C. Excessive humidity will degrade MTTF. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. www.onsemi.com 29 KAI−16050 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for marking code. 2. No materials to interfere with clearance through package holes. 3. Units: IN [MM] Figure 27. Completed Assembly (1 of 2) www.onsemi.com 30 KAI−16050 Notes: 1. Units IN [MM] Figure 28. Completed Assembly (2 of 2) www.onsemi.com 31 KAI−16050 Cover Glass Notes: 1. Substrate = Schott D263T eco 2. Dust, Scratch, Inclusion Specification: a.) 20 mm Max size in Zone A 3. MAR coated both sides 4. Spectral Transmission a.) 350 − 365 nm: T ≥ 88% b.) 365 − 405 nm: T ≥ 94% c.) 405 − 450 nm: T ≥ 98% d.) 450 − 650 nm: T ≥ 99% e.) 650 − 690 nm: T ≥ 98% f.) 690 − 770 nm: T ≥ 94% g.) 770 − 870 nm: T ≥ 88% 5. Units: IN [MM] Figure 29. Cover Glass www.onsemi.com 32 KAI−16050 Cover Glass Transmission Figure 30. Cover Glass Transmission ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 33 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAI−16050/D