KAI 08050 D

KAI-08050
3296 (H) x 2472 (V)
Interline CCD Image Sensor
Description
The KAI−08050 Image Sensor is an 8−megapixel CCD in a 4/3”
optical format. Based on the TRUESENSE 5.5 micron Interline
Transfer CCD Platform, the sensor features broad dynamic range,
excellent imaging performance, and a flexible readout architecture
that enables use of 1, 2, or 4 outputs. The sensor supports full
resolution readout up to 16 frames per second, while a Region of
Interest (ROI) mode supports partial readout of the sensor at even
higher frame rates. A vertical overflow drain structure suppresses
image blooming and enables electronic shuttering for precise exposure
control.
The sensor is available with the TRUESENSE Sparse Color Filter
Pattern, a technology which provides a 2x improvement in light
sensitivity compared to a standard color Bayer part.
The sensor shares common pin−out and electrical configurations
with other devices based on the TRUESENSE 5.5 micron Interline
Transfer Platform, allowing a single camera design to support multiple
members of this sensor family.
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Figure 1. KAI−08050 CCD Image Sensor
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Typical Value
Interline CCD; Progressive Scan
3364 (H) x 2520 (V)
3320 (H) x 2496 (V)
3296 (H) x 2472 (V)
5.5 mm (H) x 5.5 mm (V)
18.13 mm (H) x 13.60 mm (V)
22.66 mm (diag), 4/3” optical format
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Quantum Efficiency
Pan (−ABA, −PBA)
R, G, B (−CBA, −PBA)
Read Noise (f = 40 MHz)
Dark Current
Photodiode
VCCD
Dark Current Doubling Temp.
Photodiode
VCCD
Dynamic Range
Charge Transfer Efficiency
Blooming Suppression
Smear
Image Lag
Maximum Pixel Clock Speed
Maximum Frame Rates
Quad Output
Dual Output
Single Output
Package
Cover Glass
4:3
1, 2, or 4
20,000 electrons
34 mV/e−
46%
29%, 37%, 39%
12 electrons rms
7 electrons/s
100 electrons/s
Features
• Bayer Color Pattern, TRUESENSE Sparse
•
•
•
•
•
•
•
Color Filter Pattern, and Monochrome
Configuration
Progressive Scan Readout
Flexible Readout Architecture
High Frame Rate
High Sensitivity
Low Noise Architecture
Excellent Smear Performance
Package Pin Reserved for Device
Identification
Applications
• Industrial Imaging
• Medical Imaging
• Security
7°C
9°C
64 dB
0.999999
> 300 X
−100 dB
< 10 electrons
40 MHz
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
16 fps
8 fps
4 fps
68 pin PGA
AR coated, 2 Sides or Clear Glass
NOTE: All parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 7
1
Publication Order Number:
KAI−08050/D
KAI−08050
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number
Description
KAI−08050−AAA−JP−BA
Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass, no coatings, Standard Grade
KAI−08050−AAA−JP−AE
Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass, no coatings, Engineering Grade
KAI−08050−ABA−JD−BA
Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Standard Grade
KAI−08050−ABA−JD−AE
Monochrome, Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Engineering Grade
KAI−08050−ABA−JP−BA
Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass, no coatings, Standard Grade
KAI−08050−ABA−JP−AE
Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass, no coatings, Engineering Grade
KAI−08050−CBA−JD−BA
Gen1 Color (Bayer RGB), Telecentric Microlens,
PGA Package, Sealed Clear Cover Glass with AR coating
(both sides), Standard Grade
KAI−08050−CBA−JD−AE
Gen1 Color (Bayer RGB), Telecentric Microlens,
PGA Package, Sealed Clear Cover Glass with AR coating
(both sides), Engineering Grade
KAI−08050−CBA−JB−B2
Gen1 Color (Bayer RGB), Telecentric Microlens,
PGA Package, Sealed Clear Cover Glass (no coatings),
Grade 2
KAI−08050−CBA−JB−AE
Gen1 Color (Bayer RGB), Telecentric Microlens,
PGA Package, Sealed Clear Cover Glass (no coatings),
Engineering Grade
KAI−08050−PBA−JD−BA
Gen1 Color (TRUESENSE Sparse CFA),
Telecentric Microlens, PGA Package, Sealed Clear Cover
Glass with AR coating (both sides), Standard Grade
KAI−08050−PBA−JD−AE
Gen1 Color (TRUESENSE Sparse CFA),
Telecentric Microlens, PGA Package, Sealed Clear Cover
Glass with AR coating (both sides), Engineering Grade
Marking Code
KAI−08050−AAA
Serial Number
KAI−08050−ABA
Serial Number
KAI−08050−CBA
Serial Number
KAI−08050−PBA
Serial Number
NOTE: Not recommended for new designs. Consider device KAI−08051.
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−08050
DEVICE DESCRIPTION
Architecture
H2Bd
H2Sd
H1Bd
H1Sd
SUB
H2Bc
H2Sc
H1Bc
H1Sc
RDc
Rc
VDDc
VOUTc
RDd
Rd
VDDd
VOUTd
HLOD
1 10 22 12
8
1648
1648
12
8 22 10 1
1 Dummy
12
12
GND
OGc
H2SLc
GND
OGd
H2SLd
V1T
V2T
V3T
V4T
V1T
V2T
V3T
V4T
DevID
ESD
3296H x 2472V
5.5 mm x 5.5 mm Pixels
22 12
12 22
V1B
V2B
V3B
V4B
RDa
Ra
VDDa
VOUTa
ESD
V1B
V2B
V3B
V4B
12 Buffer
12 Dark
1 Dummy (Last VCCD Phase = V1 → H1S)
1 10 22 12
8
1648
H2Bb
H2Sb
H1Bb
H1Sb
SUB
H2Ba
H2Sa
H1Ba
H1Sa
GND
OGa
H2SLa
1648
HLOD
12
8 22 10 1
RDb
Rb
VDDb
VOUTb
GND
OGb
H2SLb
Figure 2. Block Diagram
Dark Reference Pixels
Active Buffer Pixels
There are 12 dark reference rows at the top and 12 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
12 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and non−uniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non−linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
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3
KAI−08050
ESD Protection
power−down sequences may cause damage to the sensor.
See Power−Up and Power−Down Sequence section.
Adherence to the power−up and power−down sequence is
critical. Failure to follow the proper power−up and
Bayer Color Filter Pattern
H2Bd
H2Sd
H1Bd
H1Sd
SUB
H2Bc
H2Sc
H1Bc
H1Sc
RDc
Rc
VDDc
VOUTc
RDd
Rd
VDDd
VOUTd
HLOD
1 10 22 12
8
1648
1648
12
8 22 10 1
1 Dummy
12
12
GND
OGc
H2SLc
BG
G R
V1T
V2T
V3T
V4T
GND
OGd
H2SLd
BG
G R
V1T
V2T
V3T
V4T
DevID
ESD
22 12
V1B
V2B
V3B
V4B
RDa
Ra
VDDa
VOUTa
3296H x 2472V
5.5 mm x 5.5 mm Pixels
12 22
V1B
V2B
V3B
V4B
BG
G R
12 Buffer
12 Dark
1 Dummy (Last VCCD Phase = V1 → H1S)
BG
G R
1 10 22 12
8
1648
1648
ESD
RDb
Rb
VDDb
VOUTb
12
8 22 10 1
HLOD
GND
OGb
H2SLb
H2Bb
H2Sb
H1Bb
H1Sb
SUB
H2Ba
H2Sa
H1Ba
H1Sa
GND
OGa
H2SLa
Figure 3. Bayer Color Filter Pattern
TRUESENSE Sparse Color Filter Pattern
H2Bd
H2Sd
H1Bd
H1Sd
SUB
H2Bc
H2Sc
H1Bc
H1Sc
RDc
Rc
VDDc
VOUTc
RDd
Rd
VDDd
VOUTd
HLOD
1648
1 10 22 12
8
1648
12
8 22 10 1
1 Dummy
12
12
GND
OGc
H2SLc
G
P
B
P
V1T
V2T
V3T
V4T
P
G
P
B
R
P
G
P
GND
OGd
H2SLd
P
R
P
G
G
P
B
P
P
G
P
B
R
P
G
P
P
R
P
G
V1T
V2T
V3T
V4T
DevID
ESD
22 12
V1B
V2B
V3B
V4B
RDa
Ra
VDDa
VOUTa
G
P
B
P
P
G
P
B
R
P
G
P
P
R
P
G
12 22
G
P
B
P
P
G
P
B
R
P
G
P
1 10 22 12
8
1648
1648
12
8 22 10 1
HLOD
H2Bb
H2Sb
H1Bb
H1Sb
SUB
Figure 4. TRUESENSE Sparse Color Filter Pattern
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4
ESD
V1B
V2B
V3B
V4B
P
R
P
G
12 Buffer
12 Dark
1 Dummy (Last VCCD Phase = V1 → H1S)
H2Ba
H2Sa
H1Ba
H1Sa
GND
OGa
H2SLa
3296H x 2472V
5.5 mm x 5.5 mm Pixels
RDb
Rb
VDDb
VOUTb
GND
OGb
H2SLb
KAI−08050
PHYSICAL DESCRIPTION
Pin Description and Device Orientation
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35
V3T
V1T
VDDc
GND
Rc
H2SLc
H1Bc
H2Sc
N/C
H2Sd
H1Bd
H2SLd
Rd
GND
VDDd
V1T
V3T
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36
ESD
V4T
V2T
VOUTc
RDc
OGc
H2Bc
H1Sc
SUB
H1Sd
H2Bd
OGd
RDd
VOUTd
V2T
V4T
DevID
Pixel
(1,1)
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
V4B
V2B
VOUTa
RDa
OGa
H2Ba
H1Sa
SUB
H1Sb
H2Bb
OGb
RDb
VOUTb
V2B
V4B
ESD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
V3B
V1B
VDDa
GND
Ra
H2SLa
H1Ba
H2Sa
N/C
H2Sb
H1Bb
H2SLb
Rb
GND
VDDb
V1B
V3B
Figure 5. Package Pin Designations − Top View
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5
KAI−08050
Table 3. PIN DESCRIPTION
Pin
Name
1
V3B
Description
Vertical CCD Clock, Phase 3, Bottom
Pin
Name
Description
68
ESD
ESD Protection Disable
67
V3T
Vertical CCD Clock, Phase 3, Top
66
V4T
Vertical CCD Clock, Phase 4, Top
V1T
Vertical CCD Clock, Phase 1, Top
Vertical CCD Clock, Phase 2, Top
3
V1B
Vertical CCD Clock, Phase 1, Bottom
65
4
V4B
Vertical CCD Clock, Phase 4, Bottom
64
V2T
VDDc
Output Amplifier Supply, Quadrant c
Video Output, Quadrant c
5
VDDa
Output Amplifier Supply, Quadrant a
63
6
V2B
Vertical CCD Clock, Phase 2, Bottom
62
VOUTc
7
GND
Ground
61
GND
Ground
8
VOUTa
Video Output, Quadrant a
60
RDc
Reset Drain, Quadrant c
9
Ra
Reset Gate, Quadrant a
59
Rc
Reset Gate, Quadrant c
10
RDa
Reset Drain, Quadrant a
58
OGc
Output Gate, Quadrant c
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant a
57
H2SLc
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant c
11
H2SLa
12
OGa
Output Gate, Quadrant a
56
H2Bc
13
H1Ba
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant a
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant c
55
H1Bc
14
H2Ba
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant a
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant c
54
H1Sc
15
H2Sa
Horizontal CCD Clock, Phase 2,
Storage, Quadrant a
Horizontal CCD Clock, Phase 1,
Storage, Quadrant c
53
H2Sc
16
H1Sa
Horizontal CCD Clock, Phase 1,
Storage, Quadrant a
Horizontal CCD Clock, Phase 2,
Storage, Quadrant c
52
SUB
Substrate
N/C
No Connect
17
N/C
No Connect
51
18
SUB
Substrate
50
H1Sd
19
H2Sb
Horizontal CCD Clock, Phase 2,
Storage, Quadrant b
Horizontal CCD Clock, Phase 1,
Storage, Quadrant d
49
H2Sd
20
H1Sb
Horizontal CCD Clock, Phase 1,
Storage, Quadrant b
Horizontal CCD Clock, Phase 2,
Storage, Quadrant d
48
H2Bd
21
H1Bb
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant b
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant d
47
H1Bd
22
H2Bb
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant b
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant d
46
OGd
Output Gate, Quadrant d
23
H2SLb
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant b
45
H2SLd
24
OGb
Output Gate, Quadrant b
44
RDd
Reset Drain, Quadrant d
25
Rb
Reset Gate, Quadrant b
43
Rd
Reset Gate, Quadrant d
26
RDb
Reset Drain, Quadrant b
42
VOUTd
27
GND
Ground
41
GND
Ground
28
VOUTb
Video Output, Quadrant b
40
V2T
Vertical CCD Clock, Phase 2, Top
29
VDDb
Output Amplifier Supply, Quadrant b
39
VDDd
V4T
Vertical CCD Clock, Phase 4, Top
Vertical CCD Clock, Phase 1, Top
30
V2B
Vertical CCD Clock, Phase 2, Bottom
38
31
V1B
Vertical CCD Clock, Phase 1, Bottom
37
V1T
32
V4B
Vertical CCD Clock, Phase 4, Bottom
36
DevID
33
V3B
Vertical CCD Clock, Phase 3, Bottom
35
V3T
34
ESD
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant d
Video Output, Quadrant d
Output Amplifier Supply, Quadrant d
Device Identification
Vertical CCD Clock, Phase 3, Top
1. Liked named pins are internally connected and should have a
common drive signal.
2. N/C pins (17, 51) should be left floating.
ESD Protection Disable
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KAI−08050
IMAGING PERFORMANCE
Table 4. TYPICAL OPERATION CONDITIONS
Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.
Condition
Description
Notes
Light Source
Continuous red, green and blue LED illumination
Operation
Nominal operating voltages and timing
For monochrome sensor, only
green LED used.
Table 5. SPECIFICATIONS
All Configurations
Description
Dark Field Global Non−Uniformity
Symbol
Min.
Nom.
Max.
Units
DSNU
−
−
2
mVpp
Die
27, 40
−
2
5
%rms
Die
27, 40
1
−
5
15
%pp
Die
27, 40
1
−
1
2
%rms
Die
27, 40
1
Bright Field Global Non−Uniformity
Bright Field Global Peak to Peak
Non−Uniformity
Temperature
Tested At
(5C)
Sampling
Plan
PRNU
Bright Field Center Non−Uniformity
Notes
Maximum Photoresponse Nonlinearity
NL
−
2
−
%
Design
2
Maximum Gain Difference Between
Outputs
DG
−
10
−
%
Design
2
Maximum Signal Error due to
Nonlinearity Differences
DNL
−
1
−
%
Design
2
Horizontal CCD Charge Capacity
HNe
−
55
−
ke−
Design
Vertical CCD Charge Capacity
VNe
−
40
−
ke−
Design
Photodiode Charge Capacity
PNe
−
20
−
ke−
Die
Horizontal CCD Charge Transfer
Efficiency
HCTE
0.999995
0.999999
−
Die
Vertical CCD Charge Transfer
Efficiency
VCTE
0.999995
0.999999
−
Die
Photodiode Dark Current
Ipd
−
7
70
e/p/s
Die
40
Vertical CCD Dark Current
Ivd
−
100
300
e/p/s
Die
40
Image Lag
Lag
−
−
10
e−
Design
Antiblooming Factor
Xab
300
−
−
Vertical Smear
Smr
−
−100
−
dB
Design
Read Noise
ne−T
−
12
−
e−rms
Design
4
Dynamic Range
DR
−
64
−
dB
Design
4, 5
Output Amplifier DC Offset
Vodc
−
9.4
−
V
Die
Output Amplifier Bandwidth
f−3db
−
250
−
MHz
Die
Output Amplifier Impedance
ROUT
−
127
−
W
Die
−
mV/e−
Design
Output Amplifier Sensitivity
DV/DN
−
34
27, 40
3
Design
27, 40
6
27, 40
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is 680 mV.
4. At 40 MHz
5. Uses 20LOG (PNe/ ne−T)
6. Assumes 5 pF load.
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7
KAI−08050
Table 6. KAI−08050−ABA AND KAI−08050−PBA CONFIGURATIONS
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Peak Quantum Efficiency
QEmax
−
44
−
%
Design
Peak Quantum Efficiency
Wavelength
lQE
−
480
−
nm
Design
Description
Temperature
Tested At
(5C)
Notes
7
7. Not recommended for new designs. Consider device KAI−08051.
Table 7. KAI−08050−CBA AND KAI−08050−PBA GEN1 COLOR CONFIGURATIONS WITH MAR GLASS
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Temperature
Tested At
(5C)
Notes
Peak Quantum Efficiency
Blue
Green
Red
QEmax
−
39
37
29
−
%
Design
7
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE
−
470
540
620
−
nm
Design
7
Table 8. KAI−08050−CBA GEN1 COLOR CONFIGURATION WITH CLEAR GLASS
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Temperature
Tested At
(5C)
Notes
Peak Quantum Efficiency
Blue
Green
Red
QEmax
−
36
34
27
−
%
Design
7
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE
−
470
540
620
−
nm
Design
7
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8
KAI−08050
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome, all configurations
Figure 6. Monochrome Configurations − Quantum Efficiency
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9
KAI−08050
Color (Bayer RGB) with Microlens (Gen1 CFA)
Figure 7. Color with Microlens Quantum Efficiency
Color (TRUESENSE Sparse CFA) with Microlens (Gen1 CFA)
Figure 8. Color (TRUESENSE Sparse CFA) with Microlens Quantum Efficiency
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10
KAI−08050
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light
angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle
is varied in a plane parallel to the VCCD.
Monochrome with Microlens
100
90
Vertical
Relative Quantum Efficiency (%)
80
70
60
50
Horizontal
40
30
20
10
0
−30
−20
−10
0
10
20
30
Angle (degrees)
Figure 9. Monochrome with Microlens Angular Quantum Efficiency
Dark Current versus Temperature
10000
Dark Current (e/s)
1000
VCCD
100
10
Photodiode
1
0.1
1000/T (K) 2.9
T ( C) 72
3.0
3.1
3.2
3.3
3.4
60
50
40
30
21
Figure 10. Dark Current versus Temperature
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11
KAI−08050
Power − Estimated
1.2
1.0
Power (W)
0.8
0.6
0.4
0.2
0.0
10
15
20
25
30
35
40
HCCD Frequency (MHz)
Single
Dual
Quad
Figure 11. Power
Frame Rate (fps)
Frame Rates
20
20
18
18
16
16
14
14
12
12
10
10
8
8
6
6
4
4
2
2
0
0
10
15
20
25
30
35
HCCD Frequency (MHz)
Single
Dual (Left/Right)
Figure 12. Frame Rates
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12
Quad
40
KAI−08050
DEFECT DEFINITIONS
Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C
Description
Condition
Notes
Operational Mode
Two outputs, using VOUTa and VOUTc, continuous readout
HCCD Clock Frequency
10 MHz
Pixels Per Line
3520
1
Lines Per Frame
1360
2
Line Time
354.9 msec
Frame Time
482.7 msec
Photodiode Integration Time
Mode A: PD_Tint = Frame Time = 482.7 msec, no electronic shutter used
Mode B: PD_Tint = 33 msec, electronic shutter used
1.
2.
3.
4.
VCCD Integration Time
447.2 msec
Temperature
40°C
3
Light Source
Continuous red, green and blue LED illumination
Operation
Nominal operating voltages and timing
4
Horizontal overclocking used.
Vertical overclocking used.
VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers.
For monochrome sensor, only the green LED is used.
Table 10. DEFECT DEFINITIONS FOR TESTING AT 405C
Description
Definition
Standard Grade
Grade 2
Notes
80
80
1
Major dark field defective bright pixel
PD_Tint = Mode A → Defect ≥ 166 mV
or
PD_Tint = Mode B → Defect ≥ 12 mV
Major bright field defective dark pixel
Defect ≥ 12%
Minor dark field defective bright pixel
PD_Tint = Mode A → Defect ≥ 86 mV
or
PD_Tint = Mode B → Defect ≥ 6 mV
800
800
Cluster defect
A group of 2 to 10 contiguous major defective
pixels, but no more than 3 adjacent defects
horizontally.
15
n/a
2
Cluster defect (grade 2)
A group of 2 to 10 contiguous major defective
pixels
n/a
15
2
Column defect
A group of more than 10 contiguous major
defective pixels along a single column
0
0
2
1. For the color device (KAI−08050−CBA or KAI−08050−PBA), a bright field defective pixel deviates by 12% with respect to pixels of the same
color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
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KAI−08050
Table 11. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C
Description
1.
2.
3.
4.
Condition
Notes
Operational Mode
Two outputs, using VOUTa and VOUTc, continuous readout
HCCD Clock Frequency
20 MHz
Pixels Per Line
3520
1
Lines Per Frame
1360
2
Line Time
177.8 msec
Frame Time
241.8 msec
Photodiode Integration Time
(PD_Tint)
Mode A: PD_Tint = Frame Time = 241.8 msec, no electronic shutter used
VCCD Integration Time
224.0 msec
Temperature
27°C
Light Source
Continuous red, green and blue LED illumination
Operation
Nominal operating voltages and timing
Mode B: PD_Tint = 33 msec, electronic shutter used
3
4
Horizontal overclocking used.
Vertical overclocking used.
VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers.
For monochrome sensor, only the green LED is used.
Table 12. DEFECT DEFINITIONS FOR TESTING AT 275C
Description
Definition
Standard Grade
Grade 2
Notes
80
80
1
A group of 2 to 10 contiguous major defective
pixels, but no more than 3 adjacent defects
horizontally.
15
n/a
2
Cluster defect (grade 2)
A group of 2 to 10 contiguous major defective
pixels
n/a
15
2
Column defect
A group of more than 10 contiguous major
defective pixels along a single column
0
0
2
Major dark field defective bright pixel
PD_Tint = Mode A → Defect ≥ 26 mV
or
PD_Tint = Mode B → Defect ≥ 4 mV
Major bright field defective dark pixel
Defect ≥ 12%
Cluster defect
1. For the color device (KAI−08050−CBA or KAI−08050−PBA), a bright field defective pixel deviates by 12% with respect to pixels of the same
color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
Defect Map
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps. See
Figure 13: Regions of interest for the location of pixel 1,1.
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
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KAI−08050
TEST DEFINITIONS
Test Regions of Interest
Image Area ROI:
Pixel (1, 1) to Pixel (3320, 2496)
Active Area ROI:
Pixel (13, 13) to Pixel (3308, 2484)
Center ROI:
Pixel (1611, 1199) to Pixel (1710, 1298)
Only the Active Area ROI pixels are used for performance and defect tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 13 for a pictorial representation of the regions of
interest.
VOUTc
12 dark rows
12 buffer rows
12 buffer rows
12 dark rows
VOUTa
Figure 13. Regions of Interest
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15
Horizontal Overclock
1, 1
22 dark columns
Pixel
12 buffer columns
12 buffer columns
22 dark columns
Pixel
13,
13
3296 x 2472
Active Pixels
KAI−08050
Tests
are found. The dark field global uniformity is then calculated
as the maximum signal found minus the minimum signal
level found.
Units: mVpp (millivolts peak to peak)
Dark Field Global Non−Uniformity
This test is performed under dark field conditions. The
sensor is partitioned into 768 sub regions of interest, each of
which is 103 by 103 pixels in size. The average signal level
of each of the 768 sub regions of interest is calculated. The
signal level of each of the sub regions of interest is calculated
using the following formula:
Dark Field Global Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 476 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 680 mV. Global non−uniformity is
defined as
Signal of ROI[i] = (ROI Average in counts − Horizontal
overclock average in counts) * mV per count
Where i = 1 to 768. During this calculation on the 768 sub
regions of interest, the maximum and minimum signal levels
GlobalNon−Uniformity + 100
ǒActiveAreaStandardDeviation
Ǔ
ActiveAreaSignal
pixels in size. The average signal level of each of the 768 sub
regions of interest (ROI) is calculated. The signal level of
each of the sub regions of interest is calculated using the
following formula:
Units: %rms.
Active Area Signal = Active Area Average − Dark Column
Average
Global Peak to Peak Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 476 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 680 mV. The sensor is partitioned
into 768 sub regions of interest, each of which is 103 by 103
GlobalNon−Uniformity + 100
Signal of ROI[i] = (ROI Average in counts − Horizontal
overclock average in counts) * mV per count
Where i = 1 to 768. During this calculation on the 768 sub
regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then
calculated as:
MaximumSignal * MinimumSignal
ActiveAreaSignal
the substrate voltage has been set such that the charge
capacity of the sensor is 680 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels of the sensor. Center uniformity is
defined as:
Units: %pp
Center Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 476 mV). Prior to this test being performed
Center ROI Uniformity + 100
ROI Standard Deviation
ǒCenterCenter
Ǔ
ROI Signal
to this test being performed the substrate voltage has been set
such that the charge capacity of the sensor is 680 mV. The
average signal level of all active pixels is found. The bright
and dark thresholds are set as:
Units: %rms.
Center ROI Signal = Center ROI Average − Dark Column
Average
Dark Field Defect Test
This test is performed under dark field conditions. The
sensor is partitioned into 768 sub regions of interest, each of
which is 103 by 103 pixels in size. In each region of interest,
the median value of all pixels is found. For each region of
interest, a pixel is marked defective if it is greater than or
equal to the median value of that region of interest plus the
defect threshold specified in the “Defect Definitions”
section.
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold
The sensor is then partitioned into 768 sub regions of
interest, each of which is 103 by 103 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Bright Field Defect Test
This test is performed with the imager illuminated to a
level such that the output is at approximately 476 mV. Prior
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16
KAI−08050
Example for major bright field defective pixels:
• Average value of all active pixels is found to be
476 mV
• Dark defect threshold: 476 mV * 12 % = 57 mV
• Bright defect threshold: 476 mV * 12 % = 57 mV
• Region of interest #1 selected. This region of interest is
pixels 13, 13 to pixels 115, 115.
♦ Median of this region of interest is found to be
470 mV.
Any pixel in this region of interest that
is ≥ (470 + 57 mV) 527 mV in intensity will be
marked defective.
♦ Any pixel in this region of interest that
is ≤ (470 − 57 mV) 413 mV in intensity will be
marked defective.
All remaining 768 sub regions of interest are analyzed
for defective pixels in the same manner.
♦
•
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17
KAI−08050
OPERATION
Table 13. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Operating Temperature
TOP
−50
+70
°C
1
Humidity
RH
+5
+90
%
2
Output Bias Current
Iout
60
mA
3
Off−chip Load
CL
10
pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 14. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description
Minimum
Maximum
Units
Notes
VDDa, VOUTa
−0.4
17.5
V
1
RDa
−0.4
15.5
V
1
V1B, V1T
ESD − 0.4
ESD + 24.0
V
V2B, V2T, V3B, V3T, V4B, V4T
ESD − 0.4
ESD + 14.0
V
H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGa
ESD − 0.4
ESD + 14.0
V
ESD
−10.0
0.0
V
SUB
−0.4
40.0
V
1
2
1. a denotes a, b, c or d
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Power−Up and Power−Down Sequence
Adherence to the power−up and power−down sequence is critical. Failure to follow the proper power−up and power−down
sequences may cause damage to the sensor.
Do not pulse the electronic shutter
until ESD is stable
V+
VDD
SUB
time
ESD
V−
VCCD
Low
HCCD
Low
Activate all other biases when
ESD is stable and sub is above 3V
Figure 14. Power−Up and Power−Down Sequence
limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD
must always be less than GND. Placing diodes
between SUB, VDD, ESD and ground will protect
the sensor from accidental overshoots of SUB,
VDD and ESD during power on and power off.
See the figure below.
Notes:
1. Activate all other biases when ESD is stable and
SUB is above 3 V
2. Do not pulse the electronic shutter until ESD is
stable
3. VDD cannot be +15 V when SUB is 0 V
4. The image sensor can be protected from an
accidental improper ESD voltage by current
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KAI−08050
The VCCD clock waveform must not have a negative
overshoot more than 0.4 V below the ESD voltage.
Example of external diode protection for SUB, VDD and
ESD. a denotes a, b, c or d
0.0V
VDDa
SUB
GND
ESD
ESD − 0.4V
All VCCD Clocks absolute
maximum overshoot of 0.4 V
ESD
Figure 15.
Figure 16.
Table 15. DC BIAS OPERATING CONDITIONS
Pins
Symbol
Minimum
Nominal
Maximum
Units
Maximum DC
Current
Notes
Reset Drain
RDa
RD
+11.8
+12.0
+12.2
V
10 mA
1
Output Gate
OGa
OG
−2.2
−2.0
−1.8
V
10 mA
1
Output Amplifier Supply
VDDa
VDD
+14.5
+15.0
+15.5
V
11.0 mA
1,2
Ground
GND
GND
0.0
0.0
0.0
V
−1.0 mA
Substrate
SUB
VSUB
+5.0
VAB
VDD
V
50 mA
3, 8
ESD Protection Disable
ESD
ESD
−9.2
−9.0
Vx_L
V
50 mA
6, 7, 9
VOUTa
Iout
−3.0
−7.0
−10.0
mA
Description
Output Bias Current
1, 4, 5
1. a denotes a, b, c or d
2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 17.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is the nominal PNe (see Specifications).
4. An output load sink must be applied to each VOUT pin to activate each output amplifier.
5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.
6. Adherence to the power−up and power−down sequence is critical. See Power−Up and Power−Down Sequence section.
7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V
8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application.
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19
VDDa
RDa
Ra
KAI−08050
Idd
HCCD
Floating
Diffusion
Iout
OGa
VOUTa
Iss
Source
Follower
#1
Source
Follower
#2
Figure 17. Output Amplifier
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20
Source
Follower
#3
KAI−08050
AC Operating Conditions
Table 16. CLOCK LEVELS
Description
Vertical CCD Clock,
Phase 1
V1B, V1T
Vertical CCD Clock,
Phase 2
V2B, V2T
Vertical CCD Clock,
Phase 3
V3B, V3T
Vertical CCD Clock,
Phase 4
V4B, V4T
Horizontal CCD Clock,
Phase 1 Storage
H1Sa
Horizontal CCD Clock,
Phase 1 Barrier
H1Ba
Horizontal CCD Clock,
Phase 2 Storage
H2Sa
Horizontal CCD Clock,
Phase 2 Barrier
H2Ba
Horizontal CCD Clock,
Last Phase 3
H2SLa
Reset Gate
Ra
Electronic Shutter 5
1.
2.
3.
4.
5.
6.
7.
Pins1
SUB
Symbol
Level
Minimum
Nominal
Maximum
Units
Capacitance2
V
43 nF (6)
V
43 nF (6)
V
43 nF (6)
V
43 nF (6)
V
280 pF (6)
V
190 pF (6)
V
280 pF (6)
V
190 pF (6)
V
20 pF (6)
V
16 pF (6)
V
3 nF (6)
V1_L
Low
−8.2
−8
−7.8
V1_M
Mid
−0.2
0
0.2
V1_H
High
11.5
12
12.5
V2_L
Low
−8.2
−8
−7.8
V2_H
High
−0.2
0
0.2
V3_L
Low
−8.2
−8
−7.8
V3_H
High
−0.2
0
0.2
V4_L
Low
−8.2
−8
−7.8
V4_H
High
−0.2
0
0.2
H1S_L
Low
−5.2 (7)
−4
−3.8
H1S_A
Amplitude
3.8
4
+5.2 (7)
H1B_L
Low
−5.2 (7)
−4
−3.8
H1B_A
Amplitude
3.8
4
+5.2 (7)
H2S_L
Low
−5.2 (7)
−4
−3.8
H2S_A
Amplitude
3.8
4
+5.2 (7)
H2B_L
Low
−5.2 (7)
−4
−3.8
H2B_A
Amplitude
3.8
4
+5.2 (7)
H2SL_L
Low
−5.2
−5
−4.8
H2SL_A
Amplitude
4.8
5
5.2
R_L
4
Low
−3.5
−2
−1.5
R_H
High
2.5
3
4
VES
High
29
30
40
a denotes a, b, c or d
Capacitance is total for all like named pins
Use separate clock driver for improved speed performance.
Reset low should be set to –3 volts for signal levels greater than 40,000 electrons.
Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
Capacitance values are estimated
If the minimum horizontal clock low level is used (–5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude)
to create a –5.2 V to 0.0 V clock. If a 5 volt clock driver is used, the horizontal low level should be set to –5.0 V and the high level should
be a set to 0.0 V.
The figure below shows the DC bias (VSUB) and AC
clock (VES) applied to the SUB pin. Both the DC bias and
AC clock are referenced to ground.
VES
VSUB
GND
GND
Figure 18.
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21
KAI−08050
Device Identification
The device identification pin (DevID) may be used to determine which Truesense Imaging 5.5 micron pixel interline CCD
sensor is being used.
Table 17. DEVICE IDENTIFICATION
Description
Device Identification
Pins
Symbol
Minimum
Nominal
Maximum
Units
Maximum DC
Current
Notes
DevID
DevID
8,000
10,000
12,000
W
50 mA
1, 2, 3
1. Nominal value subject to verification and/or change during release of preliminary specifications.
2. If the Device Identification is not used, it may be left disconnected.
3. Values specified are for 40°C.
Recommended Circuit
Note that V1 must be a different value than V2.
V1
V2
R_external
DevID
ADC
R_DeviceID
GND
KAI−08050
Figure 19. Device Identification Recommended Circuit
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KAI−08050
TIMING
Table 18. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Units
Photodiode Transfer
tpd
1.0
−
−
ms
VCCD Leading Pedestal
t3p
4.0
−
−
ms
VCCD Trailing Pedestal
t3d
4.0
−
−
ms
VCCD Transfer Delay
td
1.0
−
−
ms
VCCD Transfer
tv
2.0
−
−
ms
vVCR
75
100
%
tVR, tVF
5
−
10
%
ths
0.2
−
−
ms
HCCD Transfer
te
25.0
−
−
ns
Shutter Transfer
tsub
1.0
−
−
ms
Shutter Delay
thd
1.0
−
−
ms
Reset Pulse
tr
2.5
−
−
ns
Reset – Video Delay
trv
−
2.2
−
ns
H2SL – Video Delay
thv
−
3.1
−
ns
Line Time
tline
45.5
−
−
ms
87.6
−
−
57.4
−
−
114.8
−
−
Dual HCCD Readout
220.7
−
−
Single HCCD Readout
VCCD Clock Cross−over
VCCD Rise, Fall Times
HCCD Delay
Frame Time
tframe
1. Refer to timing diagrams as shown in Figures 20, 21, 22, 23 and 24.
2. Refer to Figure 24: VCCD Clock Edge Alignment
3. Relative to the pulse width
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23
Notes
2, 3
Dual HCCD Readout
Single HCCD Readout
ms
Quad HCCD Readout
KAI−08050
Timing Diagrams
The timing sequence for the clocked device pins may be
represented as one of seven patterns (P1−P7) as shown in the
table below. The patterns are defined in Figure 20 and
Figure 21. Contact ON Semiconductor Application
Engineering for other readout modes.
Table 19.
Quad Readout
Dual Readout
VOUTa, VOUTb
Dual Readout
VOUTa, VOUTc
Single Readout
VOUTa
V1T
P1T
P1B
P1T
P1B
V2T
P2T
P4B
P2T
P4B
V3T
P3T
P3B
P3T
P3B
V4T
P4T
P2B
P4T
P2B
Device Pin
V1B
P1B
V2B
P2B
V3B
P3B
V4B
P4B
P5
H1Sa
H1Ba
P6
H2Sa2
H2Ba
Ra
P7
P5
H1Sb
P5
H1Bb
H2Sb
P6
2
P6
P6
H2Bb
P5
Rb
P7
P7
1
or Off
3
P7 1 or Off 3
P5
P5 1 or Off 3
P5
P5 1 or Off 3
P6
P6 1 or Off 3
P6
P6 1 or Off 3
Rc
P7
P7 1 or Off 3
P7
P7 1 or Off 3
H1Sd
P5
P5 1 or Off 3
P5
P5 1 or Off 3
P6
P6 1 or Off 3
H1Sc
H1Bc
H2Sc 2
H2Bc
H1Bd
H2Sd 2
P6
H2Bd
Rd
# Lines/Frame (Minimum)
# Pixels/Line (Minimum)
P6 1 or Off 3
P6
P5
P7
P7 1 or Off 3
P7 1 or Off 3
P7 1 or Off 3
1260
2520
1260
2520
1693
3386
1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should
be a multiple of the frequency used on the a and b register.
2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver.
3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the
unused c/d register into the image area.
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24
KAI−08050
Photodiode Transfer Timing
A row of charge is transferred to the HCCD on the falling
edge of V1 as indicated in the P1 pattern below. Using this
timing sequence, the leading dummy row or line is
combined with the first dark row in the HCCD. The “Last
Line” is dependent on readout mode – either 632 or 1264
minimum counts required. It is important to note that, in
Pattern
td
1 2
t3p
3
tpd
4
t3d
P1T
5 6
general, the rising edge of a vertical clock (patterns P1−P4)
should be coincident or slightly leading a falling edge at the
same time interval. This is particularly true at the point
where P1 returns from the high (3rd level) state to the
mid−state when P4 transitions from the low state to the high
state.
td
tv
tv
tv/2
tv/2
P2T
tv/2
tv/2
P3T
P4T
tv
P1B
tv/2
tv
tv/2
P2B
P3B
P4B
ths
P5
Last Line
ths
L1 + Dummy Line
L2
P6
P7
Figure 20. Photodiode Transfer Timing
Line and Pixel Timing
Each row of charge is transferred to the output, as
illustrated below, on the falling edge of H2SL (indicated as
P6 pattern). The number of pixels in a row is dependent on
Pattern
P1T
tline
tv
tv
P1B
ths
P5
P6
readout mode – either 853 or 1706 minimum counts
required.
te/2
te
tr
P7
VOUT
Pixel
1
Pixel
34
Pixel
n
Figure 21. Line and Pixel Timing
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25
KAI−08050
Pixel Timing Detail
P5
P6
P7
VOUT
thv
trv
Figure 22. Pixel Timing Detail
Frame/Electronic Shutter Timing
The resulting photodiode integration time is defined from
the falling edge of SUB to the falling edge of V1 (P1
pattern).
The SUB pin may be optionally clocked to provide
electronic shuttering capability as shown below.
tframe
Pattern
P1T/B
SUB
P6
thd
tint
tsub
thd
Figure 23. Frame/Electronic Shutter Timing
VCCD Clock Edge Alignment
VVCR
90%
tV
10%
tVF
tVR
tV
tVF
tVR
Figure 24. VCCD Clock Edge Alignment
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KAI−08050
Line and Pixel Timing − Vertical Binning by 2
tv
tv
tv
ths
P1T
P2T
P3T
P4T
P1B
P2B
P3B
P4B
ths
P5
P6
P7
VOUT
Pixel
1
Pixel
n
Pixel
34
Figure 25. Line and Pixel Timing − Vertical Binning by 2
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27
KAI−08050
STORAGE AND HANDLING
Table 20. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
TST
−55
+80
°C
1
Humidity
RH
5
90
%
2
1. Long term storage toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
www.onsemi.com
28
KAI−08050
MECHANICAL INFORMATION
Completed Assembly
Figure 26. Completed Assembly
5. Internal traces may be exposed on sides of
package. Do not allow metal to contact sides of
ceramic package.
6. Recommended mounting screws: 1.6 X 0.35 mm
(ISO Standard); 0 – 80 (Unified Fine Thread
Standard)
7. Units: millimeters
Notes:
1. See Ordering Information for marking code.
2. No materials to interfere with clearance through
guide holes.
3. The center of the active image is nominally at the
center of the package.
4. Die rotation < 0.5 degrees
www.onsemi.com
29
KAI−08050
MAR Cover Glass
Figure 27. MAR Cover Glass
Notes:
1. Dust/Scratch count − 12 micron maximum
2. Units: mm
Clear Cover Glass
Figure 28. Clear Cover Glass
Notes:
1. Dust/Scratch count − 10 micron maximum
2. Units: mm
www.onsemi.com
30
KAI−08050
Cover Glass Transmission
100
90
Transmission (%)
80
70
60
50
40
30
20
10
0
200
300
400
500
600
700
800
900
Wavelength (nm)
MAR
Clear
Figure 29. Cover Glass Transmission
ON Semiconductor and the
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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31
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
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KAI−08050/D