NCP339 3 A Ultra-Small Controlled Load Switch with Auto-Discharge Path and Reverse Current Control The NCP339 is a very low Ron MOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, due to a current consumption optimization with PMOS structure, leakage currents are eliminated by isolating connected IC on the battery when not used. Reverse blocking control is automatically engage if OUT pin voltage is higher than IN pin voltage, eliminate leakages current from OUT to IN. Proposed in a wide input voltage range from 1.2 V to 5.5 V, in a small 1 x 1.5 mm WLCSP6, pitch 0.5 mm. http://onsemi.com WLCSP6, 1.00x1.50 CASE 567FH MARKING DIAGRAM XX AYWG G Features • • • • • • • • • 1.2 V − 5.5 V Operating Range 19 m P MOSFET at 4.5 V DC Current up to 3 A Soft Start Control Low Quiescent Current Reverse Blocking Active High EN pin WLCSP6 1 x 1.5 mm This is a Pb−Free Device XX A Y W G (*Note: Microdot may be in either location) PACKAGE PINOUT DIAGRAM Typical Applications • • • • • • = NP or DP = Assembly Location = Year = Work Week = Pb−Free Package Mobile Phones Tablets Digital Cameras GPS Portable Devices Computers 1 2 A OUT IN B OUT IN C GND EN (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2013 November, 2013 − Rev. 2 1 Publication Order Number: NCP339/D NCP339 VCC V+ LS NCP339 C2 1 F ENy OUT OUT IN IN GND A2 B2 EN A1 B1 Platform IC’n 100n C1 DCDC Converter or LDO SMPS ENx 0 LS Platform IC’n+1 Figure 1. Typical Application Circuit Table 1. PIN FUNCTION DESCRIPTION Pin Name Pin Number Type IN A2, B2 POWER Load-switch input voltage; connect a 1 F or greater ceramic capacitor from IN to GND as close as possible to the IC. Description GND C1 POWER Ground connection. EN C2 INPUT OUT A1, B1 OUTPUT Enable input, logic high turns on power switch. Load-switch output; connect a 100 nF ceramic capacitor from OUT to GND as close as possible to the IC is recommended. IN: pin A2, B2 OUT: pin A1, B1 Gate driver and soft start control Control logic Optional EN: C2 EN block 7M GND: C1 Figure 2. Block Diagram http://onsemi.com 2 NCP339 Table 2. MAXIMUM RATINGS Value Unit IN, OUT, EN, Pins: (Note 1) Rating VEN, VIN, VOUT Symbol -0.3 to +7.0 V From IN to OUT Pins: Input/Output (Note 1) VIN, VOUT -7.0 to +7.0 V Human Body Model (HBM) ESD Rating are (Note 1 and 2) ESD HBM 4000 V Machine Model (MM) ESD Rating are (Note 1 and 2) ESD MM 250 V Latch-up protection (Note 3) − Pins IN, OUT, EN LU 100 mA Maximum Junction Temperature TJ -40 to +125 °C Storage Temperature Range TSTG -55 to +150 °C Moisture Sensitivity (Note 4) MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. OPERATING CONDITIONS Symbol 1. 2. 3. 4. Parameter Conditions Min Typ Max Unit 1.2 5.5 V 0 5.5 VIN Operational Power Supply VEN Enable Voltage TA Ambient Temperature Range -40 25 +85 °C TJ Junction Temperature Range -40 25 +125 °C CIN Decoupling input capacitor COUT Decoupling output capacitor RJA Thermal Resistance Junction to Air IOUT Maximum DC current PD Power Dissipation Rating (Note 4) WLCSP package (Note 3) 1 F 100 nF 100 °C/W 3 A TA ≤ 25 °C WLCSP package 1 W TA = 85 °C WLCSP package 0.4 W According to JEDEC standard JESD22-A108. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020. The RJA is dependent of the PCB heat dissipation and thermal via. The maximum power dissipation (PD) is given by the following formula: PD + http://onsemi.com 3 T JMAX*T A R JA NCP339 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN between 1.2 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 5 V (Unless otherwise noted). Parameter Symbol Conditions Min Typ Max Unit POWER SWITCH RDSON Static drain-source on-state resistance Vin = 5.5 V Iout = 200 mA, TA = 25°C Vin = 5.5 V Tj = 125°C Vin = 4.5 V Iout = 200 mA, TA = 25°C 18 30 19 Tj = 125°C Vin = 3.3 V 30 Iout = 200 mA, TA = 25°C 22 Tj = 125°C Vin = 2.5 V 30 Iout = 200 mA, TA = 25°C 27 Tj = 125°C Vin = 1.8 V 40 Iout = 200 mA, TA = 25°C 37 Tj = 125°C Vin = 1.5 V 60 Iout = 200 mA, TA = 25°C 48 Tj = 125°C Rdis Output discharge path VIH High-level input voltage VIL Low-level input voltage Rpd EN pull down resistor EN = low m 110 Discharge path option 70 90 V 1.2 0.8 5.5 7.1 9.5 M REVERSE CURRENT BLOCKING Vrev_thr Reverse threshold Vrev_hyst Reverse threshold hysteresis Trev Reverse comparator response time Vout-Vin Vout-Vin > Vrev_thr 40 mV 60 mV 2.5 s QUIESCENT CURRENT Istd Standby current Vin = 4.2 V EN = low, No load, GND current 0.35 0.6 A Iin_leak Mos leakage current Vin = 4.2 V EN = low, Vout = GND, Vout current 9 200 nA Iq Quiescent current Vin = 4.2 V EN = high, No load, GND current 1.0 1.5 A Iout_leak Output leakage current Vout = 4.2 V Vin = GND 16 200 nA TEN Enable time Vin = 4.2 V (Note 6) RL = 5 , Cout = 100 F 1.7 TR Output rise time TON ON time (TEN + TR) 4.4 TF Output fall time 1.5 TEN Enable time TR Output rise time TON ON time (TEN + TR) TF Output fall time TIMINGS Vin = 4.2 V (Note 6) ms 2.7 RL = 25 , Cout = 1 F 0.5 1.0 2.5 0.4 1.5 2.3 0.9 2.5 4.8 0.06 0.1 5. Guaranteed by design and characterization. 6. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground. http://onsemi.com 4 ms NCP339 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN between 1.2 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Vin = 4.2 V (Note 6) Min RL = 150 , Cout = 100 F Typ TEN Enable time 1.7 TR Output rise time TON ON time (TEN + TR) 3.2 TDIS Disable time 1.8 TF Fall time 4 TOFF Output fall time (TF + TDIS) 42 1.5 5. Guaranteed by design and characterization. 6. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground. Vin EN Vout TEN TR TDIS TON TOFF Figure 3. Timings http://onsemi.com 5 TF Max Unit ms NCP339 TYPICAL CHARACTERISTICS Figure 4. Standby Current (mA) versus Vin (V) Figure 5. Quiescent Current (mA) versus Vin (V) http://onsemi.com 6 NCP339 Figure 6. Reverse Current (nA) versus Vin (V) Figure 7. RDSON (mW) versus Temperature (ILOAD = 100 mA) http://onsemi.com 7 NCP339 Figure 8. RDSON (mW) versus Vin (V) FUNCTIONAL DESCRIPTION Overview Table 5. CONTROL LOGIC The NCP339 is a high side P channel MOSFET power distribution switch designed to isolate ICs connected on the battery in order to save energy. The part can be turned on, with a wide range of battery from 1.2 V to 5.5 V. Reverse blocking from output to input control is embedded in the IC to eliminate leakage current if Vout voltage exceed front end power supply. VIN VOUT EN Present Mos OFF Low Present Mos ON High Mos OFF VOUT > VIN x Auto Discharge (Optional) Enable Input NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. The auto-discharge is activated when EN pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as EN pin is set at low level and Vin > 1.2 V. In order to limit the current across the internal discharge Nmosfet, the typical value is set at 70 . Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing P MOS switch off. The IN/OUT path is activated with a minimum of Vin of 1.2 V and EN forced to high level. Blocking Control The reverse blocking feature allows to avoid reverse current, through the PMOS fet if a voltage is applied on Vout pin, and Vrev_thr above the Vin pin. This function is available, whatever the EN logic pin state (High or low). To retrieve normal state, Vin-Vout must be higher to hysteresis of the reverse blocking comparator (Vrev_hyst). The reverse blocking comparator response time is set to Trev. Cin and Cout Capacitors Cin 1 F and Cout 100 nF , at least, capacitors must be placed as close as possible the part to for stability improvement. For inrush effects at start up, it’s recommended to respect Cin > Cout size. http://onsemi.com 8 NCP339 APPLICATION INFORMATION Power Dissipation Example of application definition. TJ − TA = RJA × PD = RJA × RDSON × I2 Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: • PD = RDS(on) × (IOUT)2 PD = Power dissipation (W) = Power MOSFET on resistance () RDS(on) IOUT = Output current (A) TJ: junction temperature. TA: ambient temperature. R = Thermal resistance between IC and air, through PCB. RDSON: intrinsic resistance of the IC Mosfet. I: load DC current. Taking into account of R obtain with: • 1 oz, 2 layers: 100°C/W. At 3 A, 25°C ambient temperature, RDSON 20 m @ Vin 5 V, the junction temperature will be: TJ = TA + R × PD = 25 + (0.02 × 32) × 100 = 43°C • TJ = PD × RJA + TA TJ RJA TA = Junction temperature (°C) = Package thermal resistance (°C/W) = Ambient temperature (°C) Taking into account of R obtain with: • 2 oz, 4 layers: 60°C/W. PCB Recommendations At 3 A, 65°C ambient temperature, RDSON 24 m @ Vin 5 V, the junction temperature will be: TJ = TA + R × PD = 65 + (0.024 × 32) × 60 = 78°C The NCP339 integrates an up to 3 A rated PMOS FET, and the PCB design rules must be respected to properly evacuate the heat out of the silicon. By increasing PCB area, especially around IN and OUT pins, the RJA of the package can be decreased, allowing higher power dissipation. Routing example: 2 oz, 4 layers with vias across 2 internal inners. Figure 9. ORDERING INFORMATION Marking Option Package Shipping† NCP339AFCT2G NP Without Auto−discharge WLCSP6, 1 x 1.5 mm (Pb−Free) 3000 / Tape & Reel NCP339BFCT2G DP With Auto−discharge WLCSP6, 1 x 1.5 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NCP339 PACKAGE DIMENSIONS WLCSP6, 1.00x1.50 CASE 567FH ISSUE O D PIN A1 REFERENCE 2X A ÈÈ ÈÈ B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. E DIM A A1 A2 b D E e 0.05 C 2X 0.05 C TOP VIEW A2 MILLIMETERS MIN MAX 0.63 0.54 0.22 0.28 0.33 REF 0.29 0.34 1.00 BSC 1.50 BSC 0.50 BSC 0.05 C A RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 A1 SIDE VIEW C SEATING PLANE A1 PACKAGE OUTLINE eD/2 6X eD b 0.05 C A B eE C 0.50 PITCH 0.03 C B A 6X 0.50 PITCH 0.25 DIMENSIONS: MILLIMETERS 1 2 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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