NB3N508S 3.3V, 216 MHz PureEdge VCXO Clock Generator with M−LVDS Output Description The NB3N508S is a high precision, low phase noise Voltage Controlled Crystal Oscillator (VCXO) and phase lock loop (PLL) that generates 216 MHz M−LVDS output from a 27 MHz crystal. The ±100 ppm output pullable range is obtained using the VIN pin of the VCXO with usable range from 0 V to 3.3 V. The VCXO input pin VIN is a high−impedance input that can be driven directly from a pulse width modulated RC integrator circuit. The NB3N508S is designed primarily for data and clock recovery applications within end products such as ADSL modems, set−top box receivers, and telecom systems. This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP−16 pin package. http://onsemi.com MARKING DIAGRAM 16 16 NB3N 508S ALYWG G 1 TSSOP−16 DT SUFFIX CASE 948F 1 Features • • • • • • • • • • PureEdge Clock Family Provides Accuracy and Precision Performs Precision Clock Multiplication from 27 MHz Crystal Uses 27 MHz Fundamental Mode Crystal External Loop Filter is Not Required 216 MHz M−LVDS Output VCXO with Pull Range $100 ppm 0 V to 3.3 V VCXO Tuning Voltage Range Capabilities Phase Noise: Offset Noise Power 100 Hz −80 dBc 1 kHz −88 dBc 10 kHz −105 dBc 100 kHz −106 dBc 1 MHz −120 dBc 10 MHz −145 dBc Operating Range 3.3 V $5% These are Pb−Free Devices* © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 0 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Publication Order Number: NB3N508S/D NB3N508S VDD X1 27 MHz Crystal CLK VCXO Phase Detector X2 Charge Pump VCO M−LVDS Output CLK VIN BN GND Figure 1. NB3N508S Simplified Logic Diagram *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 2 NB3N508S X1 1 16 X2 VDD 2 15 NC VDD 3 14 CLK VDD 4 13 CLK VIN 5 12 GND GND 6 11 NC GND 7 10 VDD GND 8 9 NC NB3N508S Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 X1 Crystal Input Crystal input(IN). Connect to a 27 MHz crystal. 2, 3, 4, 10 VDD Power Supply Positive power supply voltage. 5 VIN Input 6, 7, 8, 12 GND Power Supply 9, 11, 15 NC − 13 CLK M−LVDS Output Inverted clock output. Typically loaded with 50 W receiver termination resistor across diff. pair. 14 CLK M−LVDS Output Noninverted clock output. Typically loaded with 50 W receiver termination resistor across diff. pair. 16 X2 Crystal Input Analog voltage input pin that controls output oscillation frequencies. VIN pin range is from 0 V to 3.3 V. VIN voltage should not exceed VDD. Ground 0 V. These pins provide GND return path for the devices. No Connect. Crystal input(OUT). Connect to a 27 MHz crystal. Recommended Crystal Parameters Crystal Fundamental AT−Cut Frequency Load Capacitance Shunt Capacitance, C0 Max Equivalent Series Resistance Max Initial Accuracy at 25°C Temperature Stability Aging C0/C1 Ration 27 MHz 14 pF 7 pF 35 W ±20 ppm ±30 ppm ±20 ppm 250 Max http://onsemi.com 3 NB3N508S Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model > 4 kV > 400 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP−16 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 6000 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 VDD Positive Power Supply GND = 0 V VI Input Voltage (VIN) GND = 0 V IOUT M−LVDS Output Current Continuous Surge TA Operating Temperature Range TSTG Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) qJA Thermal Resistance (Junction−to−Case) TSOL Wave Solder Condition 2 GND v VI v VDD Rating Unit 4.6 V VDD V 25 50 mA mA 0 to +70 °C −65 to +150 °C 0 lfpm 500 lfpm TSSOP–16 TSSOP–16 138 108 °C/W °C/W (Note 2) TSSOP−16 33 to 36 °C/W 265 °C Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 2S2P (2 Signal, 2 Power). Table 4. DC CHARACTERISTICS (VDD = 3.135 V to 3.465 V, GND = 0 V, TA = 0°C to +70°C) Symbol Characteristic Min Typ Max Unit 52 62 mA 3.3 V IDD Power Supply Current (outputs loaded with RL = 50 W) 42 VIA VCXO Control Voltage, VIN 0 VOD Differential Output Voltage (Note 3) 480 650 mV DVOD Change in Magnitude of VOD for Complementary Output States (Notes 3, 6) −50 50 mV VOS Offset Voltage (See Figure 4) 300 2100 mV DVOS Change in Magnitude of VOS for Complementary Output States (Note 6) −50 50 mV VOH Output HIGH Voltage (Note 4) 2425 mV VOL Output LOW Voltage (Note 5) ISC Output Short Circuit Current 565 1300 −25 CLK or CLK to GND 700 mV 43 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. M−LVDS outputs require 50 W receiver termination resistor between differential. pair. See Figure 3 4. VOHmax = VOSmax + ½ VODmax. 5. VOLmax = VOSmin − ½ VODmax. 6. Parameters guaranteed by design but not tested in production. http://onsemi.com 4 NB3N508S Table 5. AC CHARACTERISTICS (VDD = 3.135 V to 3.465 V, GND = 0 V, TA = 0°C to +70°C, Note 7) Characteristic Symbol Min Typ Max Unit fCLKIN Crystal Input Frequency 27 MHz fCLKOUT Output Clock Frequency 216 MHz FNOISE Phase−Noise Performance fCLKOUT = 216 MHz @ 100 Hz Offset from Carrier @ 1 kHz Offset from Carrier @ 10 kHz Offset from Carrier @ 100 kHz Offset from Carrier @ 1 MHz Offset from Carrier @ 10 MHz Offset from Carrier −80 −88 −105 −106 −120 −145 Spurious Noise Components −60 FP Crystal Pullability 0 V v VIN v 3.3 V tDUTY_CYCLE Output Clock Duty Cycle (Measured at Crosspoint) tR tF dBc/Hz dBc/Hz ppm "100 45 50 55 % Output Rise Time (CLK/CLK) (Note 8) 380 500 ps Output Fall Time (CLK/CLK) (Note 8) 380 500 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. CLK/CLK loaded with 50 W receiver termination resistor between diff. pair. 8. Measured differentially (CLK − CLK) at 10% to 90%; RL = 50 W. NOISE POWER (dBc) Phase Noise 10.00dB/Ref −20.00dBc/Hz OFFSET FREQUENCY (Hz) Figure 3. Typical Phase Noise Plot (VDD = 3.3 V, VIN = 0 V; Room Temperature) http://onsemi.com 5 NB3N508S 216.06 150 216.04 Maximum 100 FREQUENCY (MHz) FREQUENCY ERROR (ppm) 200 0 −50 Minimum −100 25° 216 215.98 −150 70° 215.96 −200 −250 0° 216.02 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 215.94 0 0.5 1.0 1.5 2.0 2.5 3.0 3.15 3.3 3.45 VIN, CONTROL VOLTAGE (V) VIN, CONTROL VOLTAGE (V) Figure 4. VCXO Pulling Range Figure 5. Output Clock Frequency vs. VIN and Temperature Figure 6. Typical Crystal Startup Time with VIN = 0 V at Ambient Temperature (1.99 ms) M−LVDS Driver Device CLK Figure 7. Typical Crystal Startup Time with VIN = 3.3 V at Ambient Temperature (694 ms) Zo = 50 W D 50 W CLK Zo = 50 W M−LVDS Receiver Device D Figure 8. Typical Termination for Output Driver and Device Evaluation CLK VOH VOS VOD VOL CLK Figure 9. H−LVDS Output http://onsemi.com 6 NB3N508S ORDERING INFORMATION Package Shipping † NB3N508SDTG TSSOP−16 (Pb−Free) 96 Units / Rail NB3N508SDTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB3N508S PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D G H DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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