NB6N14S 3.3 V 1:4 AnyLevelt Differential Input to LVDS Fanout Buffer/Translator The NB6N14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevelt differential input signals: LVPECL, CML or LVDS. These signals will be translated to LVDS and four identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB6N14S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6N14S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels. The NB6N14S is offered in a small 3 mm x 3 mm 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6N14S is a member of the ECLinPS MAXt family of high performance products. Features • • • • • • • • • • Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum RMS Clock Jitter Typically 10 ps Data Dependent Jitter 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times VREF_AC Reference Output TIA/EIA − 644 Compliant Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and SG Devices These are Pb−Free Devices http://onsemi.com MARKING DIAGRAM* 16 1 NB6N 14S ALYW G G 1 QFN−16 MN SUFFIX CASE 485G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 Q0 Q1 Q1 IN W VT 50 W /IN 50 Q2 Q2 VOLTAGE (130 mV/div) EN (LVTTL/CMOS) D Q Q3 VREF_AC Device DDJ = 10 ps Q3 Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. TIME (58 ps/div) Figure 2. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps) © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 3 1 Publication Order Number: NB6N14S/D NB6N14S Q0 Q0 VCC GND 16 15 14 Exposed Pad (EP) 13 Table 1. TRUTH TABLE Q1 1 12 IN Q1 2 11 VT Q2 3 10 VREF_AC Q2 4 9 NB6N14S IN IN IN EN Q Q 0 1 1 0 1 1 0 1 1 0 x x 0 0 (Note 1) 1 (Note 1) 1. On next transition of the input signal (IN). 5 6 7 Q3 Q3 VCC 8 EN Figure 3. NB6N14S Pinout, 16−pin QFN (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 Q1 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 3 Q2 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 4 Q2 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 Q3 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 6 Q3 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 7 VCC − 8 EN LVTTL / LVCMOS Input 9 IN LVPECL, CML, LVDS 10 VREF_AC LVPECL Output The VREF_AC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. For the capacitor−coupled IN and/or INb inputs, VREF_AC should be connected to the VT pin and bypassed to ground with a 0.01 mF capacitor. Internal 100 W Center−tapped Termination Pin for IN and IN Positive Supply Voltage. Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb outputs will go HIGH on the next negative transition of IN input. The internal DFF register is clocked on the falling edge of IN input; see Figure 19. The EN pin has an internal pullup resistor and defaults HIGH when left open. Inverted Differential Input 11 VT LVPECL Output 12 IN LVPECL, CML, LVDS 13 GND − Negative Supply Voltage. 14 VCC − Positive Supply Voltage. 15 Q0 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 16 Q0 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. − EP − Non−inverted Differential Input. (Note 2) The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to self−oscillation. http://onsemi.com 2 NB6N14S Table 3. ATTRIBUTES Characteristics Value Moisture Sensitivity (Note 3) Flammability Rating ESD Protection Level 1 Oxygen Index: 28 to 34 Human Body Model Machine Model UL 94 V−0 @ 0.125 in > 2 kV > 200 V Transistor Count 225 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 3.8 V 3.8 V 35 70 mA mA VCC Positive Power Supply GND = 0 V VIN Positive Input GND = 0 V IIN Input Current Through RT (50 W Resistor) Static Surge IOSC Output Short Circuit Current Line−to−Line (Q to Q) Line−to−End (Q or Q to GND) TIA/EIA − 644 Compliant Q or Q to GND Q to Q IREF_AC VREF_AC Sink/Source Current TA Operating Temperature Range Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 4) 0 lfpm 500 lfpm QFN−16 QFN−16 41.6 35.2 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 4) QFN−16 4.0 °C/W Tsol Wave Solder 265 °C VIN ≤ VCC Continuous Continuous QFN−16 Pb−Free 12 24 mA "0.5 mA −40 to +85 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6N14S Table 5. DC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C Characteristic Symbol ICC Min Power Supply Current (Note 9) Typ Max Unit 65 100 mA DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 10, 11, 15, and 17) Vth Input Threshold Reference Voltage Range (Note 8) GND +100 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 mV VREF_AC Reference Output Voltage (Note 11) VCC − 1.300 V VCC − 1.600 VCC − 1.425 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6, 7, 8, 9, 16, and 18) VIHD Differential Input HIGH Voltage 100 VCC mV VILD Differential Input LOW Voltage GND VCC − 100 mV VCMR Input Common Mode Range (Differential Configuration) GND + 50 VCC − 50 mV VID Differential Input Voltage (VIHD − VILD) 100 VCC mV RTIN Internal Input Termination Resistor 40 60 W 450 mV 25 mV 1375 mV 1 25 mV 1425 1600 mV 50 LVDS OUTPUTS (Note 5) VOD Differential Output Voltage 250 DVOD Change in Magnitude of VOD for Complementary Output States (Note 10) VOS Offset Voltage (Figure 14) DVOS Change in Magnitude of VOS for Complementary Output States (Note 10) VOH Output HIGH Voltage (Note 6) VOL Output LOW Voltage (Note 7) 0 1 1125 0 900 1075 mV LVTTL/LVCMOS INPUTS VIH Input HIGH Voltage (Note 7, 8) 2.0 VCC V VIL Input LOW Voltage (Note 7, 8) GND 0.8 V IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 13. 6. VOHmax = VOSmax + ½ VODmax. 7. VOLmax = VOSmin − ½ VODmax. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 10. Parameter guaranteed by design verification not tested in production. 11. VREF_AC used to rebias capacitor−coupled inputs only (see Figures 10 and 11). http://onsemi.com 4 NB6N14S Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 12) −40°C finMax Maximum Input Clock Frequency 2.0 VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.0 GHz (Figure 4) fin= 1.5 GHz fin= 2.0 GHz 220 200 170 350 300 270 220 200 170 350 300 270 220 200 170 350 300 270 mV fDATA Maximum Operating Data Rate 1.5 2.5 1.5 2.5 1.5 2.5 Gb/s tPLH, tPHL Differential Input to Differential Output Propagation Delay 300 450 300 450 300 450 ts th Setup Time Hold Time 300 500 60 70 300 500 60 70 300 500 60 70 tSKEW Within Device Skew (Note 17) Device−to−Device Skew (Note 16) 5 30 tJITTER RMS Random Clock Jitter (Note 14) 0.5 0.5 10 10 10 Deterministic Jitter (Note 15) fin = 1.0 GHz fin = 1.5 GHz fDATA = 622 Mb/s fDATA = 1.5 Gb/s fDATA = 2.488 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 13) tr tf Output Rise/Fall Times @ 250 MHz (20% − 80%) 60 Min Typ Max 2.0 100 Q, Q Max 85°C Characteristic Symbol Typ 25°C Min 120 600 20 200 Min 600 20 200 190 60 120 600 ps 20 200 ps 0.5 0.5 10 10 10 VCC− GND 100 190 60 Unit GHz 5 30 0.5 0.5 10 10 10 100 Max 2.0 5 30 VCC− GND Typ 120 ps VCC− GND mV 190 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W. Input edge rates 150 ps (20%−80%). See Figure 13. 13. Input voltage swing is a single−ended measurement operating in differential mode. 14. RMS jitter with 50% Duty Cycle clock signal at 750 MHz. 15. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5. 16. Skew is measured between outputs under identical transition @ 250 MHz. 17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition. OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 −40°C 250 85°C 200 25°C 150 100 50 0 0 0.5 1 1.5 2 2.5 INPUT CLOCK FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V) http://onsemi.com 5 3 VOLTAGE (63.23 mV/div) NB6N14S Device DDJ = 10 ps TIME (58 ps/div) Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask (VINPP = 100 mV; Input Signal DDJ = 14 ps) http://onsemi.com 6 NB6N14S VCC VCC Zo = 50 W LVPECL Driver VT = VCC − 2.0 V VCC NB6N14S CLK Zo = 50 W 50 W LVDS Driver VEE 50 W VEE Figure 7. LVDS Interface VCC VCC NB6N14S CLK VCC Zo = 50 W 50 W CML Driver 50 W VEE 50 W VEE Figure 9. Standard 50 W Load HSTL Interface VCC VCC NB6N14S CLK VCC Zo = 50 W 50 W Differential Driver VEE NB6N14S CLK 50 W Single−Ended Driver VT = VREF_AC 50 W Zo = 50 W CLK VEE Figure 8. Standard 50 W Load CML Interface Zo = 50 W VT =VEE Zo = 50 W CLK VEE VCC NB6N14S CLK 50 W HSTL Driver VT = VCC Zo = 50 W CLK VEE Figure 6. LVPECL Interface Zo = 50 W VT = OPEN Zo = 50 W CLK VEE VCC NB6N14S CLK 50 W 50 W Zo = 50 W VCC CLK VT = VREF_AC 50 W CLK VEE VEE Figure 10. Capacitor−Coupled Differential Interface (VT Connected to VREF_AC) VEE Figure 11. Capacitor−Coupled Single−Ended Interface (VT Connected to VREF_AC) http://onsemi.com 7 NB6N14S D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 12. AC Reference Measurement Q LVDS Driver Device Zo = 50 W D 100 W Q Zo = 50 W LVDS Receiver Device D Figure 13. Typical LVDS Termination for Output Driver and Device Evaluation QN VOH VOS VOD VOL QN Figure 14. LVDS Output IN VIH Vth VIL Vth IN IN IN Figure 15. Differential Input Driven Single−Ended Figure 16. Differential Inputs Driven Differentially VCC VCC VIHmax Vthmax IN VIL VILmax VCMR Vth Vthmin GND VIH(MAX) VIH VINPP = VIHD − VILD VIL VIHmin IN VIH VILmin GND Figure 17. Vth Diagram VIL(MIN) Figure 18. VCMR Diagram http://onsemi.com 8 NB6N14S EN VCC/2 /IN IN VCC/2 tS tH VINPP tpd /Q VOUTPP Q Figure 19. EN Timing Diagram ORDERING INFORMATION Package Shipping † NB6N14SMNG QFN−16, 3 X 3 mm (Pb−Free) 123 Units / Rail NB6N14SMNR2G QFN−16, 3 X 3 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB6N14S PACKAGE DIMENSIONS D PIN 1 LOCATION A B ÇÇ ÇÇ 0.15 C 16 PIN QFN CASE 485G−01 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 SOLDERING FOOTPRINT* C D2 16X L 5 NOTE 5 e 4 16X 3.25 0.128 0.30 0.012 EXPOSED PAD 9 E2 K 12 1 16 16X 1.50 0.059 3.25 0.128 e 13 b 0.10 C A B 0.05 C 0.575 0.022 EXPOSED PAD 8 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 BOTTOM VIEW 0.50 0.02 NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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