NB6L11S 2.5 V 1:2 AnyLevelt Input to LVDS Fanout Buffer / Translator The NB6L11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevelt input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6L11S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB6L11S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6L11S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels. The NB6L11S is the 2.5 V version of the NB6N11S and is offered in a small 3 mm X 3 mm 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com. http://onsemi.com MARKING DIAGRAM* 16 1 1 QFN−16 MN SUFFIX CASE 485G A L Y W G Features • • • • • • • • Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times Single Power Supply; VCC = 2.5 V " 5% These are Pb−Free Devices NB6L 11S ALYW G G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 VTD Q0 D D VOLTAGE (130 mV/div) VTD Q1 Q1 Figure 1. Logic Diagram Device DDJ = 10 ps ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. TIME (58 ps/div) Figure 2. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps) © Semiconductor Components Industries, LLC, 2006 September, 2006 − Rev. 2 1 Publication Order Number: NB6L11S/D NB6L11S Exposed Pad (EP) VCC VCC VCC VCC 16 Q0 1 Q0 2 15 14 13 12 VTD 11 D NB6L11S Q1 3 10 D Q1 4 9 5 6 7 VCC NC VEE VTD 8 VEE Figure 3. NB6L11S Pinout, 16−pin QFN (Top View) Table 1. PIN DESCRIPTION Pin Name I/O 1 Q0 LVDS Output Non−inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q0 LVDS Output Inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. 3 Q1 LVDS Output Non−inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. 4 Q1 LVDS Output Inverted D output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 VCC − 6 NC No Connect. 7 VEE Negative Supply Voltage. 8 VEE 9 VTD − 10 D LVPECL, CML, LVDS, LVCMOS, LVTTL Inverted Differential Clock/Data Input (Note 1). 11 D LVPECL, CML, LVDS, LVCMOS, LVTTL Non−inverted Differential Clock/Data Input (Note 1). 12 VTD − Internal 50 W termination pin for D. 13 VCC − Positive Supply Voltage. 14 VCC − Positive Supply Voltage. 15 VCC − Positive Supply Voltage. 16 VCC − Positive Supply Voltage. EP Description Positive Supply Voltage. Negative Supply Voltage. Internal 50 W termination pin for D. Exposed pad. The exposed pad (EP) on the package bottom must be attached to a heat−sinking conduit. The exposed pad may only be electrically connected to VEE. 1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation. http://onsemi.com 2 NB6L11S Table 2. ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 2) > 2 kV > 200 V > 1 kV Pb−Free Pkg QFN−16 Flammability Rating Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 225 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Power Supply GND = 0 V VIN Positive Input GND = 0 V IIN Input Current Through RT (50 W Resistor) Static Surge IOSC Output Short Circuit Current Line−to−Line (Q to Q) Line−to−End (Q or Q to GND) Q or Q to GND Q to Q TA Operating Temperature Range QFN−16 Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 3) Tsol Wave Solder Condition 2 VIN ≤ VCC Rating Unit 3.8 V 3.8 V 35 70 mA mA mA Pb−Free Continuous Continuous 12 24 −40 to +85 °C −65 to +150 °C QFN−16 QFN−16 41.6 35.2 °C/W °C/W QFN−16 4.0 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L11S Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C Symbol ICC Characteristic Min Power Supply Current (Note 8) Typ Max Unit 30 45 mA DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 11, 12, 16, and 18) Vth Input Threshold Reference Voltage Range (Note 7) GND +100 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19) VIHD Differential Input HIGH Voltage 100 VCC mV VILD Differential Input LOW Voltage GND VCC − 100 mV VCMR Input Common Mode Range (Differential Configuration) GND + 50 VCC − 50 mV VID Differential Input Voltage (VIHD − VILD) 100 VCC mV RTIN Internal Input Termination Resistor 40 60 W 450 mV 25 mV 1375 mV 1 25 mV 1425 1600 mV 50 LVDS OUTPUTS (Note 4) VOD Differential Output Voltage 250 DVOD Change in Magnitude of VOD for Complementary Output States (Note 9) VOS Offset Voltage (Figure 15) DVOS Change in Magnitude of VOS for Complementary Output States (Note 9) VOH Output HIGH Voltage (Note 5) VOL Output LOW Voltage (Note 6) 0 1 1125 0 900 1075 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14. 5. VOHmax = VOSmax + ½ VODmax. 6. VOLmax = VOSmin − ½ VODmax. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 9. Parameter guaranteed by design verification not tested in production. http://onsemi.com 4 NB6L11S Table 5. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V; (Note 10) −40°C Symbol Characteristic Min VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.0 GHz (Figure 4) fin= 1.5 GHz fin= 2.0 GHz 220 200 170 350 300 270 fDATA Maximum Operating Data Rate 1.5 2.5 tPLH, tPHL Differential Input to Differential Output Propagation Delay 250 tSKEW Duty Cycle Skew (Note 11) Within Device Skew (Note 16) Device−to−Device Skew (Note 15) 8 5 30 tJITTER RMS Random Clock Jitter (Note 13) 0.5 0.5 6 7 10 Deterministic Jitter (Note 14) fin = 1.0 GHz fin = 1.5 GHz fDATA = 622 Mb/s fDATA = 1.5 Gb/s fDATA = 2.488 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 12) tr tf Output Rise/Fall Times @ 250 MHz (20% − 80%) Typ 450 100 Q, Q 70 25°C Max 120 Min Typ 220 200 170 350 300 270 1.5 2.5 250 45 25 100 85°C Max 450 8 5 30 Min Typ 220 200 170 350 300 270 1.5 2.5 250 45 25 100 8 5 30 0.5 0.5 6 7 10 VCC− GND 100 170 70 120 Max mV Gb/s 450 ps 45 25 100 ps 0.5 0.5 6 7 10 VCC− GND 100 170 70 120 Unit ps VCC− GND mV 170 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across “D” and “D” of the receiver. Input edge rates 150 ps (20%−80%). 11. See Figure 13 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz. 12. Input voltage swing is a single−ended measurement operating in differential mode. 13. RMS jitter with 50% Duty Cycle input clock signal. 14. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5. 15. Skew is measured between outputs under identical transition @ 250 MHz. 16. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition. OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 −40°C 250 85°C 200 25°C 150 100 50 0 0 0.5 1 1.5 2 2.5 INPUT CLOCK FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V) http://onsemi.com 5 3 VOLTAGE (63.23 mV/div) NB6L11S Device DDJ = 10 ps TIME (58 ps/div) Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask (VINPP = 100 mV; Input Signal DDJ = 14 ps) RC RC 1.25 kW 1.25 kW Dx 50 W 1.25 kW 1.25 kW I VTDx VTDx 50 W Dx Figure 6. Input Structure http://onsemi.com 6 NB6L11S VCC = 3.3 V or 2.5 V VCC = 2.5 V NB6L11S D Zo = 50 W LVPECL Driver VCC = 3.3 V or 2.5 V VCC = 2.5 V 50 W* VTD VTD 50 W* VTD LVDS Driver 50 W* Zo = 50 W NB6L11S D Zo = 50 W VTD 50 W* Zo = 50 W D D VTD = VTD VTD = VTD = VCC − 2.0 V GND GND GND Figure 7. LVPECL Interface VCC = 2.5 V CML Driver Figure 8. LVDS Interface VCC = 3.3 V or 2.5 V VCC = 2.5 V VCC = 2.5 V NB6L11S D Zo = 50 W VCC VTD Zo = 50 W VTD 50 W* VTD HSTL Driver 50 W* VTD Zo = 50 W D VTD = VTD = VCC GND GND GND Figure 9. Standard 50 W Load CML Interface VCC = 2.5 V D VTD = VTD = GND or VDD/2 Depending on Driver. VCC = 2.5 V NB6L11S D GND VCC = 2.5 V Zo = 50 W 50 W* VTD 50 W* Figure 10. HSTL Interface VCC = 2.5 V Zo = 50 W VTD LVTTL Driver VTD VTD 50 W* D NB6L11S D 50 W* 50 W* D 2.5 kW* GND NB6L11S D 50 W* Zo = 50 W LVCMOS Driver GND 1.5 kW* GND GND GND GND VTD = OPEN D = GND VTD = VTD = OPEN D = GND Figure 11. LVCMOS Interface Figure 12. LVTTL Interface *RTIN, Internal Input Termination Resistor. http://onsemi.com 7 GND NB6L11S D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 13. AC Reference Measurement Q LVDS Driver Device Zo = 50 W D 100 W Q Zo = 50 W LVDS Receiver Device D Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation QN VOH VOS VOD VOL QN Figure 15. LVDS Output D D VIH Vth VIL D D Vth Figure 16. Differential Input Driven Single−Ended Figure 17. Differential Inputs Driven Differentially VCC VCC VIHmax Vthmax D VIL VILmax VCMR Vth VIH VINPP = VIHD − VILD VIL VIHmin Vthmin GND VIH(MAX) D VIH VILmin GND Figure 18. Vth Diagram VIL(MIN) Figure 19. VCMR Diagram http://onsemi.com 8 NB6L11S ORDERING INFORMATION Package Shipping † NB6L11SMNG QFN−16, 3 X 3 mm (Pb−Free) 123 Units / Rail NB6L11SMNR2G QFN−16, 3 X 3 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB6L11S PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C D PIN 1 LOCATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B ÇÇ ÇÇ E DIM A A1 A3 b D D2 E E2 e K L 0.15 C TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 SOLDERING FOOTPRINT* C D2 16X 0.575 0.022 e L 5 NOTE 5 EXPOSED PAD 8 4 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 3.25 0.128 0.30 0.012 EXPOSED PAD 9 E2 16X K 12 1 16 16X 13 b 0.10 C A B 0.05 C 1.50 0.059 3.25 0.128 e BOTTOM VIEW 0.50 0.02 NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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