NCP3235 D

NCP3235
High Current Synchronous
Buck Converter
The NCP3235 is a high current, high efficiency voltage mode
synchronous buck converter which operates from 4.5 V to 23 V input
and generates output voltages down to 0.6 V at up to 15 A continuous
current. It has two operation modes: FCCM and automatic
CCM/DCM. In automatic CCM/DCM mode, the controller can switch
smoothly between CCM and DCM, where converter runs at reduced
switching frequency to achieve much higher efficiency at light load.
The NCP3235 is available in 6 mm x 6 mm QFN−40 pin package.
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MARKING
DIAGRAM
1
Features
Wide Input Voltage Range from 4.5 V to 23 V
0.6 V Internal Reference Voltage
Switching Frequency Option: 550 kHz, 1.1 MHz
External Programmable Soft−Start
Lossless Low−side FET Current Sensing
Output Over−voltage Protection and Under−voltage Protection
Selective Hiccup/Latch Off Operation for All Faults
Pre−bias Start−up
Adjustable Output Voltage
Power Good Output
Internal Over−temperature Protection
Adjustable Input UVLO
This is a Pb−Free Device
PIN CONNECTIONS
VIN
PG
MODE
AGND
ISET
COMP
FB
SS
9
8
7
6
5
4
3
2
1
VIN
11
VIN
12
VIN
VIN
13
EP42
VIN
14
37
AGND
VSWH
15
36
BST
PGND
16
35
VSW
PGND
17
34
VSWH
PGND
18
33
VSWH
PGND
19
32
VSWH
PGND
20
31
VSWH
40
EN
GND
39
VCC
EP41
38
VB
VSWH
29
30
28
PGND
VSWH
27
PGND
VSWH
26
24
PGND
PGND
23
PGND
25
22
PGND
PGND
21
EP43
PGND
Industry PC Equipment
ASIC, FPGA, DSP and CPU Core and I/O Supplies
Server and Storage System
Telecom and Network Equipment
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
10
•
•
•
•
A
WL
YY
WW
G
VIN
Typical Application
NCP3235
AWLYYWWG
QFN40 6x6, 0.5P
CASE 485CM
VIN
•
•
•
•
•
•
•
•
•
•
•
•
•
1 40
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP3235MNTXG
QFN−40
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 0
1
Publication Order Number:
NCP3235/D
NCP3235
VCC
VB
VB
VCC
LDO
VB
BST
VB
OSC
COMP
VIN
VB
Control Logic
Ramp Generator
PWM Logic
VREF
E/A
FB
SS
−and−
VSWH
UVLO
OVP, UVP
Power Good
OCP, TSD
Protection
Soft Start
VCC
VSW
VB
VB
2 mA
EN
Enable
Logic
PGND
1.2V
POR
PG
Mode
Selection
AGND
MODE
ISET
Figure 1. NCP3235 Block Diagram
Table 1. PIN DESCRIPTION
Pin No.
Symbol
Description
1
SS
A capacitor from this pin to GND allows the user to adjust the soft−start ramp time.
2
FB
Output voltage feedback.
3
COMP
4
ISET
5, 37
AGND
Analog ground.
6
MODE
Mode selection for FCCM mode and automatic CCM/DCM mode, switching frequency and hiccup/latch protection mode. See table I in the latter page.
Output of the error amplifier.
A resistor from this pin to ground sets the over−current protection (OCP) threshold.
7
PG
Power good indicator of the output voltage. Open−drain output. Connect PG to VDD with an external resistor.
8−14,
EP42
VIN
The VIN pin is connected to the internal power NMOS switch. The VIN pin has high di/dt edges and must be
decoupled to ground close to the pin of the device.
15, 29−34,
EP43
VSWH
The VSWH pin is the connection of the drain and source of the internal NMOS switches. At switch off, the
inductor will drive this pin below ground as the body diode and the NMOS conducts with a high dv/dt.
16−28
PGND
Ground reference and high−current return path for the bottom gate driver and low− side NMOS.
35
VSW
IC connection to the switch node between the top MOSFET and bottom MOSFET. Return path of the high−
side gate driver.
36
BST
Top gate driver input supply, a bootstrap capacitor connection between the switch node and this pin.
38
VB
39
VCC
40
EN
EP41
GND
The internal LDO output and supply for the NCP3235. Connect a minimum of 4.7uF ceramic capacitor from
this pin to ground.
Input Supply for IC. This pin must be connected to VIN.
Logic control for enabling the switcher. An internal pull−up enables the device automatically. The EN pin can
also be driven high to turn on the device, or low to turn off the device. A comparator and precision reference
allow the user to implement this pin as an adjustable UVLO circuit.
Exposed Pad. Connect GND to a large copper plane at ground potential to improve thermal dissipation.
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2
NCP3235
VIN ≥ 4.5 V
BST
VIN
VCC
Vout
VSWH
MODE
VSW
ISET
SS
VB
NCP3235
VB
FB
EN
COMP
PG
PGND
AGND
Figure 2. NCP3235 Typical Application Circuit Without External VCC
VIN ≥ 3.0 V
BST
VIN
Vout
VSWH
MODE
VSW
ISET
SS
NCP3235
VCC = 5 V
FB
VB
VCC
VB
EN
COMP
PG
AGND
PGND
Figure 3. NCP3235 Typical Application Circuit With VCC = 5 V
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3
NCP3235
Table 2. ABSOLUTE MAXIMUM RATINGS (measured vs. GND pad, unless otherwise noted)
Rating
Symbol
Value
Unit
VIN, VCC
23
−0.3
V
VSW to GND
VSWH, VSW
30
−0.6 (DC)
35 (t < 50 ns)
−5 (t < 50 ns)
V
BST to GND
BST
35 (DC)
−0.6 (DC)
40 (t < 50 ns)
V
BST to VSW
VBST_VSW
6.5 (DC)
−0.3 (DC)
V
6.0
−0.3
V
1.0
kV
Power Supply to GND
All other input pins
Electrostatic Discharge Human body model
HBM
Electrostatic Discharge Charge device model
CDM
2.0
kV
TA
−40 to +85
°C
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
TJ
−40 to +125
°C
TJ(MAX)
+150
°C
Tstg
−55 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. THERMAL INFORMATION
HS FET Junction−to−case−bottom thermal resistance (Note 1)
RqJC−HS
1.3
°C/W
LS FET Junction−to−case−bottom thermal resistance (Note 1)
RqJC−LS
0.6
°C/W
RqA
35
°C/W
Junction−to−ambient thermal resistance
1. RθJC thermal resistance is obtained by simulating a cold plate test on the exposed power pad. No specific JEDEC standard test exists, but
a close description can be found in the ANSI SEMI standard G30−88.
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NCP3235
Table 4. ELECTRICAL CHARACTERISTICS
(−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted, TJ = +25°C for typical values)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
21
V
4.2
4.3
4.4
V
3.8
3.95
4.0
V
4.86
5.15
5.45
V
IB = 25 mA, VCC = 4.5 V
65
120
mV
EN=H, COMP=H, no switching;
PG open; no switching
4.7
6.4
mA
EN=0; Vcc=21 V; PG open
100
140
mA
EN=0; Vcc=4.5; PG open
75
85
mA
mV
POWER SUPPLY
VIN/VCC Operation Voltage
VIN/VCC
4.5
VB UVLO Threshold (Rising)
VB UVLO Threshold (Falling)
VB Output Voltage
VB
VB Dropout voltage
VCC Quiescent Current
Shutdown Supply Current
VCC = 6 V, 0 ≤ IB ≤ 40 mA
FEEDBACK VOLTAGE
FB input voltage
Feedback Input Bias Current
VFB
IFB
TJ = 25°C, 4.5 V ≤ VCC ≤ 21 V
597
600
603
−40°C ≤ TJ ≤ 125°C;
4.5 V ≤ VCC ≤ 21 V
594
600
606
VFB = 0.6 V
75
nA
ERROR AMPLIFIER
Open Loop DC Gain (GBD)
Open Loop Unity Gain Bandwidth
60
F0dB,EA
Open Loop Phase Margin
85
dB
24
MHz
60
deg
2.5
V/m
COMP Clamp Voltage, High
3.3
V
COMP Clamp Voltage, Low
0.57
V
Slew Rate
COMP pin to GND = 10 pF
Output Source Current
Output Sink Current
VFB = 0.55 V
15
mA
VFB = 1 V
20
mA
CURRENT LIMIT
Low−side RDS(on)/ISET
Low−side ISET Current Source
Temperature Coefficient
RDS(on)/
ISET
LS_OCPth
Low−side programmable OCP range
LS OCP Blanking time
W/A
+0.33
%/°C
Guaranteed by design
600
mV
Guaranteed by design
600
mV
TC_LS_ISET
Low−side OCP switch−over threshold
Low−side Fixed OCP threshold
108
Guaranteed by
characterization, TJ = 25°C
Guaranteed by design
LS_Tblnk
<600
mV
Guaranteed by design
150
ns
fsw = 550 kHz,
4.5 V < VCC < 21 V
87
%
fsw = 1.1 MHz,
4.5 V < VCC < 21 V
76
VCOMP < PWM Ramp Offset
Voltage
0
%
Minimum GH on−time
Guaranteed by design
35
ns
PWM Ramp Amplitude
Guaranteed by characterization
PWM
Maximum duty cycle
Minimum duty cycle
PWM Ramp Offset
VCC/7.9
VCC/6.5
0.67
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VCC/5.6
V
V
NCP3235
Table 4. ELECTRICAL CHARACTERISTICS
(−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted, TJ = +25°C for typical values)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
fsw
fsw = 550 kHz
4.5 V < VCC < 21 V
500
550
600
kHz
fsw = 1100 kHz
4.5 V < VCC < 21 V
990
1100
1210
OSCILLATOR
Oscillator Frequency Range
Hiccup Timer
Thiccup
tss < 1 ms
4
Tss > 1 ms
4 x tss
ms
ZERO CROSSING
Zero Crossing Comparator Internal
Offset
PGND−VSW, Automatic
CCM/DCM
Guaranteed by design
−4.5
−3.0
−1.5
mV
0.25
V
MODE
Mode pin threshold voltage
Mode pin source current
ModeTHS
GND
49.9 kW
0.43
0.65
100 kW
0.86
1.15
174 kW
1.48
2.0
Floating
2.4
IMode
8.8
10
11.2
mA
5.5
V
1.29
V
ENABLE INPUT (EN)
EN Input Operating Range
Enable Threshold Voltage
V_EN
Enable Threshold Voltage
Min VEN rising
1.11
Max VEN falling
Deep Disable Threshold
1.2
1.05
0.7
Enable Pull−up Current
0.8
V
0.9
V
2
mA
1.45
ms
SOFTSTART INPUT (SS)
SS Startup Delay
tSSD
SS End Threshold
SSEND
SS Source Current
ISS
0.6
V
2.15
2.5
2.8
mA
10
20
30
mA
687
700
713
mV
475
500
525
mV
VOLTAGE MONITOR
Power Good Sink Current
PG = 0.15 V
Output Overvoltage Rising Threshold
Overvoltage Fault Blanking Time
ms
4.0
Output Under−Voltage Trip Threshold
Under−voltage Protection Blanking
Time
ms
20
POWER STAGE
High−side On Resistance
RDSONH
VIN/VCC = 5 V, ID = 2 A
6.5
10
mW
Low−side On Resistance
RDSONL
VIN/VCC = 5 V, ID = 2 A
2.9
5.2
mW
IBOOT = 2 mA
28
mV
Thermal Shutdown Threshold
Guaranteed by Characterization
150
°C
Thermal Shutdown Hysteresis
Guaranteed by Characterization
25
°C
VFBOOT
THERMAL SHUTDOWN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP3235
0.604
118
0.603
116
0.602
114
RDS(on)/Iset
0.601
0.600
0.599
110
106
0.597
0.596
−40 −25 −10
5
20
35
50
65
80
104
−45 −30 −15 0
95 110 125
15
30
45
60
75
90 105 120 135
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Reference Voltage vs. Temperature
Figure 5. RDS(on)/Iset vs. Temperature
1.23
1.22
1.21
1.20
1.19
1.18
−40 −25 −10
5
20
35
50
65
80
95 110 125
1.08
1.07
1.06
1.05
1.04
1.03
1.02
−40 −25 −10
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Rising Enable Threshold vs.
Temperature
Figure 7. Falling Enable Threshold vs.
Temperature
6
IQ, QUIESCENT CURRENT (mA)
120
ISD, SHUTDOWN CURRENT (mA)
112
108
0.598
VEN, FALLING ENABLE THRESHOLD (V)
VEN, RISING ENABLE THRESHOLD (V)
VFB, FEEDBACK REFERENCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
110
100
90
80
70
VCC = 12 V
60
50
−40 −25 −10
5
20
35
50
65
80
5
4
3
2
VCC = 12 V
1
0
−40 −25 −10
95 110 125
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Shutdown Current vs. Temperature
Figure 9. Quiescent Current vs. Temperature
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NCP3235
TYPICAL CHARACTERISTICS
10
VIN/VCC = 12 V
2.65
9
2.60
2.55
HS RDS(on)
ISS, SOFT−START CURRENT (mA)
2.70
2.50
2.45
6
5
2.35
5
20
35
50
65
80
4
−45 −30 −15 0
95 110 125
30 45
60 75
90 105 120 135
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Soft−start Current vs. Temperature
Figure 11. HS RDS(on) vs. Temperature
4.40
VB UVLO RISING THRESHOLD
VOLTAGE (V)
4.5
15
TJ, JUNCTION TEMPERATURE (°C)
5.0
VIN/VCC = 12 V
4.0
3.5
3.0
2.5
2.0
−45 −30 −15
0
15
30
45
60 75
4.38
4.36
4.34
4.32
4.30
4.28
4.26
4.24
4.22
4.20
−40 −25 −10
90 105 120 135
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. LS RDS(on) vs. Temperature
Figure 13. VB UVLO Rising Threshold vs.
Junction Temperature
4.00
OVP, OVERVOLTAGE THRESHOLD (mV)
LS RDS(on)
7
2.40
2.30
−40 −25 −10
VB UVLO, FALLING THRESHOLD VOLTAGE (V)
8
3.96
3.92
3.88
3.84
3.80
−40 −25 −10
5
20
35
50
65
80
95 110 125
705
703
701
699
697
695
−40 −25 −10
5
20
35
50
65
80
95 110 125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 14. VB UVLO Falling Threshold vs.
Junction Temperature
Figure 15. Output OVP vs. Junction
Temperature
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NCP3235
510
100
95
506
EFFICIENCY (%)
UVP, UNDERVOLTAGE THRESHOLD (mV)
TYPICAL CHARACTERISTICS
502
498
494
90
85
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 5.0 V
80
75
490
−40 −25 −10
70
5
20
35
50
65
80
0
95 110 125
2
4
6
8
10
12
14
TJ, JUNCTION TEMPERATURE (°C)
LOAD CURRENT (A)
Figure 16. Output UVP vs. Junction
Temperature
Figure 17. Efficiency (FSW = 550 kHz,
VIN = 12 V, TA = Room)
16
100
100
95
95
EFFICIENCY (%)
EFFICIENCY (%)
90
90
85
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
80
75
85
VOUT = 1.0 V
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
VOUT = 5.0 V
VOUT = 12 V
80
75
70
65
60
70
0
2
4
6
8
10
12
14
0
16
2
4
6
8
10
12
14
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 18. Efficiency (FSW = 550 kHz,
VIN = 5 V, TA = Room)
Figure 19. Efficiency (FSW = 550 kHz,
VIN = 19 V, TA = Room)
16
0.20
95
0.18
FSW = 550 kHz
0.16
POWER LOSS (W)
EFFICIENCY (%)
90
85
FSW = 1.1 MHz
80
75
0.14
0.12
Sonic Mode
0.10
0.08
None Sonic Mode
0.06
0.04
70
0.02
0
65
0
2
4
6
8
10
12
14
0
16
0.05
0.10
0.15
0.20
0.25
0.30
0.35 0.40
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 20. Efficiency (VOUT = 1.0 V,
VIN = 12 V, TA = Room)
Figure 21. Power Loss Difference
(VOUT = 1.0 V, VIN = 12 V, TA = Room)
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NCP3235
TYPICAL CHARACTERISTICS
CH1 (Yellow): EN
CH2 (Green): VSW
CH3 (Orange): PG
CH4 (Blue): Vout
CH1 (Yellow): EN
CH2 (Green): VSW
CH3 (Orange): PG
CH4 (Blue): Vout
Figure 22. Soft Start Waveform
(no load, sonic mode disabled)
Figure 23. Pre−biased Soft Start Waveform
(no load, sonic mode disabled)
CH1 (Yellow): COMP
CH2 (Green): VSW
CH3 (Blue): Vout
CH1 (Yellow): COMP
CH2 (Green): VSW
CH3 (Blue): Vout
Figure 24. Steady−state CCM Operation
(load = 10 A)
Figure 25. Steady−state DCM Operation
(load = 0 A), sonic mode (enabled) limits
switching frequency around 30 kHz
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NCP3235
TYPICAL CHARACTERISTICS
CH1 (Yellow): COMP
CH2 (Green): VSW
CH3 (Blue): Vout
CH1 (Yellow): SS pin
CH2 (Green): VSW
CH3 (Blue): Vout
Figure 26. Stead−state DCM Operation
(load = 0 A), sonic mode (disabled) allows
switching frequency drop to about 100 Hz
Figure 27. Hiccup in Over Current Protection
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NCP3235
OPERATION DESCRIPTION
architecture enables smooth transition between light load
and heavy load while maintaining fast response to load
transients.
Protection features include overcurrent protection (OCP),
output over and under voltage protection (OVP, UVP), and
power good indicator. The enable function is highly
programmable to allow for adjustable startup voltages at
higher input voltages. There is also an adjustable soft−start,
and internal thermal shutdown.
The NCP3235 is a high efficiency, high current PWM
synchronous buck converter. It operates with a single supply
voltage from 4.5 to 23 V and provides output current as high
as 15 A. NCP3235 utilizes voltage mode with voltage
feed−forward control to respond instantly to input voltage
changes and provide for easier compensation over the
supply range of the converter. The device also includes
pre−bias startup capability to allow monotonic startup in the
event of a pre−biased output condition.
The NCP3235 provides two operation modes to fit various
application requirements. The automatic CCM/DCM mode
operation provides reduced power loss and increases the
efficiency at light load. The adaptive power control
Operation Mode
The NCP3235 offers five options programmed by MODE
pin connections, see Table 5 below.
Table 5. OPERATION MODE SELECTION
MODE pin Connection
Switching Frequency
Operation Mode
Overvoltage Protection
Sonic Mode
GND
550 kHz
Automatic CCM/DCM
Latch off
enabled
49.9 kW (±1%)
550 kHz
Automatic CCM/DCM
Latch off
disabled
100 kW (±1%)
1.1 MHz
Automatic CCM/DCM
Latch off
enabled
174 kW (±1%)
1.1 MHz
FCCM
Hiccup
not applied
Floating
1.1 MHz
Automatic CCM/DCM
Latch off
disabled
Forced Continuous Conduction Mode
In forced continuous conduction mode (FCCM), the
high−side FET is ON during the on−time and the low−side
FET is ON during the off−time. The switching is
synchronized to an internal clock thus the switching
frequency is fixed.
In Automatic CCM/DCM mode, the high−side FET is ON
during the on−time and low−side FET is ON during the
off−time until the inductor current reaches zero. An internal
zero−crossing comparator detects the zero crossing of the
inductor current from positive to negative. When the
inductor current reaches zero, the comparator sends a signal
to the logic circuitry and turns off the low−side FET.
When the load is increased, the inductor current is always
positive and the zero−crossing comparator does not send any
zero−crossing signal. The converter enters into continuous
conduction mode (CCM) when no zero−crossing is detected
for two consecutive PWM pulses. In CCM mode, the
switching synchronizes to the internal clock and the
switching frequency is fixed.
When MODE pin is connected with 175 kW resistor, the
NCP3235 is operating in forced continuous conduction
mode in both light load and heavy load conditions. In this
mode, the switching frequency remains constant over the
entire load range, making it suitable for applications that
need tight regulation of switching frequency at a cost of
lower efficiency at light load.
Reference Voltage
The NCP3235 incorporates an internal reference that
allows output voltages as low as 0.6 V. The tolerance of the
internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
Oscillator Ramp
The ramp waveform is a saw−tooth form at the PWM
frequency with a peak−to−peak amplitude of VCC/6.0, offset
from GND by typically 0.64 V. The PWM duty cycle is
limited to a maximum of 92%, allowing the bootstrap
capacitors to charge during each cycle.
Automatic Power Saving Mode
In Automatic CCM/DCM mode when the load current
decreases, the converter will enter power saving mode
operation. During power saving mode, the low−side
MOSFET will turn off when the inductor current reaches
zero. So the converter skips switching and operates with
reduced frequency, which minimizes the quiescent current
and maintains high efficiency. When sonic mode is enabled,
the lowest switching frequency is limited above 30 kHz to
stay out of audible noise frequency range.
Error Amplifier
The error amplifier’s primary function is to regulate the
converter’s output voltage using a resistor divider connected
from the converter’s output to the FB pin of the controller,
as shown in the Applications Schematic. A type III
compensation network must be connected around the error
amplifier to stabilize the converter. It has a bandwidth of
greater than 24 MHz, with open loop gain of at least 60 dB.
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12
NCP3235
Programmable Soft−Start
circuitry is off. As the voltage at EN continues to rise, the
Enable comparator and reference are active and provide a
more accurate EN threshold. The drivers are held off until
the rising voltage at EN crosses V_EN. An internal 2 mA
pullup automatically enables the device when the EN pin is
left floating.
An external capacitor connected from the SS pin to
ground sets up the soft start period, which can limit the
start−up inrush current. The soft start period can be
programmed based on the Equation 1.
t SS +
C SS @ V ref
I SS
(eq. 1)
INPUT SUPPLY / VCC
OCP and TSD (thermal shutdown) are the only
protections that are active during a soft−start.
VDD
Adaptive Non−Overlap Gate Driver
2 uA
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side
drive signal to avoid shoot through. During the dead time,
the body diode of the low side FET freewheels the current.
The body diode has much higher voltage drop than that of
the MOSFET, which reduces the efficiency significantly.
The longer the body diode conducts, the lower the
efficiency. NCP3235 implements adaptive dead time
control to minimize the dead time, as well as preventing
shoot through.
EN
Enable
Logic
1.2 V
Figure 28. Enable Functional Block Diagram
Pre−bias Startup
In some applications the controller will be required to start
switching when it’s output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP3235 supports pre−bias
start up by holding off switching until the feedback voltage
rises above the set regulated voltage. If the pre−bias voltage
is higher than the set regulated voltage, switching does not
occur until the output voltage drops back to the regulation
point.
Precision Enable (EN)
The ENABLE block allows the output to be toggled on
and off and is a precision analog input.
When the EN voltage exceeds V_EN, the controller will
initiate the soft−start sequence as long as the input voltage
and sub−regulated voltage have exceeded their UVLO
thresholds. V_EN_hyst helps to reject noise and allow the
pin to be resistively coupled to the input voltage or
sequenced with other rails.
If the EN voltage is held below typically 0.8 V, the
NCP3235 enters a deep disable state where the internal bias
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13
NCP3235
PROTECTION FEATURES
Hiccup Mode
third consecutive count, the device enters hiccup/latch
mode. The scheme of LS OCP and hiccup mode protection
is described in Figure 29.
The NCP3235 uses hiccup mode for over current
protection. Upon entering hiccup mode after a fault
detection, the NCP3235 turns off the high side and low side
FET’s and PG goes low. It waits for tHiccup ms before
reinitiating a soft−start. tHiccup is defined as four soft start
timeouts (tss). The equation for tss is shown in Equation 1.
OCP is the only active fault detection during the hiccup
mode soft start.
Thermal Shutdown (TSD)
The NCP3235 protects itself from overheating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold both
the upper and lower MOSFETs will be shut OFF. Once the
temperature drops below the falling hysteresis threshold, the
voltage at the COMP pin will be pulled below the ramp
valley voltage and a soft−start will be initiated.
Over Voltage Protection (OVP)
When the voltage at the FB pin (VFB) is above the OVP
threshold for greater than 5 ms (typical), an OVP fault is set.
The high side FET (HSFET) will turn off and the low side
FET (LSFET) will turn on. The open−drain PG pull down
will turn on at that point as well, thus pulling PG low. Once
VFB has fallen below the Undervoltage Protection
Threshold (UVP), the device will enter hiccup/latch off
mode. If entering latch off mode after a fault detection, the
NCP3235 turns off the high side and turns on the low side
FET’s and PG goes low. The user has to toggle the input
power supply to restart the device.
Power Good Monitor (PG)
NCP3235 monitors the output voltage and signal when the
output is out of regulation or during a non−regulated
pre−bias condition, or fault condition. When the output
voltage is within the OVP and UVP thresholds, the power
good pin is a high impedance output. If the NCP3235 detects
an OCP, OVP, UVP, TSD or is in soft start, it pulls PG pin
low. The PG pin is an open drain 5−mA pull down output.
Layout Guide
When laying out a power PCB for the NCP3235 there are
several key points.
General Layout Guide: these are the common techniques
for high frequency high power board layout design.
Base component placement: High current path
components should be placed to keep the current path as
tight as possible. Placement of components on the bottom of
the board such as input or output decoupling can add loop
inductance.
Ground Return for Power and Signals: Solid,
uninterrupted ground planes must be present and adjacent to
the high current path.
Copper Shapes on Component Layers: Large copper
planes on one or multiple layers with adequate vias will
increase thermal transfer, reduce copper conduction losses,
and minimize loop inductance. Greater than 20 A designs
require 2~3 layer shapes or more, increasing the number of
layers will only improvement performance.
Via Placement for Power and Ground: Place enough vias
to adequately connect outer layers to inner layers for thermal
transfer and to minimize added inductance in layer
transition. Multiple vias should be placed near important
components like input and output ceramic capacitors.
Key Signal Routes: Do not route sensitive signals, such as
FB near or under noisy nets such as the switch node VSW
and BST node, to reduce noise coupling effects on the
sensitive lines.
To improve the Low−side OCP accuracy, users should use
single ground connection instead of separate analog ground
and power ground. Make sure that the inner layers (at least
2nd layer, 3rd layer and 4th layer) are dedicated for ground
plane. Do not use other copper planes to break or interrupt
Under Voltage Protection (UVP)
A UVP circuit monitors the VFB voltage to detect an
under voltage event. If the VFB voltage is below this
threshold for more than 20 ms, a UVP fault is set and the
device will enter hiccup mode.
Over Current Protection (OCP)
The NCP3235 over current protection scheme senses the
peak freewheeling current in the low−side FET (LSOCP)
after a blanking time of 150 ns as shown in Figure 29. The
low−side MOSFET drain to source voltage is compared
against the voltage of an internal temperature compensated
current source and a user−selected resistor RSET. The value
of RSET for a given OCP level is defined by the follow
equation:
RSET +
i LS
RDSON
i SET
4
(eq. 2)
In this equation, iLS is the inductor peak current value,
RDSON is the on resistance of low−side MOSFET, and iSET
is an internal current source used to compensate the
temperature effects of on resistance of low−side MOSFET.
NCP3235 can guarantee that RDSON/iSET is a constant
value. By doing this, OCP accuracy won’t be affected by the
variation of MOSFET RDSON. In case RSET is not
connected, the device switches the OCP threshold to a fixed
300 mV threshold.
After one OCP event is detected, the NCP3235 keeps the
high−side MOSFET off until the low−side MOSFET falls
below the trip point again and the high−side MOSFET turns
on in the next clock cycle. So the low−side over current
protection shows pulse skipping behavior. An internal OCP
counter will count up to 3 consecutive OCP events. After the
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14
NCP3235
thermal conductivity of the board; all the thermal vias must
be either plated (copper) shut or plugged and capped on both
sides of the board. This prevents solder seeping in to the
thermal vias causing solder voids. Solder voids are
detrimental to the thermal and electrical performance of the
package; to ensure reliability and performance, the solder
coverage should be at least 85 percent. This means the total
voids on the ground pad should be less than 15 percent with
no single void larger than 1 mm. Several smaller voids are
always better than a few big voids.
the shape of ground plane, which may add more parasitic
components to affect the sensing accuracy.
Thermal management consideration: the major heat flow
path from package to the ambient is through the copper on
the PCB, the area and thickness of copper plane affect the
themeral performance; maximize the copper coverage on all
the layers to increase the effective thermal conductivity of
the board. This is importatnt especially when there is no heat
sinks attached to the PCB on the other side of the package.
Add as many thermal vias as possible directly under the
package ground pad to maximize the effective out−of−plane
Power Good (PG) Operation
Power Good Pullup Voltage
LSOCP Trip Level
Inductor Current
Start
Reset/Start
Reset/Start
Backup Counter
Hiccup
Start
Hiccup Counter
1
2
3
tHiccup = 4xtSS
Skipped Pulses showing Skip Count
Figure 29. LSOCP Function with Counters and Power Good Shown (exaggerated for informational purposes)
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15
NCP3235
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
CASE 485CM
ISSUE O
ÉÉÉ
ÉÉÉ
ÉÉÉ
A B
D
PIN ONE
LOCATION
2X
L
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
ÉÉ
ÉÉ
0.15 C
EXPOSED Cu
2X
TOP VIEW
0.15 C
(A3)
DETAIL B
0.10 C
DIM
A
A1
A3
b
D
D2
D3
E
E2
E3
E4
e
G
K
L
L1
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
A
43X
0.08 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. POSITIONAL TOLERANCE APPLIES TO ALL
THREE EXPOSED PADS.
L
SIDE VIEW A1
C
NOTE 4
SEATING
PLANE
0.10 C A B
D3
D2
NOTE 5
G
DETAIL A
40X
L
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.18
0.30
6.00 BSC
2.30
2.50
1.40
1.60
6.00 BSC
4.30
4.50
1.90
2.10
1.64
1.84
0.50 BSC
2.20 BSC
0.20
−−−
0.30
0.50
−−−
0.15
SOLDERING FOOTPRINT*
6.30
E3
4.56
E2
1.66
E4
1
1
G
40
K
e
40X
e/2
G
BOTTOM VIEW
40X
0.63
2.56
b
0.10 C A B
0.05 C
2.16
4.56
NOTE 3
6.30
2.16
PKG
OUTLINE
40X
0.50
PITCH
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP3235/D