INTERSIL JANSR2N7272

JANSR2N7272
Formerly FRL130R4
8A, 100V, 0.180 Ohm, Rad Hard,
N-Channel Power MOSFET
June 1998
Features
Description
• 8A, 100V, rDS(ON) = 0.180Ω
The Intersil Corporation,has designed a series of SECOND
GENERATION hardened power MOSFETs of both N-Channel and P-Channel enhancement types with ratings from
100V to 500V, 1A to 60A, and on resistance as low as
25mΩ. Total dose hardness is offered at 100K RAD (Si) and
1000K RAD (Si) with neutron hardness ranging from 1E13
for 500V product to 1E14 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates to 1E9 without current
limiting and 2E12 with current limiting.
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BVDSS
- Typically Survives 2E12 if Current Limited to IDM
• Photo Current
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to exhibit minimal characteristic changes to total dose (GAMMA) and
neutron (no) exposures. Design and processing efforts are
also directed to enhance survival to dose rate (GAMMA
DOT) exposure.
- 1.5nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm2
- Usable to 3E14 Neutrons/cm2
Also available at other radiation and screening levels. See us
on
the
web,
Intersil’s
home
page:
http://www.semi.harris.com. Contact your local Intersil
Sales Office for additional information.
Ordering Information
PART NUMBER
JANSR2N7272
PACKAGE
TO-205AF
BRAND
JANSR2N7272
Symbol
Die family TA17631.
D
MIL-PRF-19500/604.
G
S
Package
TO-205AF
D
G
S
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
2-3
File Number
4297.2
JANSR2N7272
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS
Maximum Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJC, TSTG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JANSR2N7272
100
100
UNITS
V
V
8
5
24
±20
A
A
A
V
25
10
0.20
24
8
24
-55 to 150
300
W
W
W/oC
A
A
A
oC
oC
1.0
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge (Not on slash sheet)
SYMBOL
MIN
TYP
MAX
UNITS
100
-
-
V
-
-
5.0
V
2.0
-
4.0
V
1.0
-
-
V
-
-
25
µA
-
-
250
µA
-
-
100
nA
-
-
200
nA
-
-
1.51
V
-
-
0.180
Ω
-
-
0.360
Ω
-
-
35
ns
-
-
210
ns
td(OFF)
-
-
200
ns
tf
-
-
145
ns
-
-
142
nC
-
-
76
nC
-
-
4
nC
nC
BVDSS
VGS(TH)
IDSS
IGSS
VDS(ON)
rDS(ON)
td(ON)
tr
TEST CONDITIONS
ID = 1mA, VGS = 0V
VGS = VDS,
ID = 1mA
VDS = 80V,
VGS = 0V
VGS = ±20V
TC = -55oC
TC = 25oC
TC = 125oC
TC = 25oC
TC = 125oC
TC = 25oC
TC = 125oC
VGS = 10V, ID = 8A
ID = 5A,
VGS = 10V
TC = 25oC
TC = 125oC
VDD = 50V, ID = 8A,
RL = 6.3Ω, VGS = 10V,
RGS = 25Ω
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge (Not on slash sheet)
Qg(TH)
VGS = 0V to 2V
VDD = 50V,
ID = 8A
Gate Charge Source
Qgs
-
-
13
Gate Charge Drain
Qgd
-
-
38
nC
Thermal Resistance Junction to Case
RθJC
-
-
5.0
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
175
oC/W
2-4
JANSR2N7272
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Forward Voltage
TEST CONDITIONS
VSD
Reverse Recovery Time
ISD = 8A
trr
MIN
TYP
MAX
UNITS
0.6
-
1.8
V
-
-
450
ns
ISD = 8A, dISD/dt = 100A/µs
Electrical Specifications up to 100K RAD
PARAMETER
TC = 25oC, Unless Otherwise Specified
MIN
MAX
UNITS
Drain to Source Breakdown Volts
(Note 3)
SYMBOL
BVDSS
VGS = 0, ID = 1mA
TEST CONDITIONS
100
-
V
Gate to Source Threshold Volts
(Note 3)
VGS(TH)
VGS = VDS, ID = 1mA
2.0
4.0
V
Gate to Body Leakage
(Notes 2, 3)
IGSS
VGS = ±20V, VDS = 0V
-
100
nA
Zero Gate Leakage
(Note 3)
IDSS
VGS = 0, VDS = 80V
-
25
µA
Drain to Source On-State Volts
(Notes 1, 3)
VDS(ON)
VGS = 10V, ID = 8A
-
1.51
V
Drain to Source On Resistance
(Notes 1, 3)
rDS(ON)
VGS = 10V, ID = 5A
-
0.180
Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 10V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS .
Typical Performance Curves
Unless Otherwise Specified
100
10
TC = 25oC
ID , DRAIN CURRENT (A)
ID , DRAIN (A)
8
6
4
2
0
-50
0
50
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
TC , CASE TEMPERATURE (oC)
NORMALIZED
THERMAL RESPONSE (ZθJC)
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10ms
1
0.1
150
100
100µs
10
1
100ms
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
100
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
1
0.5
0.1
0.2
0.1
0.05
0.02
0.01
PDM
SINGLE PULSE
0.01
0.001
10-5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-5
t1
t2
100
101
JANSR2N7272
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN IAS IS REACHED
VDS
L
BVDSS
+
CURRENT I
TRANSFORMER AS
tP
-
VARY tP TO OBTAIN
REQUIRED PEAK IAS
50Ω
VDD
50V-150V
DUT
tP
VDD
+
VGS ≤ 20V
0V
VDS
IAS
50Ω
tAV
FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 5. UNCLAMPED ENERGY WAVEFORMS
tON
VDD
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
VDS
VGS = 10V
10%
DUT
10%
0V
90%
RGS
50%
VGS
50%
PULSE WIDTH
10%
FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 7. RESISTIVE SWITCHING WAVEFORMS
QG
10V
QGS
QGD
VG
CHARGE
FIGURE 8. BASIC GATE CHARGE WAVEFORM
2-6
JANSR2N7272
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS)
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
UNITS
Gate to Source Leakage Current
IGSS
VGS = ±20V
±20 (Note 4)
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 80% Rated Value
Drain to Source On Resistance
rDS(ON)
TC = 25oC at Rated ID
Gate Threshold Voltage
VGS(TH)
ID = 1.0mA
±25 (Note 4)
µA
±20% (Note 5)
Ω
±20% (Note 5)
V
NOTES:
4. Or 100% of Initial Reading (whichever is greater).
5. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
VGS = 30V, t = 250µs
Pind
Required
Pre Burn-In Tests (Note 6)
MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 6)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours
PDA
5%
Final Electrical Tests (Note 6)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
6. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
Unclamped Inductive Switching
SYMBOL
SOA
TEST CONDITIONS
VDS = 80V, t = 10ms
MAX
UNITS
1.50
A
IAS
VGS(PEAK) = 15V, L = 0.1mH
24
A
Thermal Response
∆VSD
tH = 10ms; VH = 25V; IH = 2A
92
mV
Thermal Impedance
∆VSD
tH = 500ms; VH = 25V; IH = 1A
190
mV
2-7
JANSR2N7272
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A
- Attributes Data Sheet
G. Group B
- Attributes Data Sheet
H. Group C
- Attributes Data Sheet
I. Group D
- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
I. Group D
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
2-8
JANSR2N7272
TO-205AF
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE
INCHES
ØD
ØD1
SYMBOL
P
A
h
SEATING
PLANE
L
Øb
e
e1
2
e2
1
90o
3
45o
j
k
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.160
0.180
4.07
4.57
-
Øb
0.016
0.021
0.41
0.53
2, 3
ØD
0.350
0.370
8.89
9.39
-
ØD1
0.315
0.335
8.01
8.50
-
e
0.095
0.105
2.42
2.66
4
e1
0.190
0.210
4.83
5.33
4
e2
0.095
0.105
2.42
2.66
4
h
0.010
0.020
0.26
0.50
-
j
0.028
0.034
0.72
0.86
-
k
0.029
0.045
0.74
1.14
-
L
0.500
0.560
12.70
14.22
3
P
0.075
-
1.91
-
5
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.
2. Lead dimension (without solder).
3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of seating plane.
5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).
6. Lead no. 3 butt welded to stem base.
7. Controlling dimension: Inch.
8. Revision 3 dated 6-94.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
2-9
ASIA
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Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029