Ordering number : ENA1998 LV8727 Bi-CMOS LSI PWM Current Control Stepping Motor Driver http://onsemi.com Overview The LV8727 is a PWM current-controlled micro step bipolar stepping motor driver. This driver can do eight ways of micro step resolution of Half, 1/8, 1/16, 1/32, 1/64, 1/128, 1/10, 1/20 Step, and can drive simply by the step input. Features • Single-channel PWM current control stepping motor driver. • Output on-resistance (upper side : 0.25Ω ; lower side : 0.15Ω ; total of upper and lower : 0.4Ω ; Ta = 25°C, IO = 4.0A) • Half, 1/8, 1/16, 1/32, 1/64, 1/128, 1/10, 1/20 Step are selectable. • Advance the excitation step with the only step signal input. • BiCDMOS process IC. • Available forward reverse control. • IO max=4.0A • Thermal shutdown circuit. • Input pull down resistance • With reset pin and enable pin. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Symbol Conditions Ratings Unit VM max 50 V 4 A Output current IO max Output peak current IO peak Logic input voltage VIN max VREF input voltage VREF max 6 V MO / DOWN pin input voltage VMO /VDOWN max 6 V tw≤10ms, duty 20% Indipendent IC 4.6 A 6 V Allowable power dissipation Pd max 2.45 W Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time. Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 June, 2013 N1611 SY 20111019-S00003 No.A1998-1/23 LV8727 Recommendation Operating Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage range VM 9 to 45 V Logic input voltage VIN 0 to 5 V VREF input voltage range VREF 0 to 3 V Electrical Characteristics at Ta = 25°C, VM = 24V, VREF = 1.5V Parameter Standby mode current drain Symbol Conditions IMst ST = “L” Current drain IM ST = “H”, OE = “H”, no load Thermal shutdown temperature TSD Design guarantee Thermal hysteresis width ΔTSD Design guarantee Logic pin input current IINL VIN = 0.8V IINH VIN = 5V Logic high-level input voltage VINH Logic low-level input voltage VINL Ratings min typ 100 μA 3.5 4.9 mA 180 200 °C 70 150 Unit max °C 40 3 8 15 μA 30 50 70 μA 0.8 V 3.1 V 0.8 V 2.0 FDT pin high-level voltage Vfdth 3.5 FDT pin middle-level voltage Vfdtm 1.1 FDT pin low-level voltage Vfdtl Cosc1 = 100pF V V Chopping frequency Fch 70 100 130 kHz OSC1 pin charge/discharge current Iosc1 7 10 13 μA Chopping oscillation circuit Vtup1 0.8 1 1.2 V threshold voltage Vtdown1 0.3 0.5 0.7 VREF pin input voltage Iref VREF = 1.5V DOWN output residual voltagr VO1DOWN Idown = 1mA MO pin residual voltage VO1MO Imo = 1mA Hold current switching frequency Fdown Cosc2 = 1500pF OSC2 pin charge/discharge current V μA -0.5 50 200 mV 50 200 mV 1.12 1.6 2.08 Hz Iosc2 7 10 13 μA Hold current switching frequency Vtup2 0.8 1 1.2 V threshold voltage Vtdown2 0.3 0.5 0.7 V Output on-resistance Ronu IO = 4.0A, high-side ON resistance 0.25 0.325 Ω Rond IO = 4.0A, low-side ON resistance 0.15 0.195 Ω 50 μA 1 1.3 V 0.5 0.515 V Output leakage current IOleak VM = 50V Diode forward voltage VD ID = -4.0A Current setting reference voltage VRF VREF = 1.5V, Current ratio 100% 0.485 No.A1998-2/23 LV8727 Package Dimensions unit : mm (typ) 3236A 29.2 25.6 (22.8) ( 2.5) 4.5 14.5 (14.4) (11.0) 21.7 18.6 max (R1.7) (5.0) 0.4 25 (2.6) (1.0) 2.0 3.5 1 0.52 4.0 4.2 2.0 SANYO : HZIP25 Pd max - Ta 3.0 Allowable power dissipation, Pd max - W (12.3) (8.5) 2.45 2.0 1.27 1.0 0 —30 0 30 60 90 120 Ambient temperature, Ta - C No.A1998-3/23 TSD Oscllator ST Output pre stage OSC2 MD1 MD2 OUT1B VM1 VM2 OUT2A MD3 FR + RF2 FDT OSC1 Decay Mode setting circuit Current select circuit OUT2B STEP RST OE Output control logic Output pre stage Current select circuit + OUT1A Output pre stage SGND + - Regulator 1 RF1 Output pre stage VREF PGND2 PGND1 Regulator 2 + - DOWN MO LV8727 Block Diagram No.A1998-4/23 LV8727 Pin Assignment 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 RF1 PGND1 OUT1A VM1 ST MD1 MD2 MD3 OE RST FR STEP OSC1 OSC2 FDT DOWN MO VREF SGND VM2 OUT2B PGND2 24 25 OUT2A 2 RF2 1 OUT1B LV8727 Top view Pin Functions Pin No. Pin Name Pin Functtion 7 MD1 Excitation mode switching pin 8 MD2 Excitation mode switching pin 9 MD3 Excitation mode switching pin 10 OE Output enable signal input pin 11 RST Reset signal input pin 12 FR Forward / Reverse signal input pin 13 STEP Clock pulse signal input pin Equivalent Circuit Internal 5V regulator GND 6 ST Chip enable input pin. Internal 5V regulator GND 1 OUT1B Channel 1 OUTB output pin. 2 RF1 Channel 1 current-sense resistor connection pin. 3 PGND1 Channel 1 power GND 4 OUT1A Channel 1 OUTA output pin. 5 Channel 1 motor supply connect pin 21 VM1 VM2 22 OUT2B Channel 2 OUTB output pin. 23 PGND2 Channel 2 power GND 24 RF2 Channel 2 current-sense resistor connection pin. 25 OUT2A Channel 2 OUTA output pin. 5 21 Channel 2 motor supply connect pin 4 25 1 22 3 23 2 24 GND Continued on next page. No.A1998-5/23 LV8727 Continued from preceding page. Pin No. 19 Pin Name VREF Pin Functtion Constant-current control reference voltage input pin. Equivalent Circuit Internal 5V regulator GND 17 DOWN Holding current output pin. 18 MO Position detecting monitor pin. Internal 5V regulator GND 14 OSC1 Chopping frequency setting capacitor connection pin. 15 OSC2 Holding current detection time setting capacitor Internal 5V regulator connection pin. GND 16 FDT Decay mode select voltage input Internal 5V regulator GND No.A1998-6/23 LV8727 Reference describing operation (1) Stand-by function When ST pin is at low levels, the IC enters stand-by mode, all logic is reset and output is turned OFF. When ST pin is at high levels, the stand-by mode is released. (2) STEP pin function STEP input advances electrical angle at every nising edge (advances step by step). Operating mode Input ST STEP Low * Standby mode High Excitation step proceeds High Excitation step is kept (3) Excitation setting method Set the excitation setting as shown in the following table by setting MD1 pin, MD2 pin and MD3 pin. Input Initial position Mode MD3 MD2 MD1 (Excitation) 1ch current 2ch current Low Low Low Half 100% 0% Low Low High 1/8 100% 0% 0% Low High Low 1/16 100% Low High High 1/32 100% 0% High Low Low 1/64 100% 0% High Low High 1/128 100% 0% 0% 0% High High Low 1/10 100% High High High 1/20 100% The initial position is also the default state at start-up and excitation position at counter-reset in each Micro step resolution. (4) MO output pin MO output pin serves as open-drain connection. If MO pin will be in the state of an initial position, it is turned on, and it outputs a Low level. Excitation position MO Initial position Low Other initial position OPEN (5) Output current setting Output current is set shown below by the VREF pin (applied voltage) and a resistance value between RF1(2) pin and GND. IOUT = ( VREF / 3 ) / RF1 (2) resistance * The setting value above is a 100% output current in each excitation mode. (Example) When VREF = 0.9V and RF1 (2) resistance is 0.1Ω, the setting is shown below. IOUT = ( 0.9V / 3 ) / 0.1Ω = 3A No.A1998-7/23 LV8727 (6) Output enable function When the OE pin is set Low, the output is forced OFF and goes to high impedance. However, the internal logic circuits are operating, so the excitation position proceeds when the STP is input. Therefore, when OE pin is returned to High, the output level conforms to the excitation position proceeded by the STEP input. OE Operation mode L Output: OFF H Output: ON OE Power save mode STEP MO 1ch output 0% 2ch output Output is high-impedance (7) Reset function When the RST pin is set Low, the output goes to initial mode and excitation position is fixed in the initial position for STEP pin and FR pin input. MO pin outputs at low levels at the initial position. (Open drain connection) RST Operation mode H Normal operation L Reset state RST RESET STEP MO 1ch output 0% 2ch output Initial state No.A1998-8/23 LV8727 (8) Forward / reverse switching function FR Operating mode Low Clockwise (CW) High Counter-clockwise (CCW) FR CW mode CCW mode CW mode STEP Excitation position (1) (2) (3) (4) (5) (6) (5) (4) (3) (4) (5) 1ch output 2ch output The internal D/A converter proceeds by a bit on the rising edge of the step signal input to the STEP pin. In addition, CW and CCW mode are switched by FR pin setting. In CW mode, the channel 2 current phase is delayed by 90° relative to the channel 1 current. In CCW mode, the channel 2 current phase is advanced by 90° relative to the channel 1 current. (9) DECAY mode setting Current DECAY method is selectable as shown below by applied voltage to the FDT pin. FDT voltage DECAY method 3.5V to SLOW DECAY 1.1V to 3.1V or OPEN MIXED DECAY To 0.8V FAST DECAY (10) Chopping frequency setting function Chopping frequency is set as shown below by a capacitor between OSC1 pin and GND. Fcp = 1 / ( Cosc1 / 10 х 10-6 ) (Hz) (Example) When Cosc1 = 180pF, the chopping frequency is shown below. Fcp = 1 / ( 180 х 10-12 / 10 х 10-6 ) = 55.6(kHz) No.A1998-9/23 LV8727 (11) Output current in each micro step resolution Output current vector locus (one step is normalized to 90 degrees) Half, 1/8, 1/16, 1/32, 1/64, 1/128 Step Channel 1 current ratio (%) 100.0 66.7 33.3 0.0 0.0 33.3 66.7 100.0 Channel 2 current ratio (%) Current setting ratio in each micro step resolution STEP θ0 θ1 θ2 θ3 θ4 θ5 θ6 θ7 θ8 θ9 θ10 θ11 θ12 θ13 θ14 θ15 θ16 θ17 θ18 θ19 θ20 θ21 θ22 θ23 θ24 θ25 1/128 (%) 1ch 2ch 100 0 100 1 100 2 100 4 100 5 100 6 100 7 100 9 100 10 99 11 99 12 99 13 99 15 99 16 99 17 98 18 98 20 98 21 98 22 97 23 97 24 97 25 96 27 96 28 96 29 95 30 1/64 (%) 1ch 2ch 100 0 100 2 100 5 100 7 100 10 99 12 99 15 99 17 98 20 98 22 97 24 96 27 96 29 1/32 (%) 1ch 2ch 100 0 100 5 100 10 99 15 98 20 97 24 96 29 1ch 100 1/16 (%) 2ch 0 100 10 98 20 96 29 1/8 (%) 1ch 2ch 100 0 98 Half (%) 1ch 2ch 100 0 20 Continued on next page. No.A1998-10/23 LV8727 Continued from preceding page. STEP θ26 θ27 θ28 θ29 θ30 θ31 θ32 θ33 θ34 θ35 θ36 θ37 θ38 θ39 θ40 θ41 θ42 θ43 θ44 θ45 θ46 θ47 θ48 θ49 θ50 θ51 θ52 θ53 θ54 θ55 θ56 θ57 θ58 θ59 θ60 θ61 θ62 θ63 θ64 θ65 θ66 θ67 θ68 θ69 θ70 θ71 θ72 θ73 θ74 θ75 θ76 θ77 θ78 θ79 θ80 θ81 θ82 θ83 θ84 θ85 θ86 θ87 θ88 θ89 θ90 1/128 (%) 1ch 2ch 95 31 95 33 94 34 94 35 93 36 93 37 92 38 92 39 91 41 91 42 90 43 90 44 89 45 89 46 88 47 88 48 87 49 86 50 86 51 85 52 84 53 84 55 83 56 82 57 82 58 81 59 80 60 80 61 79 62 78 62 77 63 77 64 76 65 75 66 74 67 73 68 72 69 72 70 71 71 70 72 69 72 68 73 67 74 66 75 65 76 64 77 63 77 62 78 62 79 61 80 60 80 59 81 58 82 57 82 56 83 55 84 53 84 52 85 51 86 50 86 49 87 48 88 47 88 46 89 45 89 1/64 (%) 1ch 2ch 95 31 1/32 (%) 1ch 2ch 94 34 94 34 93 36 92 38 92 38 91 41 90 43 90 43 89 45 88 47 88 47 87 49 86 51 86 51 84 53 83 56 83 56 82 58 80 60 80 60 79 62 77 63 77 63 76 65 74 67 74 67 72 69 71 71 71 71 69 72 67 74 67 74 65 76 63 77 63 77 62 79 60 80 60 80 58 82 56 83 56 83 53 84 51 86 51 86 49 87 47 88 47 88 45 89 1/16 (%) 1ch 2ch 1/8 (%) 1ch 2ch 92 38 92 38 88 47 83 56 83 56 77 63 71 71 71 71 63 77 56 83 56 83 47 88 Halfe (%) 1ch 2ch 71 71 Continued on next page. No.A1998-11/23 LV8727 Continued from preceding page. STEP θ91 θ92 θ93 θ94 θ95 θ96 θ97 θ98 θ99 θ100 θ101 θ102 θ103 θ104 θ105 θ106 θ107 θ108 θ109 θ110 θ111 θ112 θ113 θ114 θ115 θ116 θ117 θ118 θ119 θ120 θ121 θ122 θ123 θ124 θ125 θ126 θ127 θ128 1/128 (%) 1ch 2ch 44 90 43 90 42 91 41 91 39 92 38 92 37 93 36 93 35 94 34 94 33 95 31 95 30 95 29 96 28 96 27 96 25 97 24 97 23 97 22 98 21 98 20 98 18 98 17 99 16 99 15 99 13 99 12 99 11 99 10 100 9 100 7 100 6 100 5 100 4 100 2 100 1 100 0 100 1/64 (%) 1ch 2ch 1/32 (%) 1ch 2ch 43 90 43 90 41 91 38 92 38 92 36 93 34 94 34 94 31 95 29 96 29 96 27 96 24 97 24 97 22 98 20 98 20 98 17 99 15 99 15 99 12 99 10 100 10 100 7 100 5 100 5 100 2 100 0 100 0 100 1/16 (%) 1ch 2ch 1/8 (%) 1ch 2ch 38 92 38 92 29 96 20 98 20 98 10 100 0 100 0 100 Half (%) 1ch 2ch 0 100 No.A1998-12/23 LV8727 Output current vector locus (one step is normalized to 90 degrees) 1/10, 1/20 STEP Channel 1 current ratio (%) 100.0 66.7 33.3 0.0 0.0 33.3 66.7 100.0 Channel 2 current ratio (%) Current setting ratio in each micro step resolution 1/10, 1/20 STEP STEP θ0 θ1 θ2 θ3 θ4 θ5 θ6 θ7 θ8 θ9 θ10 θ11 θ12 θ13 θ14 θ15 θ16 θ17 θ18 θ19 θ20 1/20 (%) 1ch 2ch 100 0 100 8 99 16 97 23 95 31 92 38 89 45 85 52 81 59 76 65 71 71 65 76 59 81 52 85 45 89 38 92 31 95 23 97 16 99 8 100 0 100 1/10 (%) 1ch 2ch 100 0 99 16 95 31 89 45 81 59 71 71 59 81 45 89 31 95 16 99 0 100 No.A1998-13/23 LV8727 (12) Current wave example in each micro step resolution (Half, 1/16, 1/128, 1/20 STEP) Half STEP (CW mode) STEP MO (%) 100 I1 0 -100 (%) 100 I2 0 -100 1/16 STEP (CW mode) STEP MO (%) 100 50 I1 0 -50 -100 (%) 100 50 I2 0 -50 -100 No.A1998-14/23 LV8727 1/128 STEP ( CW mode ) STEP MO (%) 100 50 I1 0 -50 -100 (%) 100 50 I2 0 -50 -100 1/20 STEP ( CW mode ) STEP MO (%) 100 50 I1 0 -50 -100 (%) 100 50 I2 0 -50 -100 No.A1998-15/23 LV8727 (13) Current control operation SLOW DECAY current control operation When FDT pin voltage is a voltage over 3.5V, the constant-current control is operated in SLOW DECAY mode. ( Sine-wave increasing direction ) STEP Setting current Setting current Coil current Chopping period Blanking Time Current mode CHARGE SLOW CHARGE SLOW ( Sine-wave decreasing direction ) STEP Setting current Coil current Setting current Chopping period Chopping period Blanking Time Current mode CHARGE SLOW Blanking Time SLOW Blanking Time SLOW Each of current modes operates with the follow sequence. The IC enters CHARGE mode at a rising edge of the chopping oscillation. ( A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1μs, regardless of the current value of the coil current (ICOIL) and set current (IREF)). After the period of the blanking time, the IC operates in CHARGE mode until ICOIL ≥ IREF. After that, the mode switches to the SLOW DECAY mode and the coil current is attenuated until the end of a chopping period. At the constand-current in SLOW DECAY mode, following to the setting current from the coil current may take time (or not follow) for the current delay attenuation. No.A1998-16/23 LV8727 FAST DECAY current control operation When FDT pin voltage is a voltage under 0.8V, the constant-current control is operated in FAST DECAY mode. (Sine-wave inxreasing direction) STEP Setting current Setting current Coil current Chopping period Blanking Time Current mode CHARGE FAST CHARGE FAST (Sine-wave decreasing direction) STEP Setting current Coil current Setting current Chopping period Blanking Time Current mode CHARGE FAST Blanking Time FAST CHARGE FAST Each of current modes operates with the follow sequence. The IC enters CHARGE mode at a rising edge of the chopping oscillation. ( A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1μs, regardless of the current value of the coil current (ICOIL) and set current (IREF)). After the period of the blanking time, the IC operates in CHARGE mode until ICOIL ≥ IREF. After that, the mode switches to the FAST DECAY mode and the coil current is attenuated until the end of a chopping period. At the constand-current control in FAST DECAY mode, following to the setting current from the coil current take short-time for the current fast attenuation, but, the current ripple value may be higher. No.A1998-17/23 LV8727 MIXED DECAY current control operation When FDT pin voltage is a voltage between 1.1V to 3.1V or OPEN, the constant-current control is operated in MIXED DECAY mode. (Sine-wave increasing direction) STEP Setting current Setting current Coil current Chopping period Blanking Time Current mode CHARGE SLOW FAST CHARGE SLOW FAST (Sine-wave decreasing direction) STEP Setting current Coil current Setting current Chopping period Blanking Time Current mode CHARGE SLOW FAST Blanking Time FAST CHARGE SLOW Each of current modes operates with the follow sequence. The IC enters CHARGE mode at a rising edge of the chopping oscillation. ( A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1μs, regardless of the current value of the coil current (ICOIL) and set current (IREF)). In a period of Blanking Time, the coil current (ICOIL) and the setting current (IREF) are compared. If an ICOIL < IREF state exists during the charge period: The IC operates in CHARGE mode until ICOIL ≥ IREF. After that, it switches to SLOW DECAY mode and then switches to FAST DECAY mode in the last approximately 1μs of the period. If no ICOIL < IREF state exists during the charge period: The IC switches to FAST DECAY mode and the coil current is attenuated with the FAST DECAY operation until the end of a chopping period. The above operation is repeated. Normally, in the sine wave increasing direction the IC operates in SLOW (+ FAST) DECAY mode, and in the sine wave decresing direction the IC operates in FAST DECAY mode until the current is attenuated and reaches the set value and the IC operates in SLOW (+ FAST) DECAY mode. No.A1998-18/23 LV8727 (13) Output short-circuit protection circuit Built-in output short-circuit protection circuit makes output to enter in stand-by mode. This function prevents the IC from damaging when the output shorts circuit by a voltage short or a ground short, etc. When output short state is detected, short-circuit detection circuit state the operating and output is once turned OFF. Subsequently, the output is turned ON again after the timer latch period ( typ. 256μs ). If the output remains in the short-circuit state, turn OFF the output, fix the output to the wait mode, and turn ON the EMO output. When output is fixed in stand-by mode by output short protection circuit, output is released the latch by setting ST = “L”. Output ON H-bridge output state Short-circuit detection state Output ON Short- Release circuit Output OFF Standby state Short-circuit Internal counter 1st counter start 1st counter 1st counter stop start 1st counter end 2nd counter start 2nd counter end No.A1998-19/23 LV8727 (15) DOWN output pin The DOWN output pin is an open-drain connection. This pin is turned ON when no rising edge of STEP between the input signals while a period determined by a capacitor between OSC2 and GND, and outputs at low levels. The open-drain output in once turned ON, is turned OFF at the next rising edge of STEP. Holding current switching time ( Tdown ) is set as shown below by a capacitor between OSC2 pin and GND. Tdown = Cosc2 х 0.4 х 109 (s) (Example) When Cosc2 = 1500pF, the STEP signal detection time is shown below. Tdown = 1500pF х 0.4 х 109 = 0.6 (s) Rotation Motor keep Rotation STEP input Tdown DOWN output OFF Low OFF By connecting circumference parts like the example of the following circuit diagram using a DOWN pin, that is a STEP signal is not inputted more than detection time, it is a DOWN output's turning on in the state of holding turning on electricity the position of a stepping motor, and setting current's falling because VREF input voltage's falls, and stopping power consumption -- it can do. R1 VREF R3 R2 DOWN (Example) When V1=5V, R1=27kΩ, R2=4.7kΩ, R3=1kΩ, the VREF input voltage is shown below. DOWN output OFF: VREF=V1×R2/(R1+R2)=0.741V DOWN output ON: VREF=V1×(R2║R3)/ (R1+(R2║R3))=0.126V No.A1998-20/23 LV8727 Application Circuit Example PGND1 OUT1A VM1 ST MD1 MD2 MD3 OE RST FR STEP OSC1 OSC2 FDT DOWN MO VREF SGND VM2 OUT2B PGND2 RF2 OUT2A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 + - Logic input - + 180pF RF1 1 - + OUT1B LV8727 Logic supply M Motor connect pin The above sample application circuit is set to the following conditions: · Constant-current setting IOUT=VREF/3/RF (Example) When is VREF=0.9V IOUT=0.9V/3/0.1Ω=3A · Chopping frequency setting Fchop=Ichop/(Cchop×Vt×2) =10µA/(180pF×0.5V×2)=55.6kHz No.A1998-21/23 LV8727 HZIP25 Heat sink attachment Heat sinks are used to lower the semiconductor device junction temperature by leading the head generated by the device to the outer environment and dissipating that heat. a. Unless otherwise specified, for power ICs with tabs and power ICs with attached heat sinks, solder must not be applied to the heat sink or tabs. b. Heat sink attachment · Use flat-head screws to attach heat sinks. · Use also washer to protect the package. · Use tightening torques in the ranges 39-59Ncm(4-6kgcm) . · If tapping screws are used, do not use screws with a diameter larger than the holes in the semiconductor device itself. · Do not make gap, dust, or other contaminants to get between the semiconductor device and the tab or heat sink. · Take care a position of via hole . · Do not allow dirt, dust, or other contaminants to get between the semiconductor device and the tab or heat sink. · Verify that there are no press burrs or screw-hole burrs on the heat sink. · Warping in heat sinks and printed circuit boards must be no more than 0.05 mm between screw holes, for either concave or convex warping. · Twisting must be limited to under 0.05 mm. · Heat sink and semiconductor device are mounted in parallel. Take care of electric or compressed air drivers · The speed of these torque wrenches should never exceed 700 rpm, and should typically be about 400 rpm. Binding head machine screw Countersunk head mashine screw Heat sink gap Via hole c. Silicone grease · Spread the silicone grease evenly when mounting heat sinks. · Recommends YG-6260 (Momentive Performance Materials Japan LLC) d. Mount · First mount the heat sink on the semiconductor device, and then mount that assembly on the printed circuit board. · When attaching a heat sink after mounting a semiconductor device into the printed circuit board, when tightening up a heat sink with the screw, the mechanical stress which is impossible to the semiconductor device and the pin doesn't hang. e. When mounting the semiconductor device to the heat sink using jigs, etc., · Take care not to allow the device to ride onto the jig or positioning dowel. · Design the jig so that no unreasonable mechanical stress is not applied to the semiconductor device. f. Heat sink screw holes · Be sure that chamfering and shear drop of heat sinks must not be larger than the diameter of screw head used. · When using nuts, do not make the heat sink hole diameters larger than the diameter of the head of the screws used. A hole diameter about 15% larger than the diameter of the screw is desirable. · When tap screws are used, be sure that the diameter of the holes in the heat sink are not too small. A diameter about 15% smaller than the diameter of the screw is desirable. g. There is a method to mount the semiconductor device to the heat sink by using a spring band. But this method is not recommended because of possible displacement due to fluctuation of the spring force with time or vibration. No.A1998-22/23 LV8727 ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1998-23/23