MC74VHC259 D

MC74VHC259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
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The MC74VHC259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation similar to
equivalent Bipolar Schottky TTL devices while maintaining CMOS low
power dissipation.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in the
mode selection table.. In the addressable latch mode, the data on Data In
is written into the addressed latch. The addressed latch follows the data
input with all non−addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state and are
unaffected by the Data or Address inputs. In the one−of−eight decoding
or demultiplexing mode, the addressed output follows the state of Data In
with all other outputs in the LOW state. In the Reset mode, all outputs are
LOW and unaffected by the address and data inputs. When operating the
VHC259 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should
only be done while in the memory mode.
The MC74VHC259 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC259 to be used to interface 5 V circuits to 3 V circuits.
• High Speed: tPD = 7.6 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V
• These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAMS
16
9
VHC259G
AWLYYWW
SOIC−16
D SUFFIX
CASE 751B
1
8
16
9
VHC
259
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
A
L, WL
Y, YY
W, WW
G or G
8
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC259DG
SOIC−16
48 Units/Rail
MC74VHC259DR2G
SOIC−16
2500 Units/Reel
TSSOP−16
96 Units/Rail
MC74VHC259DTG
MC74VHC259DTR2G TSSOP−16 2500 Units/Reel
A0
1
16
VCC
A1
2
15
RESET
A2
3
14
ENABLE
Q0
4
13
DATA IN
Q1
5
12
Q7
Q2
6
11
Q6
Q3
7
10
Q5
GND
8
9
Q4
Figure 1. Pin Assignment
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 5
1
Publication Order Number:
MC74VHC259/D
MC74VHC259
4
A0
ADDRESS
INPUTS
A1
RESET
ENABLE
5
Q0
Q1
2
6
Q2
7
9
10
Q3
Q4
Q5
3
A2
DATA IN
1
13
11
12
NONINVERTING
OUTPUTS
Q6
Q7
PIN 16 = VCC
PIN 8 = GND
15
14
Figure 2. Logic Diagram
A0
1
A1
2
A2
3
BIN/OCT
1
0
2
1
4
2
4
5
6
7
3
8
4
13
ID
5
14
EN
6
15
R
10
11
12
7
Q0
A0
1
Q1
A1
2
Q2
A2
3
DMUX
0
0
G
0
7
2
1
2
Q3
3
Q4
4
13
Q5
14
Q6
15
Q7
ID
5
EN
6
R
7
4
5
6
7
8
10
11
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Figure 3. IEC Logic Symbol
LATCH SELECTION TABLE
Address Inputs
MODE SELECTION TABLE
Enable
Reset
Mode
C
B
A
Latch
Addressed
L
H
Addressable Latch
L
L
L
Q0
H
H
Memory
L
L
8−Line Demultiplexer
H
L
Reset
L
L
H
Q1
L
H
L
Q2
L
H
H
Q3
H
L
L
Q4
H
L
H
Q5
H
H
L
Q6
H
H
H
Q7
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2
MC74VHC259
DATA INPUT
13
D
D
D
D
4
5
6
7
Q0
Q1
Q2
Q3
A0
ADDRESS
INPUTS
3 TO 8
DECODER
A1
D
9
Q4
A2
D
ENABLE
Q5
14
D
D
RESET
10
15
Figure 4. Expanded Logic Diagram
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3
11
12
Q6
Q7
MC74VHC259
MAXIMUM RATINGS
Value
Unit
VCC
Symbol
Positive DC Supply Voltage
Parameter
−0.5 to +7.0
V
VIN
Digital Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
$20
mA
IOUT
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
$75
mA
PD
Power Dissipation in Still Air
200
180
mW
TSTG
Storage Temperature Range
−65 to +150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 1.)
Machine Model (Note 2.)
Charged Device Model (Note 3.)
>2000
>200
>2000
V
ILATCH−UP
Latch−Up Performance
Above VCC and Below GND at 125°C (Note 4.)
$300
mA
qJA
Thermal Resistance, Junction to Ambient
143
164
°C/W
SOIC Package
TSSOP
SOIC Package
TSSOP
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
VIN
DC Input Voltage
0
5.5
V
VOUT
DC Output Voltage
0
VCC
V
TA
Operating Temperature Range, all Package Types
−55
125
°C
tr, tf
Input Rise or Fall Time
0
20
ns/V
VCC = 3.3 V + 0.3 V
VCC = 5.0 V + 0.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
TJ = 90 ° C
1,032,200
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 5. Failure Rate vs. Time Junction Temperature
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4
MC74VHC259
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Condition
Min
1.5
VCCX 0.7
VIH
Minimum High−Level
Input Voltage
2.0
3.0to 5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0to 5.5
VOH
Maximum High−Level
Output Voltage
VIN = VIH or VIL
IOH = −50 μA
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
VOL
Maximum Low−Level
Output Voltage
−55°C ≤ TA ≤ 125°C
TA = 25°C
(V)
Typ
Max
Min
Max
1.5
VCCX 0.7
0.5
VCCX 0.3
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
V
0.5
VCCX 0.3
2.0
3.0
4.5
Unit
1.9
2.9
4.4
V
V
V
VIN = VIH or VIL
IOL = 50 μA
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
2.48
3.8
2.0
3.0
4.5
0.0
0.0
0.0
3.0
4.5
0.36
0.36
0.1
0.1
0.1
0.1
0.1
0.1
V
V
0.44
0.44
IIN
Input Leakage Current
VIN = 5.5 V or GND
0 to 5.5
±0.1
±1.0
μA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
4.0
40.0
μA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tPHL
CIN
Typ
Max
Min
Max
Min
Max
Unit
Maximum
Propagation Delay,
Data to Output
(Figures 6 and 11)
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
ns
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
Maximum
Propagation Delay,
Address Select to
Output
(Figures 7 and 11)
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
Maximum
Propagation Delay,
Enable to Output
(Figures 8 and 11)
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
Maximum
Propagation Delay,
Reset to Output
(Figures 9 and 11)
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
6
10
Parameter
Test Conditions
Min
−55°C ≤ TA ≤
125°C
TA ≤ 85°C
TA = 25°C
Maximum Input
Capacitance
10
10
ns
ns
ns
pF
Typical @ 25°C, VCC = 5.0V
CPD
30
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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5
MC74VHC259
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TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = ≤ 85°C
TA = 25°C
Min
Minimum Pulse Width, Reset or Enable
(Figure 10)
VCC = 3.3 ± 0.3V
5.0
5.5
5.5
VCC = 5.0 ± 0.5V
5.0
5.5
5.5
tsu
Minimum Setup Time, Address or Data to Enable
(Figure 10)
VCC = 3.3 ± 0.3V
4.5
4.5
4.5
VCC = 5.0 ± 0.5V
3.0
3.0
3.0
th
Minimum Hold Time, Enable to Address or Data
(Figure 8 or 9)
VCC = 3.3 ± 0.3V
2.0
2.0
2.0
VCC = 5.0 ± 0.5V
2.0
2.0
2.0
Maximum Input, Rise and Fall Times
(Figure 6)
VCC = 3.3 ± 0.3V
400
300
300
VCC = 5.0 ± 0.5V
200
100
100
tw
tr, tf
Parameter
Typ
Max
Min
TA = ≤ 125°C
Test Conditions
Symbol
Max
Min
Max
Unit
ns
ns
ns
ns
VCC
tr
DATA IN
tf
VCC
50%
DATA IN
GND
ADDRESS
SELECT
VCC
50%
GND
GND
tPLH
tPHL
VCC
50%
GND
50%
tPHL
OUTPUT Q
tPHL
OUTPUT Q
50%
Figure 6. Switching Waveform
Figure 7. Switching Waveform
VCC
DATA IN
tw
VCC
GND
DATA IN
VCC
RESET
GND
tw
ENABLE
50%
50%
tw
50%
VCC
50%
GND
GND
tPHL
tPHL
tPHL
OUTPUT Q
OUTPUT Q
50%
Figure 8. Switching Waveform
DATA IN
OR
ADDRESS
SELECT
Figure 9. Switching Waveform
TEST POINT
VCC
50%
th(H)
tsu
th(H)
tsu
VCC
ENABLE
OUTPUT
GND
DEVICE
UNDER
TEST
CL*
50%
GND
*Includes all probe and jig capacitance
Figure 10. Switching Waveform
Figure 11. Test Circuit
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6
MC74VHC259
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74VHC259
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
S
V
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
0.25 (0.010)
8
1
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
SOLDERING FOOTPRINT
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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MC74VHC259/D