MC14518B D

MC14518B, MC14520B
Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS P−channel and N−channel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4−stage
counters. The counter stages are type D flip−flops, with interchangeable
Clock and Enable lines for incrementing on either the positive−going or
negative−going transition as required when cascading multiple stages.
Each counter can be cleared by applying a high level on the Reset line.
In addition, the MC14518B will count out of all undefined states within
two clock periods. These complementary MOS up counters find
primary use in multi−stage synchronous or ripple counting applications
requiring low power dissipation and/or high noise immunity.
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SOIC−16 WB
DW SUFFIX
CASE 751G
Features
•
•
•
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Internal and External Speeds
Logic Edge−Clocked Design − Incremented on Positive Transition of
Clock or Negative Transition on Enable
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1)
Parameter
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 2)
500
mW
TA
Operating Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
VDD
Vin, Vout
Iin, Iout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
CA
1
16
VDD
EA
2
15
RB
Q0A
3
14
Q3B
Q1A
4
13
Q2B
Q2A
5
12
Q1B
Q3A
6
11
Q0B
RA
7
10
EB
VSS
8
9
CB
MARKING DIAGRAM
Value
Symbol
PIN ASSIGNMENT
16
145xxB
AWLYYWWG
1
xx
A
WL, L
YY, Y
WW, W
G
= 18 or 20
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
Stresses exceeding Maximum Ratings may damage the device. Maximum
ORDERING INFORMATION
Ratings are stress ratings only. Functional operation above the Recommended
See
detailed
ordering and shipping information in the package
Operating Conditions is not implied. Extended exposure to stresses above the
dimensions section on page 2 of this data sheet.
Recommended Operating Conditions may affect device reliability.
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 8
1
Publication Order Number:
MC14518B/D
MC14518B, MC14520B
BLOCK DIAGRAM
CLOCK
1
Q0
Q1
Q2
C
2
ENABLE
R
3
4
Q3
5
6
Q0
11
Q1
Q2
Q3
12
7
CLOCK
9
C
10
ENABLE
R
13
14
15
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Clock
Enable
Reset
Action
1
0
Increment Counter
0
Increment Counter
0
No Change
0
No Change
0
No Change
0
No Change
1
Q0 thru Q3 = 0
0
X
X
0
1
X
X
X = Don’t Care
ORDERING INFORMATION
Package
Shipping†
MC14518BDWG
SOIC−16 WB
(Pb−Free)
47 Units / Rail
MC14518BDWR2G
SOIC−16 WB
(Pb−Free)
1000 Units / Tape & Reel
NLV14518BDWR2G*
SOIC−16 WB
(Pb−Free)
1000 Units / Tape & Reel
MC14520BDWG
SOIC−16 WB
(Pb−Free)
47 Units / Rail
MC14520BDWR2G
SOIC−16 WB
(Pb−Free)
1000 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14518B, MC14520B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
VDD
Vdc
Min
Max
Min
Typ
(Note 3)
125_C
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
–1.7
–0.36
–0.9
–2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current (Notes 4, 5)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (0.6 mA/kHz) f + IDD
IT = (1.2 mA/kHz) f + IDD
IT = (1.7 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in μA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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3
MC14518B, MC14520B
SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25_C)
All Types
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Clock to Q/Enable to Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
Reset to Q
tPHL = (1.7 ns/pF) CL + 265 ns
tPHL = (0.66 ns/pF) CL + 117 ns
tPHL = (0.66 ns/pF) CL + 95 ns
tPHL
VDD
Min
Typ
(Note 7)
Max
5.0
10
15
−
−
−
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
−
−
−
280
115
80
560
230
160
5.0
10
15
−
−
−
330
130
90
650
230
170
tw(H)
tw(L)
5.0
10
15
200
100
70
100
50
35
−
−
−
ns
fcl
5.0
10
15
−
−
−
2.5
6.0
8.0
1.5
3.0
4.0
MHz
tTHL, tTLH
5.0
10
15
−
−
−
−
−
−
15
5
4
μs
Enable Pulse Width
tWH(E)
5.0
10
15
440
200
140
220
100
70
−
−
−
ns
Reset Pulse Width
tWH(R)
5.0
10
15
280
120
90
125
55
40
−
−
−
ns
trem
5.0
10
15
–5
15
20
– 45
– 15
–5
−
−
−
ns
Clock Pulse Width
Clock Pulse Frequency
Clock or Enable Rise and Fall Time
Reset Removal Time
ns
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
500 μF
PULSE
GENERATOR
ID
0.01 μF
CERAMIC
C Q0
Q1
Q2
E Q3
R
CL
CL
CL
CL
VSS
20 ns
20 ns
50%
90%
10%
VARIABLE
WIDTH
VSS
Figure 1. Power Dissipation Test Circuit and Waveform
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4
MC14518B, MC14520B
20 ns
VDD
PULSE
GENERATOR
C
20 ns
90%
50%
10%
CLOCK
INPUT
Q0
tWH
Q1
E
R
Q2
Q3
CL
VSS
CL
CL
tPHL
90%
tf
Figure 2. Switching Time Test Circuit and Waveforms
1
2 3
4 5
6
7 8
9 10 11 12 13 14 15 16 17 18
1
2 3
4 5
6
7 8
9 0 1
6
7 8
9 0
1
2 3
4 5
6
7 8
9 10 11 12 13 14 15 0
1 2
3
CLOCK
ENABLE
RESET
2 3
4 5
Q0
Q1
Q2
Q3
Q0
MC14520B
50%
10%
Q
tr
MC14518B
VSS
tWL
tPLH
CL
VDD
Q1
Q2
Q3
Figure 3. Timing Diagram
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5
4
MC14518B, MC14520B
Q0
D
C
R
Q1
Q
D
Q
C
R
Q2
Q
D
Q
C
R
Q3
Q
D
Q
C
Q
R
Q
RESET
ENABLE
CLOCK
Figure 4. Decade Counter (MC14518B) Logic Diagram
(1/2 of Device Shown)
Q0
D
C
R
Q1
Q
D
Q
C
R
Q2
Q
D
Q
C
R
Q
D
Q
C
RESET
ENABLE
CLOCK
Figure 5. Binary Counter (MC14520B) Logic Diagram
(1/2 of Device Shown)
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6
Q3
Q
R
Q
MC14518B, MC14520B
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G−03
ISSUE D
A
D
9
1
8
h X 45 _
E
0.25
H
8X
M
B
M
16
q
16X
M
B
B
T A
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
S
B
S
L
A
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
14X
C
A1
e
T
SEATING
PLANE
SOLDERING FOOTPRINT
16X
0.58
11.00
1
16X
1.27
PITCH
1.62
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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MC14518B/D