NB4L7210 D

NB4L7210
2.5V/3.3V Differential 2x10
Crosspoint Clock Driver
with SDI Programmable
Output Selects
www.onsemi.com
The NB4L7210 is a Clock input crosspoint fanout distribution
device selecting between one of two input clocks on each of the 10
differential output pairs. A 10 Bit Serial Data Interface programs each
output MUX to asynchronously select either Input clock.
CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or
LVDS signal levels and incorporate an internal 50 ohms on die
termination resistors. SCLK, SDATA, and SLOAD input can accept
single ended LVPECL, CML, LVCMOS, LVTTL signals levels.
SCLK and SDATA inputs operate up to 20 MHz. SLOAD input
loads and latches the output select data. The SDATAOUT pin permits
cascading multiple devices. Outputs are optimized for minimal
output−to−output skew and low jitter.
MARKING
DIAGRAM*
52
1
1
QFN52
MN SUFFIX
CASE 485M
NB4L7210
A
WL
YY
WW
G
Features
•
•
•
•
•
•
•
•
•
•
•
Typical Input Clock Frequency > 2 GHz
200 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Output to Output Skew 150 ps
Additive RMS Phase Jitter of 0.2 ps
Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
Differential LVPECL Output Level (Typ 700 mV Peak−to−Peak)
Low Profile 8x8 mm, 52 QFN Package
10GE WAN: 155.52 MHz / 622.08 MHz
10GE LAN: 161.1328 MHz
These are Pb−Free Devices*
52
NB4L
7210
AWLYYWWG
= Device Code
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0b
VTCLK0
CLK0
CLK0b
Q1
Q1b
VTCLK0b
Q8
VTCLK1
CLK1
CLK1b
Q8b
VTCLK1b
Q9
Q9b
VCC
VEE
SCLK
SDATA
SLOAD
SDATAOUT
Figure 1. Functional Block Diagram
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 8
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Publication Order Number:
NB4L7210/D
GND
GND
Q2
Q2
VCC2
Q1
Q1
VCC1
Q0
Q0
VCC0
VCC
SDATAOUT
NB4L7210
Exposed Pad (EP)
52 51 50 49 48 47 46 45 44 43 42 41 40
GND
1
39 VCC3
SLOAD
2
38 Q3
VTCLK0
3
37 Q3
CLK0
4
36 VCC4
35 Q4
CLK0
5
VTCLK0
6
GND
7
33 GND
VTCLK1
8
32 Q5
CLK1
9
31 Q5
34 Q4
NB4L7210
CLK1
10
30 VCC5
VTCLK1
11
29 Q6
SDATA
12
28 Q6
GND
13
27 VCC6
GND
GND
Q7
Q7
Q8
VCC7
Q8
VCC8
Q9
Q9
VCC
VCC9
SCLK
14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1, 7, 13, 25, 26, 33,
40, 41
GND
Supply
Negative Supply pins must be all externally connected to a power
supply to guarantee proper operation.
2
SLOAD
LVCMOS, LVTTL
Serial Load and Latch control input pin. Defaults LOW when float-
3, 6, 8, 11
VTCLK0, VTCLK0,
VTCLK1, VTCLK1
Termination−
Internal 50 Ohms Termination Resistor connection Pins. In the
differential configuration when the input termination pins are connected to the common termination voltage.
4, 9
CLK0, CLK1
Differential LVPECL,
CML, or LVDS
CLOCK Input (TRUE). If no signal is applied then the device may
be susceptible to self oscillation.
5, 10
CLK0, CLK1
Differential LVPECL,
CML, or LVDS
CLOCK Input (INVERT). If no signal is applied then the device
may be susceptible to self oscillation.
12
SDATA
LVCMOS, LVTTL
Serial Data input pin (for BITS 0:9, a “0” selects CLK1, “1” selects
CLK 0). Defaults LOW when floating open.
14
SCLK
LVCMOS, LVTTL
Serial Load Clock input pin. Defaults LOW when floating open.
15, 16, 19, 22, 27,
30, 36, 39, 44, 47,
50, 51
VCC, VCC9, VCC8,
VCC7, VCC6, VCC5,
VCC4, VCC3, VCC2,
VCC1, VCC0
Supply
17, 20, 23, 28, 31,
34, 37, 42, 45, 48
Q[9−0]
LVPECL
Output (INVERT)
18, 21, 24, 29, 32,
35, 38, 43, 46, 49
Q[9−0]
LVPECL
Output (TRUE)
52
SDATAOUT
LVCMOS, LVTTL
Exposed Pad
EP
GND
ing open.
Positive Supply pins must be all externally connected to a power
supply to guarantee proper operation.
Serial Data output pin for cascade
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat−
sinking conduit for proper thermal operation and must be connected to GND.
www.onsemi.com
2
NB4L7210
10 MUXes
SLOAD
SDATA
Output Qx
9 8 7 6 5 4 3 2 1 0
BIT
9 8 7 6 5 4 3 2 1 0
10 Bit LATCH
10 Bit SHIFT
MSB
SDATAOUT
SCLK
SDATA REGISTER DATA BIT VALUE
LSB
0 Selects CLK1 / CLK1
SDATA 10 BIT REGISTER
10 Bit SHIFT REGISTER
1 Selects CLK0 / CLK0
(B)
(C)
(A)
Figure 3. Serial Data Interface
Table 2. ATTRIBUTES
Characteristic
Value
Input Default State Resistors
None
ESD Protection
Human Body Model
Moisture Sensitivity Pb−Free Package (Note 1)
Flammability Rating
> 2 kV
QFN−52
Oxygen Index: 28 to 34
Level 1
UL 94 V−0 @ 0.125 in
Transistor Count
2027
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Power Supply
Parameter
GND = 0 V
Condition 1
6.0
V
VI
Positive Input
GND = 0 V
GND−0.3 ≤ VI ≤ VCC
V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
35
70
mA
mA
VINPP
Differential Input Voltage
2.5
V
IOUT
Output Current (Q / Q)
Continuous
Surge
25
50
mA
TA
Operating Temperature Range
QFN−52
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient) (Note 2)
0 lfpm
500 lfpm
QFN−52
QFN−52
25
19.6
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 2)
QFN−52
21
°C/W
Tsol
Wave Solder
265
°C
Pb−Free
Condition 2
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
www.onsemi.com
3
NB4L7210
Table 4. DC CHARACTERISTICS (VCC = 2.375 V to 3.6 V, VEE = 0 V, TA = −40°C to +85°C (Note 4))
Symbol
Min
Typ
Max
Unit
IEED
GND Supply Current (All Outputs Loaded)
Characteristic
110
150
200
mA
RTIN
Internal Input Termination Resistor
40
50
60
W
VOH
Output HIGH Voltage
VCC−1145
VCC−1020
VCC−895
mV
VOL
Output LOW Voltage
VCC−1945
VCC−1820
VCC−1695
mV
IIH
Input HIGH Current (VTx/VTx open)
8
150
mA
IIL
Input LOW Current (VTx/VTx open)
150
mA
0.1
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 5, 6)
Vth
Input Threshold Reference Voltage Range (Note 5)
GND +950
VCC − 150
mV
VIH
Single−Ended Input HIGH Voltage
Vth + 150
VCC
mV
VIL
Single−Ended Input LOW Voltage
GND
Vth − 150
mV
VINAMP
Single−Ended Input Amplitude
300
VCC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8)
VCMR
Input Common Mode Range
GND +950
VCC − 75
mV
VIHD
Differential Input HIGH Voltage
VCMR + 75
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCMR − 75
mV
VID
Differential Input Voltage (VIHD − VILD)
150
2400
mV
LVCMOS/LVTTL INPUTS (SCLK, SDATA, SLOAD)
VIH
Input HIGH Voltage
2.0
VCC
V
VIL
Input LOW Voltage
GND
0.8
V
LVCMOS/LVTTL OUTPUTS (SDATAOUT)
VOH
Output HIGH Voltage @ IOH = −1.0 mA, RL = 20 kW to GND
VOL
Output LOW Voltage @ IOL = 1.0 mA, RL = 20 kW to GND
2.0
3.2
0.25
V
0.5
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. Input and Output parameters vary 1:1 with VCC. Outputs loaded with 50 W to VCC − 2.0 V (See Figure 16) except SDATAOUT.
5. Vth is applied to the complementary input when operating in single−ended mode.
www.onsemi.com
4
NB4L7210
Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 6))
Symbol
Characteristic
Min
Typ
Max
Unit
fin = 100 MHz
fin = 1 GHz
650
530
800
790
875
960
mV
CLK/CLK to Qx/Qx (Note 7)
SCLK to SDATAOUT Measured at 1.5 V
610
6.5
725
20
875
30.8
ps
ns
−5
0
0
2
5
20
10
35
200
ps
SDATA to SCLK Measured at 1.5 V
SCLK to SLOAD+ Measured at 1.5 V
−150
1000
−115
SDATA to SCLK
325
345
SLOAD
2.0
VOUTPP
Output Voltage Amplitude @ VINPPmin (See Figure 9)
tPLH,
tPHL
Propagation Delay to (See Figure 9)
tSKEW
Duty Cycle Skew (Note 8)
Within −Device Skew
Device to Device Skew (Note 8)
ts
Setup Time
ps
Th
Hold Time
PWmin
Minimum Pulse Width
tJIT(Ø)
RMS Phase Jitter, Integration Range 12 KHz to 20 MHz
365
ps
ns
fs
@155.52 MHz
@ 622.08 MHz
tJITTER
TIE Rj (10,000 Cycles)
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration, measured Single−ended on each input)
tr , tf
Output Risetime and Falltime
See Fig 10
See Fig 11
@155.52 MHz
@ 622.08 MHz
Crosstalk RMS Jitter RMS (1000 Cycles) (Note 9)
Qx/Qx (20% to 80%)
SDATAOUT (0.8 V − 2.0 V)
1.7
0.63
3.9
ps
150
750
1200
mV
120
0.88
185
10
260
15
ps
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Measured by forcing VINPP (Typ 750 mVPP) from a 50% duty cycle clock source. Q/Q Outputs loaded with 50 W to VCC − 2.0 V (See Figure 16).
SCLK, SDATA and SLOAD at LOW SDATAOUT loaded 20 kW and 15 pF to GND.
7. Measured from the input pair crosspoint to each single output pair crosspoint.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+.
9. 155.52 MHz @ 750 mVPP input on measured output, 161.13 MHz @ 850 mVPP input on all other others.
www.onsemi.com
5
NB4L7210
Programming Application Information for the SDI
As shown in Figure 4, the SLOAD pulse Low to HIGH
level transition transfers the data from the SHIFT register to
the LATCH register. The SLOAD Pulse HIGH to LOW level
transition will lock the new MUX select data values into the
LATCH register. An initial program load cycle is
recommended since the 10 bit register will power−up in a
random state.
SDATAOUT pin outputs the shift register LSB bit with
each SCLK rising edge for porting to the SCLK of the next
device in a cascade interconnect only. Cascade operation
will require a complete data register loading of all devices
to purge the shift registers of power up random state bits.
To use the serial port, the SCLK signal samples the
information on the SDATA line and indexes the data into a
10 bit shift register (See Figure 3). The register shifts once
per rising edge of the SCLK input. The serial input SDATA
bits must each meet setup and hold timing to their respective
SCLK rising edge as specified in the AC Characteristics
section of this document. (See Figure 4)
The SDATA Least Significant Bit (LSB), D0, is indexed
in first and the Most Least Significant Bit (LSB), D9, is
indexed in last. A Pulse on the SLOAD pin after the SHIFT
register is fully indexed (10 clocks) will load and lock the
MUX select data values into the Latch register (See Figure
4). For each MUX (Output Q[0:9], a “0” bit value selects
CLK1 and a “1” bit value selects CLK 0 (see Figure 3, “C”).
SDATA to SCLOCK
ts
th
SCLK
SDATA
C0
D0
C1
C2
C3
C4
D1
D2
D3
D4
C5
D5
C6
D6
C7
D7
C9
C8
D9
D8
MSB
LSB
SLOAD
SDATA to SLOAD
ts
PWmin
Figure 4. Serial Interface Timing Diagram
www.onsemi.com
6
NB4L7210
VIH
CLK
Qx
CLK
Qx
Vth
VIL
Vth
Figure 5. Differential Input Driven Single−Ended Vth Schema
VCC
Vthmax
VIHmax
VILmax
CLKx
Vth
VIHmin
Vthmin
VILmin
CLKx
GND
Figure 6. Differential Input Driven Single−Ended Vth Diagram
CLK
Q
CLK
Q
Figure 7. Differential Inputs Driven Differentially
VCC
VIH(MAX)
VIL
VIH
VINPP = VIHD − VILD
VCMR
VIL
VIH
VIL(MIN)
GND
Figure 8. VCMR Diagram
CLK
VINPP = VIH − VIL
CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 9. AC Reference Measurement
www.onsemi.com
7
NB4L7210
Figure 10. With conditions of an Input (source) noise floor below the NB4L7210 device noise floor, additive Phase
Noise with a 155.52 MHz Carrier (Agilent 8665A) is revealed. Note near zero additive Phase Noise below 100 kHz
offset. From 100 kHz to 20 MHz additive (residual) integrated phase noise Jitter is about 200 fs RMS.
Figure 11. With conditions of an Input (source) noise floor below the NB4L7210 device noise floor, additive Phase
Noise with a 622.08 MHz Carrier (Agilent 8665A) is revealed. Note near zero additive Phase Noise below 50 kHz
offset. From 50 kHz to 20 MHz additive (residual) integrated phase noise Jitter is about 200 fs RMS.
www.onsemi.com
8
NB4L7210
VCC
VCC
CLK
Z = 50 W
LVTTL/
LVCMOS
Driver
50 W
VTCLK
No Connect
NB4L7210
No Connect
VREF
50 W
VTCLK
Recommended VREF Values
VREF
CLK
60 pF
LVCMOS VCC − VEE
2
VEE
VCC
LVTTL
Figure 12. LVCMOS/LVTTL to NB4L7210 Receiver Interface
VCC
VCC
CLK
Z = 50 W
VTCLK
LVPECL
Driver
NB4L7210
VTCLK
Recommended RT Values
VCC
50 W
Z = 50 W
RT
3.3 V 120 W
2.5 V
50 W
RT
CLK
RT
50 W
VEE
VEE
VEE
Figure 13. LVPECL to NB4L7210 Receiver Interface
VCC
VCC
50 W
50 W
Q
Z = 50 W
CML Driver
VCC
VCC
CLK
VTCLK
50 W
VTCLK
50 W
Z = 50 W
Q
CLK
VEE
VEE
Figure 14. CML to NB4L7210 Interface
www.onsemi.com
9
NB4L7210
1.5 V
NB4L7210
VCC
VCC
CLK
Z = 50 W
VTCLK
LVDS
Driver
50 W
NB4L7210
VTCLK
50 W
Z = 50 W
CLK
VEE
VEE
Figure 15. LVDS to NB4L7210 Receiver Interface
Q
Zo = 50 W
D
Receiver
NB4L7210
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 16. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
NB4L7210MNG
QFN−52
(Pb−Free)
46 Units / Rail
NB4L7210MNTXG
QFN−52
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
10
NB4L7210
PACKAGE DIMENSIONS
QFN52 8x8, 0.5P
CASE 485M
ISSUE C
D
PIN ONE
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
B
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
K
L
E
2X
0.15
C
2X
0.15 C
A2
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.60
0.80
0.20 REF
0.18
0.30
8.00 BSC
6.50
6.80
8.00 BSC
6.50
6.80
0.50 BSC
0.20
--0.30
0.50
0.10 C
A
0.08 C
A3
A1
RECOMMENDED
SOLDERING FOOTPRINT
REF
SEATING PLANE
C
D2
14
52 X
L
8.30
52X
26
0.62
6.75
27
13
E2
6.75
39
1
52 X
K
8.30
52
40
e
52 X
b
NOTE 3
0.10 C A B
PKG
OUTLINE
0.05 C
0.50
PITCH
52X
0.30
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB4L7210/D