NBSG111 2.5V/3.3VSiGe Differential 1:10 Clock/Data Driver with RSECL* Outputs *Reduced Swing ECL http://onsemi.com The NBSG111 is a 1-to-10 differential clock/data driver. The device is functionally equivalent to the LVEP111 device with much higher bandwidth and lower EMI capabilities. Inputs incorporate internal 50 termination resistors (input to VT pad) and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. The Q[0:9] / Q[0:9] outputs have a differential synchronous enable (EN/EN) pin. The synchronous enable pin is used to avoid a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of selected clock (CLK0/CLK0 or CLK1/CLK1), therefore all associated specification limits are referenced to the negative edge of the selected clock input. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used for single-ended NECL or PECL inputs and the VMM pin is used for LVCMOS inputs. For single- ended input operation, the unused differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. • Maximum Input Clock Frequency > 6 GHz Typical • • • • • • Maximum Input Data Rate > 6 Gb/s Typical 300 ps Typical Propagation Delay MARKING DIAGRAM* SG 111 LYW FCBGA-49 BA SUFFIX CASE 489A SG111 L Y W *For further details, refer to Application Note AND8002/D ORDERING INFORMATION Device Package NBSG111BA 8x8 mm FCBGA-49 100 Units/Tray NBSG111BAR2 8x8 mm FCBGA-49 500/Tape & Reel 60 ps Typical Rise and Fall Times RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Differential Output 50 Internal Input Termination Resistors = Device Code = Wafer Lot = Year = Work Week Board NBSG111BAEVB Shipping Description NBSG111BA Evaluation Board • • Compatible with Existing 2.5 V/3.3 V LVEP and EP Devices • VBB and VMM Reference Voltage Output Semiconductor Components Industries, LLC, 2003 May, 2003 - Rev. 7 1 Publication Order Number: NBSG111/D NBSG111 1 2 3 4 5 6 7 A VEE Q9 Q9 Q8 Q8 Q7 VEE B Q0 VMM CLK1 CLK1 VCC NC Q7 C Q0 VEE VTCLK1 VTCLK1 VTSEL SEL Q6 D Q1 EN VTEN VCC VTSEL SEL Q6 E Q1 EN VTEN VTCLK0 VTCLK0 VEE Q5 F Q2 NC VCC CLK0 CLK0 VBB Q5 G VEE Q2 Q3 Q3 Q4 Q4 VEE Figure 1. BGA-49 Pinout (Top View) http://onsemi.com 2 NBSG111 Table 1. Pin Description Pin Name I/O Description A1,A7,G1,G7,C2,E6 VEE - Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. F3,D4,B5 VCC - Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. B2 VMM - LVCMOS Reference Voltage Output (VCC - VEE) / 2. F6 VBB - ECL Reference Voltage Output E4 VTCLK0 - Internal 50 Termination Pin for CLK0. See Table 4. (Note 1) F4 CLK0 ECL, CML, LVCMOS, LVDS, LVTTL Input E5 VTCLK0 - F5 CLK0 ECL, CML, LVCMOS, LVDS, LVTTL Input C4 VTCLK1 - B4 CLK1 ECL, CML, LVCMOS, LVDS, LVTTL Input C3 VTCLK1 - B3 CLK1 ECL, CML, LVCMOS, LVDS, LVTTL Input B1,D1,F1,G3,G5,F7, D7,B7,A5,A3 Q[0:9] RSECL Output Noninverted Differential Outputs [0:9]. Typically Terminated with 50 to VTT = VCC - 1.5 V C1,E1,G2,G4,G6,E7, C7,A6,A4,A2 Q[0:9] RSECL Output Inverted Differential Outputs [0:9]. Typically Terminated with 50 to VTT = VCC - 1.5 V D5 VTSEL - D6 SEL ECL, CML, LVCMOS, LVDS, LVTTL Input C5 VTSEL - C6 SEL ECL, CML, LVCMOS, LVDS, LVTTL Input D3 VTEN - D2 EN ECL, CML, LVCMOS, LVDS, LVTTL Input E3 VTEN - E2 EN ECL, CML, LVCMOS, LVDS, LVTTL Input F2,B6 NC - Noninverted Differential Input CLK0. Internal 75 k to VEE. Internal 50 Termination Pin for CLK0. See Table 4. (Note 1) Inverted Differential Input CLK0. Internal 75 k to VEE and 36.5 k to VCC. Internal 50 Termination Pin 1. See Table 4. (Note 1) Noninverted Differential Input CLK1. Internal 75 k to VEE. Internal 50 Termination Pin for CLK1. See Table 4. (Note 1) Inverted Differential Input CLK1. Internal 75 k to VEE and 36.5 k to VCC. Internal 50 Termination Pin for SEL. See Table 4. (Note 1) Noninverted Differential Select Logic Input. Internal 75 k to VEE. Internal 50 Termination Pin for SEL. See Table 4. (Note 1) Inverted Differential Select Logic Input. Internal 75 k to VEE and 36.5 k to VCC. Internal 50 Termination Pin for EN. See Table 4. (Note 1) Noninverted Differential Output Enable Pin. Internal 75 k to VEE. Internal 50 termination Pin for EN. See Table 4. (Note 1) Inverted Differential Output Enable Pin. Internal 75 k to VEE and 36.5 k to VCC. No Connect. The NC Pins are Electrically Connected to the Die and ”MUST BE” Left Open. 1. In the differential configuration when the input termination pins (VTCLK, VTDCLK) are connected to a common termination voltage and if no signal is applied, then the device will be susceptible to self-oscillation. http://onsemi.com 3 NBSG111 Table 2. FUNCTION TABLE SEL EN Active Input L L H H L H L H Disabled Outputs CLK0, CLK0 Disabled Outputs CLK1, CLK1 2. SEL/EN are the inverse of SEL/EN unless specified otherwise. Q0 (B1) Q0 (C1) Q1 (D1) Q1 (E1) (C5) VTSEL (C6) SEL Q2 (F1) R1 RTIN Q2 (G2) R2 Q3 (G3) (E4) VTCLK0 (F4) CLK0 R2 (F5) CLK0 (E5) VTCLK0 RTIN Q3 (G4) (D3) VTEN RTIN RTIN (D2) EN R1 Q4 (G5) R2 0 R2 Q4 (G6) SYNC Q5 (F7) (B4) CLK1 (C4) VTCLK1 (B3) CLK1 (C3) VTCLK1 RTIN R2 RTIN R1 R2 R1 (E2) EN (E3) VTEN (D6) SEL (D5) VTSEL Q5 (E7) 1 RTIN R2 Q6 (D7) RTIN R2 Q6 (C7) (F6) VBB Q7 (B7) (A1, A7, G1, G7) VEE Q7 (A6) Q8 (A5) Q8 (A4) (B5, D4, F3) VCC Q9 (A3) (B2) VMM Q9 (A2) Figure 2. Logic Diagram Table 3. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL to VCC LVDS Connect VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Together AC-COUPLED Bias VTCLK0, VTCLK1, VTEN, VTSEL and VTCLK0, VTCLK1, VTEN, VTSEL Inputs within Common Mode Range (VIHCMR) RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS See Text on Page 1. Unused Differential Input Switching Voltage Reference Range is from VEE + 1125 mV to VCC - 75 mV http://onsemi.com 4 NBSG111 Table 4. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor, R2 (CLK0, CLK0, CLK1, CLK1, SEL, SEL, EN, EN) 75 k Internal Input Pullup Resistor, R1 (CLK0, CLK1, SEL, EN) 36.5 k ESD Protection > 2 kV > 100 V > 1 kV Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 3) Flammability Rating Level 3 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in Transistor Count 479 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS (Note 4) Parameter Rating Units 3.6 V 3.6 -3.6 V V -3.6 V 2.8 |VCC - VEE| V V Continuous Surge 25 50 mA mA Static Surge 45 80 mA mA VBB Sink/Source 1 mA IMM VMM Sink/Source 1 mA TA Operating Temperature Range -40 to +70 °C Tstg Storage Temperature Range -65 to +150 °C JA Thermal Resistance (Junction-to-Ambient) (Note 5) 0 LFPM 500 LFPM 49 FCBGA 49 FCBGA 67 57 °C/W °C/W JC Thermal Resistance (Junction-to-Case) 2S2P (Note 5) 49 FCBGA 2 to 4 °C/W Tsol Wave Solder < 15 sec. 225 °C Symbol Condition 1 VCC Positive Power Supply VEE = 0 V VI Positive Input Negative Input VEE = 0 V VCC = 0 V VEE Negative Power Supply VCC = 0 V VINPP Differential Input Voltage |CLK - CLK| VCC - VEE 2.8 V VCC - VEE 2.8 V IOUT Output Current IIN Input Current Through RT (50 Resistor) IBB 4. Maximum Ratings are those values beyond which device damage may occur. 5. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). http://onsemi.com 5 Condition 2 VI VCC VI VEE NBSG111 Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 6) -40 °C Symbol Characteristic 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 100 70 85 100 70 85 100 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 7) 1490 1540 1590 1510 1560 1610 1520 1570 1620 mV VOUTPP Output Voltage Amplitude 300 370 450 300 370 450 300 370 450 mV VIH Input HIGH Voltage (Single-Ended) (Notes 9 and 10) VTHR + 75 VCC 1000* VCC VTHR + 75 VCC 1000* VCC VTHR + 75 VCC 1000* VCC mV VIL Input LOW Voltage (Single-Ended) (Notes 9 and 11) VIH 2500 VCC 1400* VTHR - 75 VIH 2500 VCC 1400* VTHR - 75 VIH 2500 VCC 1400* VTHR - 75 mV VBB PECL Output Voltage Reference 1080 1140 1200 1080 1140 1200 1080 1140 1200 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 8) 2.5 1.2 2.5 1.2 2.5 V VMM LVCMOS Output Voltage Reference (VCC - VEE) / 2 1.2 mV 1100 1250 1400 1100 1250 1400 1100 1250 1400 45 50 55 45 50 55 45 50 55 RTIN Internal Input Termination Resistor IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 100 25 100 25 100 A Table 7. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 12) -40 °C Symbol Characteristic 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Unit 70 85 100 70 85 100 70 85 100 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 7) 2290 2340 2390 2310 2360 2410 2320 2370 2420 mV VOUTPP Output Voltage Amplitude 300 370 450 300 370 450 300 370 450 mV VIH Input HIGH Voltage (Single-Ended) (Notes 9 and 10) VTHR + 75 VCC 1000* VCC VTHR + 75 VCC 1000* VCC VTHR + 75 VCC 1000* VCC mV VIL Input LOW Voltage (Single-Ended) (Notes 9 and 11) VIH 2500 VCC 1400* VTHR - 75 VIH 2500 VCC 1400* VTHR - 75 VIH 2500 VCC 1400* VTHR - 75 mV VBB PECL Output Voltage Reference 1880 1940 2000 1880 1940 2000 1880 1940 2000 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 8) 3.3 1.2 3.3 1.2 3.3 V VMM LVCMOS Output Voltage Reference (VCC - VEE)/2 1.2 mV 1500 1650 1800 1500 1650 1800 1500 1650 1800 45 50 55 45 50 55 45 50 55 RTIN Internal Input Termination Resistor IIH Input HIGH Current (@ VIH) 30 100 30 100 30 100 A IIL Input LOW Current (@ VIL) 25 100 25 100 25 100 A NOTE: SiGe circuits are designed to meet the DC specifications shown in the above tables after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 7. All outputs loaded with 50 to VCC - 1.5 V. VOH/VOL measured at VIH/VIL (Typical). 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 9. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR - 75 mV. 10. VIH cannot exceed VCC. 11. VIL always VEE. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. *Typicals used for testing purposes. http://onsemi.com 6 NBSG111 Table 8. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 13) -40 °C Symbol Characteristic 25°C 70°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 70 85 100 70 85 100 70 85 100 mA VOH Output HIGH Voltage (Note 14) -1010 -960 -910 -990 -940 -890 -980 -930 -880 mV VOUTPP Output Voltage Amplitude 300 370 450 300 370 450 300 370 450 mV VIH Input HIGH Voltage (Single-Ended) (Notes 16 and 17) VTHR + 75 VCC 1000* VCC VTHR + 75 VCC 1000* VCC VTHR + 75 VCC 1000* VCC mV VIL Input LOW Voltage (Single-Ended) (Notes 16 and 18) VIH 2500 VCC 1400* VTHR - 75 VIH 2500 VCC 1400* VTHR - 75 VIH 2500 VCC 1400* VTHR - 75 mV VBB NECL Output Voltage Reference -1420 -1360 -1300 -1420 -1360 -1300 -1420 -1360 -1300 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) VMM LVCMOS Output Voltage Reference (VCC - VEE)/2 (Note 19) RTIN Internal Input Termination Resistor IIH IIL V VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 0.0 VMMT - 150 VMMT VMMT + 150 VMMT - 150 VMMT VMMT + 150 VMMT - 150 VMMT VMMT + 150 mV 45 50 55 45 50 55 45 50 55 Input HIGH Current (@ VIH) 30 100 30 100 30 100 A Input LOW Current (@ VIL) 25 100 25 100 25 100 A NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 13. Input and output parameters vary 1:1 with VCC. 14. All outputs loaded with 50 to VCC - 1.5 V. VOH/VOL measured at VIH/VIL (Typical). 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 16. VTHR is the voltage applied to the complementary input, typically VBB or VMM. VTHR(MIN) = VIHCMR + 75 mV. VTHR(MAX) = VIHCMR - 75 mV. 17. VIH cannot exceed VCC. 18. VIL always VEE. 19. VMM Typical = |VCC - VEE| / 2 + VEE = VMMT. *Typicals used for testing purposes. http://onsemi.com 7 NBSG111 Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40 °C Symbol Characteristic fin < 3 GHz fin = 5.5 GHz 25°C Min Typ Max 320 180 420 250 250 430 400 300 550 450 350 700 500 2 5 15 15 20 85 70°C Min Typ Max 300 150 400 220 250 430 400 300 550 450 350 700 500 2 5 15 15 20 85 Min Typ Max 300 100 400 200 250 430 400 300 600 480 350 750 550 ps 2 5 15 15 20 85 ps Unit VOUTPP Output Voltage Amplitude (See Figure 3) (Note 20) mV tPLH, tPHL Propagation Delay to Output Differential Output Enable Clock Select tSKEW Duty Cycle Skew (Note 21) Within-Device Skew (Note 22) Device-to-Device Skew (Note 23) tS Setup Time to CLK (EN to Selected CLK0:1) 110 70 110 70 115 80 ps tH Hold Time (EN to Selected CLK0:1) 110 70 110 70 115 80 ps tJITTER RMS Random Clock Jitter(Figure 3) (Note 25) Peak-to-Peak Data Dependent Jitter (Note 26) ps fin = 5 GHz 0.5 2.0 0.5 fin = 5 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 24) tr tf Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q 2.0 0.5 2.0 14 75 2600 75 80 40 2600 75 80 40 2600 mV ps 40 60 60 60 80 20. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC - 1.5 V. Input edge rates 40 ps (20% - 80%). 21. tSKEW = |tPLH - tPHL| for a nominal 50% differential clock input waveform (Figure 4). 22. Within-Device skew is measured between outputs under identical transitions and conditions on any one device. 23. Device-to-Device skew for identical transitions at identical VCC levels. 24. VINPP (MAX) cannot exceed VCC - VEE (applicable only when VCC -VEE 2600 mV). 25. Additive RMS jitter with 50% duty cycle clock signal at 5 GHz. 26. Additive Peak-to-Peak jitter with input NRZ data at PRBS 231-1 at 5 Gb/s. http://onsemi.com 8 NBSG111 10.0 9.0 8.0 Q AMP (mV) 450 7.0 6.0 3.3 V 350 5.0 4.0 RMS JITTER (ps) OUTPUT VOLTAGE AMPLITUDE (mV) 550 2.5 V 3.0 250 2.0 RMS JITTER (ps) 1.0 150 1 2 3 4 5 6 0.0 INPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical) CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH Figure 4. AC Reference Measurement Q Z = 50 D Receiver Device Driver Device Q Z = 50 D 50 50 V TT VTT = VCC - 1.5 V Figure 5. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices) http://onsemi.com 9 NBSG111 PACKAGE DIMENSIONS FCBGA-49 BA SUFFIX PLASTIC 8x8 mm (1.0 mm pitch) BGA FLIP CHIP PACKAGE CASE 489A-02 ISSUE A A NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M−1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE C. 4. DATUM C (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 6. 489A−01 OBSOLETE, NEW STANDARD 489A−02. A D B ÉÉ ÉÉ A2 TERMINAL A1 CORNER Z E DIM A A1 A2 b D D1 E E1 e Z 4X DETAIL A 0.15 C D1 FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA e NOTE 5 A B e E1 49 X 0.20 C b NOTE 3 C 0.15 M C A B D 0.08 M C E NOTE 4 0.12 C G 6 5 4 3 2 C SEATING PLANE F 7 MILLIMETERS MIN MAX −−− 1.40 0.3 0.5 0.91 REF 0.40 0.60 8.00 BSC 6.00 BSC 8.00 BSC 6.00 BSC 1.00 BSC A1 49 X 1 DETAIL A (ROTATED 90 C.W.) VIEW Z-Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 10 NBSG111/D