NB4L858M 2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB4L858M is a high−bandwidth low voltage fully differential dual 2 x 2 crosspoint switch with CML outputs that is suitable for applications such as SDH/SONET DWDM and high speed switching applications. Design technique minimizes jitter accumulation, crosstalk, and signal skew which make this device ideal for loop−through and protection channel switching application. Each 2 x 2 crosspoint switch can fan out and/or multiplex up to 3 Gb/s data and 3 GHz clock signals. Differential inputs incorporate a pair of internal 50 W termination resistors in a center−tapped configuration (VTDx Pins) and can accept LVPECL (Positive ECL) or CML input signal without any external component. This feature provides transmission line termination on−chip, at the receiver end, eliminating external components. Differential 16 mA CML output provides matching internal 50 W terminations, and 400 mV output swings when externally terminated, 50 W to VCC. The SELECT inputs are single−ended and can be driven with either LVCMOS or LVTTL input levels. The device is housed in a low profile 7 x 7 mm 32−pin LQFP package. LQFP−32 FA SUFFIX CASE 873A A WL, L YY, Y WW, W G • 32 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. SELA0 0 DA0 VTDA0 50W 50W QA0 A0 DA0 QA0 1 Features • • • • • • • • • NB4L 858M AWLYYWW Maximum Input Clock Frequency 3 GHz Maximum Input Data Frequency 3 Gb/s 350 ps Typical Propagation Delay 80 ps Typical Rise and Fall Times 12 ps Channel to Channel Skew 0.5 ps RMS Jitter 5 ps Deterministic Jitter @ 2.5 Gb/s Operating Range: VCC = 2.3V to 3.6 V with GND = 0 V CML Output Level (400 mV Peak−to−Peak Output), Differential Output These are Pb−Free Devices SELA1 0 DA1 VTDA1 50W 50W A1 QA1 QA1 DA1 1 SELB0 0 DB0 VTDB0 50W 50W QB0 B0 QB0 DB0 1 SELB1 0 DB1 VTDB1 50W 50W B1 QB1 QB1 DB1 1 Figure 1. Functional Block Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2005 December, 2005 − Rev. 9 1 Publication Order Number: NB4L858M/D NB4L858M GND VCC QA0 QA0 24 23 22 21 VCC QA1 20 19 QA1 18 VCC 17 DA0 25 16 VCC VTDA0 26 15 QB1 DA0 27 14 QB1 SELA1 28 13 VCC 12 QB0 LQFP−32 DA1 29 VTDA1 30 11 QB0 DA1 31 10 VCC SELA0 32 9 GND 1 2 3 4 5 6 7 8 DB1 VTDB1 DB1 SELB0 DB0 VTDB0 DB0 SELB1 Figure 1. Pin Configuration (Top View) Table 1. TRUTH TABLE SELA0/SELB0 SELA1/SELB1 QA0/QB0 QA1/QB1 L L DA0/DB0 DA0/DB0 1:2 Fanout or Redundant Distribution L H DA0/DB0 DA1/DB1 Quad Repeater or Crosspoint Switch H L DA1/DB1 DA0/DB0 Quad Repeater or Crosspoint Switch H H DA1/DB1 DA1/DB1 1:2 Fanout or Redundant Distribution http://onsemi.com 2 Function NB4L858M Table 2. PIN DESCRIPTION Pin Name I/O 1 DB1 LVPECL, CML Input Description 2 VTDB1 − 3 DB1 LVPECL, CML Input 4 SELB0 LVTTL / LVCMOS 5 DB0 LVPECL, CML Input 6 VTDB0 − 7 DB0 LVPECL, CML Input 8 SELB1 LVTTL / LVCMOS 9,24 GND − Supply ground. All GND pins must be externally connected to power supply to guarantee proper operation. 10, 13, 16, 17, 20, 23 VCC − Positive Supply. All VCC pins must be externally connected to power supply to guarantee proper operation. 11 QB0 CML Output Channel B0 negative signal output. Typically terminated with 50 W resistor to VCC. 12 QB0 CML Output Channel B0 positive signal output. Typically terminated with 50 W resistor to VCC 14 QB1 CML Output Channel B1 negative signal output. Typically terminated with 50 W resistor to VCC. 15 QB1 CML Output Channel B1 positive signal output. Typically terminated with 50 W resistor to VCC. 18 QA1 CML Output Channel A1 negative signal output. Typically terminated with 50 W resistor to VCC. 19 QA1 CML Output Channel A1 positive signal output. Typically terminated with 50 W resistor to VCC. 21 QA0 CML Output Channel A0 negative signal output. Typically terminated with 50 W resistor to VCC. 22 QA0 CML Output Channel A0 positive signal output. Typically terminated with 50 W resistor to VCC. 25 DA0 LVPECL, CML Input 26 VTDA0 − 27 DA0 LVPECL, CML Input 28 SELA1 LVTTL 29 DA1 LVPECL, CML Input 30 VTDA1 − 31 DA1 LVPECL, CML Input 32 SELA0 LVTTL Channel B1 positive signal input. Internal 100 W center−tapped termination pin for channel B1. Channel B1 negative signal input. Channel B0 Output Select. See Table 1. Channel B0 positive signal input. Internal 100 W center−tapped termination pin for channel B0. Channel B0 negative signal input. Channel B1 output select. See Table 1. Channel A0 positive signal input. Internal 100 W center−tapped termination pin for channel A0. Channel A0 negative signal input. Channel A1 output select. See Table 1. Channel A1 positive signal input. Internal 100 W center−tapped termination pin for channel A1. Channel A1 negative signal input. Channel A0 output select. See Table 1. http://onsemi.com 3 NB4L858M Table 3. Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 1) > 2000 V >110 V 32−LQFP Flammability Rating Level 2 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 380 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Rating Unit 3.8 V 3.8 V 3.8 V Static Surge 45 80 mA mA Output Current Continuous Surge 25 80 mA mA TA Operating Temperature Range LQFP−32 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 32 LQFP 32 LQFP 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 2) 32 LQFP 12 to 17 °C/W Tsol Wave Solder <3 sec @ 260°C 265 °C VCC Positive Power Supply GND = 0 V VI Positive Input GND = 0 V VINPP Differential Input Voltage IIN Input Current Through Internal RT (50 W Resistor) IOUT Condition 2 GND v VI v VCC |D − D| Pb−Free Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 4 NB4L858M Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 2.3 V to 3.6 V, GND = 0 V TA = −40°C to +85°C Symbol Characteristic Typ Max Unit 130 190 mA 640 800 400 1000 mV Output HIGH Voltage (No Load) VCC−40 VCC−10 VCC mV VOL Output LOW Voltage (No Load) VCC−1000 VCC−800 VCC−650 mV RTOUT Output Source Resistance Qx or Qx 40 50 60 W VIH Input HIGH Voltage 1600 VCC mV VIL Input LOW Voltage 1500 VCC−100 mV VID Differential Input Voltage (VIHD − VILD) 100 1600 mV RTIN Input Termination Resistance Dx or Dx to VTDx 40 60 W ICC Power Supply Current Voutdiff CML Differential Output Swing (Note 3) No Load Loaded 50 W to VCC VOH Min 50 LVTTL CONTROL INPUT PINS VIH Input HIGH Voltage (LVTTL Inputs) VIL Input LOW Voltage (LVTTL Inputs) IIH Input HIGH Current (LVTTL inputs) IIL Input LOW Current (LVTTL Inputs) 2000 mV 800 mV −10 10 mA −10 10 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. CML outputs require 50 W receiver termination resistors to VCC for proper operation. http://onsemi.com 5 NB4L858M Table 6. AC CHARACTERISTICS VCC = 2.3 V to 3.6 V, GND = 0 V; (Note 4) −40°C Symbol Characteristic Min VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 2 GHz (See Figure 2) fin ≤ 3 GHz fin ≤ 3.5GHz 280 235 170 fDATA Maximum Operating Data Rate tPLH, tPHL Propagation Delay to Output Differential D/D to Q/Q tSWiITCH Typ 365 310 220 25°C Max Min Typ 280 235 170 365 310 220 85°C Max Min Typ 280 235 170 365 310 220 Max Unit mV 3 3 3 Gb/s ps 220 350 450 SELyx to Valid Qyx Output (Note 9) 0.5 1.0 tSKEW Within −Device Skew (Note 5) Within −Device Skew (Note 6) Device to Device Skew (Note 9) 12 25 100 12 25 100 12 25 100 ps tJITTER RMS Random Clock Jitter (Note 8) fin =2 GHz fin =3 GHz Peak−to−Peak Data Dependent Jitter fin =2.5Gb/s (Note 9) fin =3.2Gb/s Crosstalk Induced RMS Jitter (Note 11) 0.5 1.0 2.0 10 0.5 0.5 1.0 5.0 10 0.5 0.5 1.0 2.0 10 0.5 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) tr tf Output Rise/Fall Times @ 0.5 GHz (20% − 80%) 100 Qx, Qx 220 800 80 350 450 0.5 1.0 100 120 800 80 120 220 350 450 0.5 1.0 100 80 ns 800 mV 120 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 5. Worst−case difference between QA0 and QA1 from either DA0 or DA1 (or between QB0 and QB1 from either DB0 or DB1 respectively), when both outputs come from the same input. 6. Worst−case difference between QA and QB outputs, when DA or DB inputs are shorted. 7. Additive RMS jitter with 50% duty cycle input clock signal. 8. Additive peak−to−peak data dependent jitter with input NRZ data signal. 9. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 10. LVTTL/LVCMOS input edge rate less than 1.5 ns 11. Data taken on the same device under identical condition. 400 −40°C 350 85°C VOLTAGE (mV) 300 25°C 250 200 150 100 50 0 1 1.5 2 2.5 3 3.5 INPUT CLOCK FREQUENCY (GHz) Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature http://onsemi.com 6 NB4L858M Dx VINPP = VIH(DX) − VIL(DX) Dx Qx VOUTPP = VOH(QX) − VOL(QX) Qx tPHL tPLH Figure 3. AC Reference Measurement VCC 50 W 50 W Zo = 50 W Q D Receiver Device Driver Device Zo = 50 W Q D Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8057/D) VCC VCC VTDX 50 W 50 W RC RC 50 W 50 W QX DX QX DX 16 mA GND GND Input Output Figure 5. CML Input and Output Structure http://onsemi.com 7 NB4L858M 640 mV MIN QX 320 mV MIN QX (QX − QX) QX 1000 mV MAX 500 mV MAX QX (QX − QX) Figure 6. CML Output Levels ORDERING INFORMATION Package Shipping† NB4L858MFAG LQFP−32 (Pb−Free) 250 Units / Tray NB4L858MFAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB4L858M PACKAGE DIMENSIONS A 32 −T−, −U−, −Z− LQFP FA SUFFIX 32−LEAD PLASTIC PACKAGE CASE 873A−02 ISSUE B 4X A1 0.20 (0.008) AB T−U Z 25 1 −U− −T− B AE P V B1 DETAIL Y 9 DETAIL Y 4X −Z− 9 AE V1 17 8 0.20 (0.008) AC T−U Z S1 S DETAIL AD G −AB− 0.10 (0.004) AC AC T−U Z −AC− BASE METAL ÉÉ ÉÉ ÉÉ F 8X M_ R M N D J C E 0.20 (0.008) SEATING PLANE W K X DETAIL AD Q_ GAUGE PLANE H 0.250 (0.010) SECTION AE−AE http://onsemi.com 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF NB4L858M ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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