NB7L111M 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output Description The NB7L111M is a low skew 1–to–10 differential clock/data driver, designed with clock/data distribution in mind. It accepts two clock/data sources into multiplexer input and reproduces ten identical CML differential outputs. This device is ideal for clock/data distribution across the backplane or a board, and redundant clock switchover applications. The input signals can be either differential or single–ended (if the external reference voltage is provided). Differential inputs incorporate internal 50 W termination resistors and accept Negative ECL (NECL), Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using appropriate power supplies). The differential 16 mA CML output provides matching internal 50 W termination, and 400 mV output swing when externally terminated 50 W to VCC. The NB7L111M operates from a 2.5 V $5% supply or a 3.3 V $5% supply and is guaranteed over the full industrial temperature range of −40°C to +85°C. This device is packaged in a low profile 8x8 mm, QFN−52 package with 0.5 mm pitch (see package dimension on the back of the datasheet). Application notes, models, and support documentation are available at www.onsemi.com. Features • • • • • • • • • • • • • Maximum Input Clock Frequency > 5.5 GHz Typical Maximum Input Data Rate > 6.125 Gb/s Typical < 0.5 ps Maximum Clock RMS Jitter < 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s 50 ps Typical Rise and Fall Times 240 ps Typical Propagation Delay 2 ps Typical Duty Cycle Skew 10 ps Typical Within Device Skew 15 ps Typical Device−to−Device Skew Operating Range: VCC = 2.5 V $5 and 3.3 V $5 400 mV Differential CML Output Swing 50 W Internal Input and Output Termination Resistors Pb−Free Packages are Available* http://onsemi.com 1 52 QFN−52 MN SUFFIX CASE 485M MARKING DIAGRAM* 52 1 NB7L 111M AWLYYWWG A WL YY WW G = Assembly Site = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 1 1 Publication Order Number: NB7L111M/D NC VCC Q0 Q0 VEE Q1 Q1 VEE Q2 Q2 VCC NC VEE 51 50 49 48 47 46 45 44 43 42 41 40 Exposed Pad (EP) 52 NB7L111M VEE 1 39 VCC VTCLK0 2 38 Q3 CLK0 3 37 Q3 CLK0 4 36 VEE VTCLK0 5 35 Q4 6 34 Q4 33 VEE VTSEL QFN52 26 VEE VCC 25 27 NC 13 24 VTCLK1 23 Q6 Q7 28 VCC 12 22 CLK1 Q7 Q6 21 29 VEE 11 20 CLK1 Q8 VEE 19 30 Q8 10 18 VTCLK1 VEE Q5 17 31 Q9 9 16 VTSEL Q9 Q5 15 32 VCC 8 14 7 SEL NC SEL Figure 1. Pinout (Top View) Q0 Q0 VCC Q1 VEE Q1 Q2 VTCLK0 50 W Q2 Q3 CLK0 Q3 0 CLK0 50 W VTCLK0 Q4 Q4 Q5 VTCLK1 50 W CLK1 Q5 Q6 1 CLK1 50 W VTCLK1 VTSEL 50 W SEL Q6 Q7 Q7 R1 Q8 Q8 SEL VTSEL 50 W Q9 R2 R3 Q9 Figure 2. Logic Diagram Table 1. FUNCTION TABLE SEL SEL CLK0/CLK0 CLK1/CLK1 LOW HIGH HIGH ON OFF LOW OFF ON http://onsemi.com 2 NB7L111M Table 2. PIN DESCRIPTION Pin Name I/O 15, 24, 27, 39, 42, 51 VCC − Positive supply voltage. All VCC pins must be externally connected to power supply to guarantee proper operation. Description 1, 18, 21, 26, 30, 33, 36, 40, 45, 48 VEE − Negative supply voltage. All VEE pins must be externally connected to power supply to guarantee proper operation. 2 VTCLK0 − Internal 50 W termination pin for CLK0. (Note 2) 3 CLK0 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Non−inverted differential clock/data input 0 (Note 2). 4 CLK0 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Inverted differential clock/data input 0 (Note 2). 5 VTCLK0 − Internal 50 W termination pin for CLK0. (Note 2) 6 VTSEL 7 SEL LVPECL, CML, LVCMOS, LVTTL, LVDS Input Non−inverted differential clock/data select input. Internal 75 kW to VEE. 8 SEL LVPECL, CML, LVCMOS, LVTTL, LVDS Input Inverted differential clock/data select input. Internal 56 KW to VCC and 56 kW to VEE bias this pin to (VCC−VEE)/2. 9 VTSEL LVPECL, CML, LVCMOS, LVTTL, LVDS Input Internal 50 W termination pin for SEL. (Note 2) 10 VTCLK1 − Internal 50 W termination pin for CLK1. (Note 2) 11 CLK1 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Non−inverted differential clock/data input 1 (Note 2). 12 CLK1 LVPECL, CML, LVCMOS, LVTTL, LVDS Input Inverted differential clock/data input 1 (Note 2). 13 VTCLK1 − Internal 50 W termination pin for CLK1. (Note 2) 14, 25, 41, 52 NC − 17, 20, 23, 29, 32, 35, 38, 44, 47, 50 Q[0−9] CML Outputs Non−inverted CML outputs [0−9] with internal 50 W source termination resistor (Note 1). 16, 19, 22, 28, 31, 34, 37, 43, 46, 49 Q[0−9] CML Outputs Inverted CML outputs [0−9] with internal 50 W source termination resistor (Note 1). EP − − Internal 50 W termination pin for SEL. (Note 2) Exposed Pad (EP). The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit on the printed circuit board. 1. CML output requires 50 W receiver termination resistor to VCC for proper operation. 2. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK and CLK then the device will be susceptible to self−oscillation. http://onsemi.com 3 NB7L111M Table 3. ATTRIBUTES Characteristics Value Input Default State Resistors ESD Protection R1, R3 R2 56 kW 75 kW Human Body Model Machine Model > 1400 V > 80 V Moisture Sensitivity (Note 3) QFN−52 Flammability Rating Oxygen Index: 28 to 34 Pb Pkg Pb−Free Pkg Level 2 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 339 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 4) Symbol Parameter Condition 1 Rating Unit 3.6 V 3.6 V 2.8 |VCC − VEE| V V Continuous Surge 25 50 mA mA Output Current Continuous Surge 25 50 mA mA TA Operating Temperature Range QFN52 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 5) 0 lfpm 500 lfpm QFN52 25 19.6 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 8) QFN52 21 °C/W Tsol Wave Solder 265 265 °C VCC Positive Power Supply VEE = 0 V VI Input Voltage VEE = 0 V VINPP Differential Input Voltage |CLK − CLK| VCC − VEE ≥ 2.8 V VCC − VEE < 2.8 V Iin Input Current Through RT (50 W Resistor) Iout Pb Pb−Free Condition 2 VEE v VI v VCC Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 4. Maximum Ratings are those values beyond which device damage may occur. 5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power). http://onsemi.com 4 NB7L111M Table 5. DC CHARACTERISTICS VCC = 2.375 V 2.625 V and 3.135 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C (Notes 6 and 7) Characteristic Symbol ICC Power Supply Current (Inputs and Outputs Open) VCC = 2.375 V to 2.625 V VCC = 3.135 V to 3.465 V VOH Output HIGH Voltage (Notes 6 and 7) VOL Output LOW Voltage (Notes 6 and 7) VCC = 2.375 V to 2.625 V VCC = 3.135 V to 3.465 V Min Typ Max 255 270 290 305 325 340 VCC − 40 VCC − 20 VCC VCC − 440 VCC − 490 VCC − 350 VCC − 400 VCC – 290 VCC − 340 Unit mA mV mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (See Figures 13 and 15) Vth Input Threshold Reference Voltage Range (Note 8) VIH Single−ended Input HIGH Voltage (Note 7) VIL Single−ended Input LOW Voltage (Note 7) 1125 VCC – 75 mV Vth + 75 VCC mV VEE VCC – 150 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 14 and 16) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage VEE VCC – 75 mV VCMR Input Common Mode Range (Differential Configuration) (Note 9) 1163 VCC – 37 mV VID Differential Input Voltage (VIHD − VILD) 2500 mV IIH Input HIGH Current (Termination Pins Open) CLK[0−1]/CLK[0−1] SEL/SEL −100 −150 5 100 150 mA IIL Input LOW Current (Termination Pins Open) CLK[0−1]/CLK[0−1] SEL/SEL −100 −150 5 100 150 mA RTIN Internal Input Termination Resistor 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W RTemp Coef Internal I/O Termination Resistor Temperature Coefficient 75 −3.75 mW/C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. CML outputs require 50 W receiver termination resistors to VCC for proper operation. 7. Input and output parameters vary 1:1 with VCC. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VCMR(MIN) varies 1:1 with VEE, VCMR(MAX) varies 1:1 with VCC. http://onsemi.com 5 NB7L111M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V and 3.135 V to 3.465 V, VEE = 0 V; (Note 10) −40°C Min Symbol Characteristic VOUTPP Output Voltage Amplitude (@ Vinppmin) (See Figures 3, 4, 5, and 6) VCC = 2.375 V to 2.625 V fin ≤ 3 GHz fin ≤ 5.5 GHz VCC = 3.135 V to 3.465 V fin ≤ 3 GHz fin ≤ 5.5 GHz fDATA Maximum Operating Data Rate tPLH, tPHL Differential Input−to−Output Propagation Delay @ 1 GHz (See Figures 7 and 11) CLK−Q SEL−Q tSKEW Duty Cycle Skew (Note 11) Within Device Skew Device−to−Device Skew (Note 15) tJITTER RMS Random Clock Jitter (Note 13) fin = 3 GHz fin = 5.5 GHz Peak−to−Peak Data Dependent Jitter (Note 14) fDATA = 3.125 Gb/s fDATA = 5 Gb/s fDATA = 6.125 Gb/s VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 12 and Figures 3, 4, 5, and 6) tr tf Output Rise/Fall Times @ 1 GHz (20% − 80%) Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit mV 240 115 330 220 240 115 330 220 240 115 330 220 250 130 350 250 250 130 350 250 250 130 350 250 5 6 5 6 5 6 200 290 240 340 280 390 200 290 240 340 280 390 200 290 240 340 280 390 2 10 15 15 20 80 2 10 15 15 20 80 2 10 15 15 20 80 0.2 0.2 0.5 0.5 0.2 0.2 0.5 0.5 0.2 0.2 0.5 0.5 6 15 15 15 25 25 6 15 15 15 25 25 6 15 15 15 25 25 400 2500 400 2500 400 2500 mV 50 75 50 75 50 75 ps 75 75 75 Gb/s ps ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. 12. VINPP(MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 223−1. 15. Device−to−device skew is measured between outputs under identical transition and conditions @ 1 GHz. http://onsemi.com 6 350 OUTPUT VOLTAGE AMPLITUDE (mV) 400 −40 25 300 250 85 200 150 100 50 0 1 2 3 3.5 4 4.5 5 5.5 6 400 350 25 300 −40 250 85 200 150 100 50 0 6.5 1 2 3 3.5 4 4.5 5 5.5 6 6.5 INPUT CLOCK FREQUENCY (GHz) INPUT CLOCK FREQUENCY (GHz) Figure 3. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 400 mV; VCC = 3.3 V) Figure 4. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 75 mV; VCC = 3.3 V) OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 25 −40 250 200 85 150 100 50 0 1 2 3 3.5 4 4.5 5 5.5 6 400 350 300 85 200 150 100 50 0 6.5 1 2 3 3.5 4.5 5 5.5 6 6.5 Figure 6. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 75 mV; VCC = 2.5 V) 280 270 260 250 Typical Tpd 240 230 220 210 −40 4 INPUT CLOCK FREQUENCY (GHz) Figure 5. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 400 mV; VCC = 2.5 V) 200 −40 25 250 INPUT CLOCK FREQUENCY (GHz) PROPAGATION DELAY (ps) OUTPUT VOLTAGE AMPLITUDE (mV) OUTPUT VOLTAGE AMPLITUDE (mV) NB7L111M 25 Temperature (°C) Figure 7. Propagation Delay versus Temperature http://onsemi.com 7 85 VOLTAGE (50 mV/div) VOLTAGE (50 mV/div) NB7L111M Device DDJ = 6 ps TIME (22.1 ps/div) Device DDJ = 7 ps TIME (22.1 ps/div) VOLTAGE (40 mv/ div) VOLTAGE (40 mv/ div) Figure 8. Typical Output Waveform at 3.125 Gb/s with PRBS 223−1 (Vinpp = 75 mV−left and 400 mV−right) Device DDJ=16ps Device DDJ=17ps TIME (22.1 ps/div) TIME (22.1 ps/div) VOLTAGE (35 mv/div) VOLTAGE (35 mv/div) Figure 9. Typical Output Waveform at 5 Gb/s with PRBS 223−1 (Vinpp=75 mV−left and 400 mV−right) Device DDJ=12ps TIME (22.1 ps/div) Device DDJ=15ps TIME (22.1 ps/div) Figure 10. Typical Output Waveform at 6.125 Gb/s with PRBS 223−1 (Vinpp = 75 mV−left and 400 mV−right) http://onsemi.com 8 NB7L111M CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 11. AC Reference Measurement VCC NB7L111M 50 W VCC 50 W 50 W Q Receiver Device 50 W CLK Q CLK Figure 12. Typical Termination for 16 mA Output Drive and Device Evaluation CLK CLK CLK CLK Vth Vth Figure 13. Differential Input Driven Single−Ended VCC Vthmax Figure 14. Differential Inputs Driven Differentially VCC VCMmax VIHmax VILmax Vth Vthmin GND VIH Vth VIL VCMR VIHDmax VILDmax VID = VIHD − VILD VIHDtyp VILDtyp VIHmin VCMmax VILmin GND Figure 15. Vth Diagram VIHDmin VILDmin Figure 16. VCMR Diagram http://onsemi.com 9 NB7L111M VCC 50 W 50 W Q Q 16 mA VEE Figure 17. CML Output Structure Table 7. Interfacing Options INTERFACING OPTIONS CONNECTIONS CML Connect VTCLK0, VTCLK0, VTCLK1, VTCLK1, VTSEL, VTSEL to VCC LVDS Connect VTCLK0, VTCLK0 together for CLK0 input; Connect VTCLK1, VTCLK1 together for CLK1 input; Connect VTSEL, VTSEL together for SEL control input. AC−COUPLED Bias VTCLK0, VTCLK0, VTSEL, VTSEL and VTCLK1, VTCLK1 inputs within (VCMR) Common Mode Range. RSECL, LVPECL Standard ECL termination techniques. See AND8020. LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. http://onsemi.com 10 NB7L111M Application Information minimum input swing of 100 mV and the maximum input swing of 450 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). All NB7L111M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are VCC 50 W VCC 50 W Q CLK Z CML or NB7L111M VCC VTCLK VCC VTCLK Z Q CML or NB7L111M 50 W 50 W CLK VEE VEE Figure 18. CML to CML Interface VCC VCC 50 W PECL Driver VBIAS* VBIAS* 50 W Recommended RT Values VCC RT RT 5.0 V 290 W 3.3 V 150 W VEE 2.5 V 80 W CLK Z VTCLK VTCLK Z 50 W NB7L111M 50 W CLK RT VEE VEE Figure 19. PECL to CML Receiver Interface *VBIAS is within VCMR Range. VCC LVDS Driver VCC CLK Z VTCLK 50 W VTCLK 50 W Z CLK VEE VEE Figure 20. LVDS to CML Receiver Interface http://onsemi.com 11 NB7L111M NB7L111M VCC VCC CLK Z LVTTL/ LVCMOS Driver No Connect No Connect 50 W VTCLK VTCLK NB7L111M 50 W VREF VEE Recommended VREF Values VREF CLK VCC Figure 21. LVCMOS/LVTTL to CML Receiver Interface LVCMOS VCC * VEE 2 LVTTL 1.5 V ORDERING INFORMATION Package Shipping † QFN−52 46 Units / Rail NB7L111MMNG QFN−52 (Pb−Free) 46 Units / Rail NB7L1MMNR2 QFN−52 2000 / Tape & Reel QFN−52 (Pb−Free) 2000 / Tape & Reel Device NB7L111MMN NB7L1MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NB7L111M PACKAGE DIMENSIONS 52 PIN QFN 8x8 CASE 485M−01 ISSUE A D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B E DIM A A1 A2 A3 b D D2 E E2 e K L 2X 0.15 C 2X 0.15 C A2 0.10 C A 0.08 C SEATING PLANE A3 A1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 −−− 0.30 0.50 REF C D2 14 52 X L 26 27 13 E2 39 1 52 X K 52 40 e 52 X b NOTE 3 0.10 C A B 0.05 C GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 13 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB7L111M/D