MC34025 D

MC34025, MC33025
High Speed Double-Ended
PWM Controller
The MC34025 series are high speed, fixed frequency, double−ended
pulse width modulator controllers optimized for high frequency
operation. They are specifically designed for Off−Line and
DC−to−DC converter applications offering the designer a cost
effective solution with minimal external components. These
integrated circuits feature an oscillator, a temperature compensated
reference, a wide bandwidth error amplifier, a high speed current
sensing comparator, steering flip−flop, and dual high current totem
pole outputs ideally suited for driving power MOSFETs.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, and a latch for single pulse metering.
The flexibility of this series allows it to be easily configured for
either current mode or voltage mode control.
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MARKING
DIAGRAMS
16
PDIP−16
P SUFFIX
CASE 648
16
1
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
50 ns Propagation Delay to Outputs
Dual High Current Totem Pole Outputs
Wide Bandwidth Error Amplifier
Fully−Latched Logic with Double Pulse Suppression
Latching PWM for Cycle−By−Cycle Current Limiting
Soft−Start Control with Latched Overcurrent Reset
Input Undervoltage Lockout with Hysteresis
Low Startup Current (500 mA Typ)
Internally Trimmed Reference with Undervoltage Lockout
45% Maximum Duty Cycle (Externally Adjustable)
Precision Trimmed Oscillator
Voltage or Current Mode Operation to 1.0 MHz
Functionally Similar to the UC3825
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
16
4
5.1V
Reference
5
UVLO
Vref
Clock
RT
CT
15
VCC
Oscillator
13
6
7
Ramp
Error Amp 3
Output
Noninverting 2
Input
Inverting
Input 1
14
Error
Amp
Output B
Latching
PWM and
Steering
Flip Flop
Output A
Power
12 Ground
9
10 Ground
This device contains 227 active transistors.
Figure 1. Simplified Application
October, 2012 − Rev. 9
SO−16WB
DW SUFFIX
CASE 751G
16
1
MC3x025DW
AWLYYWWG
1
x
A
WL
YY
WW
G
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Error Amp
Inverting Input
Error Amp
Noninverting Input
Error Amp Output
1
16
Vref
2
15
VCC
3
14
Output B
Clock
4
13
VC
RT
5
12
Power Ground
CT
6
11
Output A
Ramp
7
10
Soft-Start
8
9
Ground
Current Limit/
Shutdown
(Top View)
Soft-Start
© Semiconductor Components Industries, LLC, 2012
16
11
8
Soft-Start
VC
MC3x025P
AWLYYWWG
1
Current
Limit/
Shutdown
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Publication Order Number:
MC34025/D
MC34025, MC33025
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
30
V
Output Driver Supply Voltage
VC
25
V
Output Current, Source or Sink (Note 1)
DC
Pulsed (0.5 ms)
IO
Current Sense, Soft−Start, Ramp, and Error Amp Inputs
Vin
−0.3 to +7.0
V
Error Amp Output and Soft−Start Sink Current
IO
10
mA
Clock and RT Output Current
ICO
5.0
mA
PD
RqJA
862
145
mW
°C/W
PD
RqJA
1.25
100
W
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature (Note 2)
MC34025
MC33025
TA
0 to +70
−40 to +105
Storage Temperature Range
Tstg
−55 to +150
°C
Human Body Model ESD Capability per JEDEC − JESD22−A114F
HBM
2000
V
Machine Model ESD Capability per JEDEC − JESD22−A115C
MM
200
V
Power Dissipation and Thermal Characteristics
SO−16 Package (Case 751G)
Maximum Power Dissipation @ TA = + 25°C
Thermal Resistance, Junction−to−Air
DIP Package (Case 648)
Maximum Power Dissipation @ TA = + 25°C
Thermal Resistance, Junction−to−Air
A
0.5
2.0
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA
is the operating ambient temperature range that applies [Note 2], unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Vref
5.05
5.1
5.15
V
Line Regulation (VCC = 10 V to 30 V)
Regline
−
2.0
15
mV
Load Regulation (IO = 1.0 mA to 10 mA)
Regload
−
2.0
15
mV
Temperature Stability
TS
−
0.2
−
mV/°C
Total Output Variation over Line, Load, and Temperature
Vref
4.95
−
5.25
V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = + 25°C)
Vn
−
50
−
mV
Long Term Stability (TA = +125°C for 1000 Hours)
S
−
5.0
−
mV
ISC
−30
−65
−100
mA
fosc
380
370
400
400
420
430
kHz
Frequency Change with Voltage (VCC = 10 V to 30 V)
Dfosc/DV
−
0.2
1.0
%
Frequency Change with Temperature (TA = Tlow to Thigh)
Dfosc/DT
−
2.0
−
%
Sawtooth Peak Voltage
VP
2.6
2.8
3.0
V
Sawtooth Valley Voltage
VV
0.7
1.0
1.25
V
VOH
VOL
3.9
−
4.5
2.3
−
2.9
V
Characteristic
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = + 25°C)
Output Short Circuit Current
OSCILLATOR SECTION
Frequency
TJ = + 25°C
Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh)
Clock Output Voltage
High State
Low State
1. Maximum package power dissipation limits must be observed.
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = +70°C for MC34025
Tlow = 0°C for MC34025
Thigh = +105°C for MC33025
Tlow = − 40°C for MC33025
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2
MC34025, MC33025
ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
Symbol
Min
Input Offset Voltage
VIO
−
Input Bias Current
IIB
−
Characteristic
Typ
Max
Unit
−
15
mV
0.6
3.0
mA
ERROR AMPLIFIER SECTION
Input Offset Current
Open−Loop Voltage Gain (VO = 1.0 V to 4.0 V)
Gain Bandwidth Product (TJ = + 25°C)
Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V)
IIO
−
0.1
1.0
mA
AVOL
60
95
−
dB
GBW
4.0
8.3
−
MHz
CMRR
75
95
−
dB
Power Supply Rejection Ratio (VCC = 10 V to 30 V)
PSRR
85
110
−
dB
Output Current,
ISource
ISink
0.5
1.0
3.0
3.6
−
−
mA
VOH
VOL
4.5
0
4.75
0.4
5.0
1.0
V
SR
6.0
12
−
V/ms
Output Voltage Swing,
Source (VO = 4.0 V)
Sink (VO = 1.0 V)
High State (IO = − 0.5 mA)
Low State (IO = 1.0 mA)
Slew Rate
PWM COMPARATOR SECTION
Ramp Input Bias Current
Duty Cycle of Each Output,
Maximum
Minimum
Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V)
Propagation Delay (Ramp Input to Output, TJ = + 25°C)
IIB
−
−0.5
−5.0
mA
DC(max)
DC(min)
40
−
45
−
−
0
%
Vth
1.1
1.25
1.4
V
tPLH(in/out)
−
60
100
ns
Ichg
3.0
9.0
20
mA
Idischg
1.0
4.0
−
mA
SOFT−START SECTION
Charge Current (VSoft−Start = 0.5 V)
Discharge Current (VSoft−Start = 1.5 V)
CURRENT SENSE SECTION
Input Bias Current (Pin 9(12) = 0 V to 4.0 V)
IIB
−
−
15
mA
Current Limit Comparator Threshold
Shutdown Comparator Threshold
Vth
Vth
0.9
1.25
1.0
1.40
1.10
1.55
V
tPLH(in/out)
−
50
80
ns
VOL
−
−
13
12
0.25
1.2
13.5
13
0.4
2.2
−
−
VOL(UVLO)
−
0.25
1.0
V
Output Leakage Current (VC = 20 V)
IL
−
100
500
mA
Output Voltage Rise Time (CL = 1.0 nF, TJ = + 25°C)
tr
−
30
60
ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = + 25°C)
tf
−
30
60
ns
Vth(on)
8.8
9.2
9.6
V
VH
0.4
0.8
1.2
V
−
−
0.5
25
1.2
35
Propagation Delay (Current Limit/Shutdown to Output, TJ = + 25°C)
OUTPUT SECTION
Output Voltage
Low State
(ISink = 20 mA)
(ISink = 200 mA)
(ISource = 20 mA)
(ISource = 200 mA)
High State
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA)
VOH
V
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC Increasing)
UVLO Hysteresis Voltage (VCC Decreasing After Turn−On)
TOTAL DEVICE
Power Supply Current
Startup (VCC = 8.0 V)
Operating
ICC
3. Maximum package power dissipation limits must be observed.
4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = +70°C for MC34025
Tlow = 0°C for MC34025
Thigh = +105°C for MC33025
Tlow = − 40°C for MC33025
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3
mA
MC34025, MC33025
100 k
3
2
5
4
7
6
9
1200
VCC = 15 V
TA = + 25°C
f osc , OSCILLATOR FREQUENCY (kHz)
R T , TIMING RESISTOR ( Ω )
1
8
CT=
1. 100 nF
2. 47 nF
3. 22 nF
4. 10 nF
5. 4.7 nF
6. 2.2 nF
7. 1.0 nF
8. 470 pF
9. 220 pF
10 k
1.0 k
470
100
1000
104
105
106
fosc, OSCILLATOR FREQUENCY (Hz)
1000
RT = 1.2 k
CT = 1.0 nF
400 kHz
RT = 3.6 k
CT = 1.0 nF
50 kHz
RT = 36 k
CT = 1.0 nF
800
VCC = 15 V
600
400
200
0
-55
107
Figure 2. Timing Resistor versus
Oscillator Frequency
-25
50
0
25
75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 3. Oscillator Frequency versus Temperature
120
1.3
0
45
Gain
60
Phase
40
90
20
, EXCESS PHASE (°C)
80
0
-20
10
135
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
V th, ZERO DUTY CYCLE (V)
100
θ
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
1.0 MHz
1.28
VCC = 15 V
Pin 7(9) = 0 V
1.26
1.24
1.22
1.2
-55
10 M
Figure 4. Error Amp Open Loop Gain and
Phase versus Frequency
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 5. PWM Comparator Zero Duty Cycle
Threshold Voltage versus Temperature
2.55 V
3.0 V
2.5 V
2.5 V
2.45 V
2.0 V
0.1 ms/DIV
0.1 ms/DIV
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
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4
125
0
I SC, REFERENCE SHORT CIRCUIT CURRENT (mA)
Vref , REFERENCE VOLTAGE CHANGE (mV)
MC34025, MC33025
-5.0
VCC = 15 V
TA = - 55°C
-10
TA = +125°C
TA = + 25°C
-15
-20
-25
-30
10
0
20
30
ISource, SOURCE CURRENT (mA)
40
50
66
65.6
VCC = 15 V
65.2
64.8
64.4
64
-55
100
125
2.0 mV/DIV
Vref LINE REGULATION 10 V - 24 V
2.0 ms/DIV
Vref LINE REGULATION 1.0 mA - 10 mA
2.0 ms/DIV
Figure 10. Reference Line Regulation
Figure 11. Reference Load Regulation
4.0
Vth , SHUTDOWN THRESHOLD VOLTAGE (V)
Δ Vth(CL), CURRENT LIMIT THRESHOLD CHANGE (mV)
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Reference Short Circuit Current
versus Temperature
2.0 mV/DIV
Figure 8. Reference Voltage Change
versus Source Current
- 25
2.0
0
- 2.0
- 4.0
- 6.0
- 8.0
-10
-12
- 50
- 25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
1.50
1.46
VCC = 15 V
1.42
1.38
1.34
1.30
-55
Figure 12. Current Limit Comparator Threshold
Change versus Temperature
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 13. Shutdown Comparator Threshold
Voltage versus Temperature
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5
125
9.5
Vsat, OUTPUT SATURATION VOLTAGE (V)
10
VCC = 15 V
9.0
8.5
8.0
7.5
7.0
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
0
VCC
-1.0
2.0
1.0
Ground
0
0
0.2
0.4
0.6
0.8
IO, OUTPUT LOAD CURRENT (A)
OUTPUT RISE & FALL TIME 10.0 nF LOAD
50 ns/DIV
Figure 16. Drive Output Rise and Fall Time
Figure 17. Drive Output Rise and Fall Time
30
RT = 3.65 kW
CT = 1.0 nF
20
VCC Increasing
15
VCC Decreasing
10
5.0
0
0
Sink Saturation
(Load to VCC)
Figure 15. Output Saturation Voltage
versus Load Current
OUTPUT RISE & FALL TIME 1.0 nF LOAD
50 ns/DIV
25
Source Saturation
(Load to Ground)
VCC = 15 V
80 ms Pulsed Load
-2.0 120 Hz Rate
TA = + 25°C
Figure 14. Soft−Start Charge Current
versus Temperature
I CC , SUPPLY CURRENT (mA)
I chg , SOFT‐START CHARGE CURRENT ( μ A)
MC34025, MC33025
4.0
8.0
12
VCC, SUPPLY VOLTAGE (V)
16
20
Figure 18. Supply Voltage versus Supply Current
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6
1.0
MC34025, MC33025
VCC
16
Vref
15
Reference
Regulator
4
Clock
4.2 V
5
Oscillator
RT
6
CT
Ramp
7
PWM
1.25 V Comparator
13
9.2 V
Vref
UVLO
VC
14
Output B
R
T
Q
S
Error Amp Output
3
2
VCC
VCC
UVLO
Error
Amp
PWM Latch
Q
Q
Steering
Flip Flop
11
Output A
12
Power Ground
+
Noninverting Input
Inverting Input
1
Current
Limit
9.0 mA
1.0 V
8
9
Soft-Start
CSS
R
0.5 V
Q
S
Current Limit/
Shutdown
Shutdown
Soft-Start Latch
10
1.4 V
Ground
Figure 19. Representative Block Diagram
CT
Clock
Soft-Start
Error Amp Output
Ramp
PWM
Comparator
Output A
Output B
Figure 20. Current Limit Operating Waveforms
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7
Vin
MC34025, MC33025
OPERATING DESCRIPTION
Soft−Start Latch
The MC33025 and MC34025 series are high speed, fixed
frequency, double−ended pulse width modulator controllers
optimized for high frequency operation. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
solution with minimal external components. A
representative block diagram is shown in Figure 19.
Soft−Start is accomplished in conjunction with an
external capacitor. The soft start capacitor is charged by an
internal 9.0 mA current source. This capacitor clamps the
output of the error amplifier to less than its normal output
voltage, thus limiting the duty cycle.
The time it takes for a capacitor to reach full charge is
given by:
Oscillator
t [ (4.5 • 10 5) C Soft-Start
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. The RT pin
is set to a temperature compensated 3.0 V. By selecting the
value of RT, the charge current is set through a current mirror
for the timing capacitor CT. This charge current runs
continuously through CT. The discharge current ratio is to be
10 times the charge current, which yields the maximum duty
cycle of 90%. CT is charged to 2.8 V and discharged to 1.0
V. During the discharge of CT, the oscillator generates an
internal blanking pulse that resets the PWM Latch, inhibits
the outputs, and toggles the steering flip−flop. The threshold
voltages on the oscillator comparator is trimmed to
guarantee an oscillator accuracy of 5.0% at 25°C.
Additional dead time can be added by externally
increasing the charge current to CT as shown in Figure 24.
This changes the charge to discharge ratio of CT which is set
internally to Icharge/10 Icharge. The new charge to discharge
ratio will be:
% Deadtime +
A Soft−Start latch is incorporated to prevent erratic
operation of this circuitry. Two conditions can cause the
Soft−Start circuit to latch so that the Soft−Start capacitor
stays discharged. The first condition is activation of an
undervoltage lockout of either VCC or Vref. The second
condition is when current sense input exceeds 1.4 V. Since
this latch is “set dominant”, it cannot be reset until either of
these signals is removed, and the voltage at CSoft−Start is less
than 0.5 V.
PWM Comparator and Latch
A PWM circuit typically compares an error voltage with
a ramp signal. The outcome of this comparison determines
the state of the output. In voltage mode operation the ramp
signal is the voltage ramp of the timing capacitor. In current
mode operation the ramp signal is the voltage ramp induced
in a current sensing element. The ramp input of the PWM
comparator is pinned out so that the user can decide which
mode of operation best suits the application requirements.
The ramp input has a 1.25 V offset such that whenever the
voltage at this pin exceeds the Error Amplifier Output
voltage minus 1.25 V, the PWM comparator will cause the
PWM latch to set, disabling the outputs. Once the PWM
latch is set, only a blanking pulse by the oscillator can reset
it, thus initiating the next cycle.
A toggle flip flop connected to the output of the PWM
latch controls which output is active. The flip flop is pulsed
by an OR gate that gets its inputs from the oscillator clock
and the output of the PWM latch. A pulse from either one
will cause the flip flop to enable the other output.
I additional ) I charge
10 (I charge)
A bidirectional clock pin is provided for synchronization
or for master/slave operation. As a master, the clock pin
provides a positive output pulse during the discharge of CT.
As a slave, the clock pin is an input that resets the PWM latch
and blanks the drive output, but does not discharge CT.
Therefore, the oscillator is not synchronized by driving the
clock pin alone. Figures 30 and 31 provide suggested
synchronization.
Error Amplifier
A fully compensated Error Amplifier is provided. It
features a typical DC voltage gain of 95 dB and a gain
bandwidth product of 8.3 MHz with 75 degrees of phase
margin (Figure 4). Typical application circuits will have the
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated
from the output of the switching power supply. Both inputs
have a Common Mode Voltage (VCM) input range of 1.5 V
to 5.5 V. The Error Amplifier Output is provided for external
loop compensation.
Current Limiting and Shutdown
A pin is provided to perform current limiting and
shutdown operations. Two comparators are connected to the
input of this pin. When the voltage at this pin exceeds 1.0 V,
one of the comparators is activated. The output of this
comparator sets the PWM latch, which disables the output.
In this way cycle−by−cycle current limiting is
accomplished. If a current limit resistor is used in series with
the power devices, the value of the resistor is found by:
1.0 V
R Sense +
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8
I pk (switch)
MC34025, MC33025
paths back to the input filter capacitor. All bypass capacitors
and snubbers should be connected as close as possible to the
specific part in question. The PC board lead lengths must be
less than 0.5 inches for effective bypassing or snubbing.
If the voltage at this pin exceeds 1.4 V, the second
comparator is activated. This comparator sets a latch which,
in turn, causes the Soft−Start capacitor to be discharged. In
this way a “hiccup” mode of recovery is possible in the case
of output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
controller will enter a “hiccup” mode is given by:
Instabilities
In current mode control, an instability can be encountered
at any given duty cycle. The instability is caused by the
current feedback loop. It has been shown that the instability
is caused by a double pole at half the switching frequency.
If an external ramp (Se) is added to the on−time ramp (Sn)
of the current−sense waveform, stability can be achieved
(see Figure 21).
One must be careful not to add too much ramp
compensation. If too much is added, the system will start to
perform like a voltage mode regulator. All benefits of
current mode control will be lost. Figures 29A and 29B show
examples of two different ways in which external ramp
compensation can be implemented.
1.4 V
I shutdown +
R Sense
Undervoltage Lockout
There are two undervoltage lockout circuits within the IC.
The first senses VCC and the second Vref. During power−up,
VCC must exceed 9.2 V and Vref must exceed 4.2 V before
the outputs can be enabled and the Soft−Start latch released.
If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs
are disabled and the Soft−Start latch is activated. When the
UVLO is active, the part is in a low current standby mode
allowing the IC to have an off−line bootstrap startup circuit.
Typical startup current is 500 mA.
Ramp Input
Ramp Compensation
Se
Output
The MC34025 has two high current totem pole outputs
specifically designed for direct drive of power MOSFETs.
They are capable of up to ± 2.0 A peak drive current with a
typical rise and fall time of 30 ns driving a 1.0 nF load.
Separate pins for VC and Power Ground are provided.
With proper implementation, a significant reduction of
switching transient noise imposed on the control circuitry is
possible. The separate VC supply input also allows the
designer added flexibility in tailoring the drive voltage
independent of VCC.
1.25 V
+
+
Current Signal
Sn
Figure 21. Ramp Compensation
A simple equation can be used to calculate the amount of
external ramp necessary to add that will achieve stability in
the current loop. For the following equations, the calculated
values for the application circuit in Figure 37 are also shown.
Reference
Se +
A 5.1 V bandgap reference is pinned out and is trimmed
to an initial accuracy of ±1.0% at 25°C. This reference has
short circuit protection and can source in excess of 10 mA
for powering additional control system circuitry.
where:
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. With high
frequency, high power, switching power supplies it is
imperative to have separate current loops for the signal paths
and for the power paths. The printed circuit layout should
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
VO =
NP, NS =
=
Ai =
=
L=
RS =
VO
L
ǒ Ǔ
NS
NP
(R S)A
i
DC output voltage
number of power transformer primary
or secondary turns
gain of the current sense network
(see Figures 26, 27 and 28)
output inductor
current sense resistance
5
4 (0.3)(0.55)
For the application circuit: S e +
1.8 μ 16
ǒ Ǔ
+ 0.115 Vńμs
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9
MC34025, MC33025
PIN FUNCTION DESCRIPTION
Pin No.
DIP/SOIC
Function
1
Error Amp Inverting
Input
This pin is usually used for feedback from the output of the power supply.
2
Error Amp
Noninverting Input
This pin is used to provide a reference in which an error signal can be produced on the output of the
error amp. Usually this is connected to Vref, however an external reference can also be used.
3
Error Amp Output
This pin is provided for compensating the error amp for poles and zeros encountered in the power
supply system, mostly the output LC filter.
4
Clock
This is a bidirectional pin used for synchronization.
5
RT
The value of RT sets the charge current through timing Capacitor, CT.
6
CT
In conjunction with RT, the timing Capacitor sets the switching frequency. Because this part is a
push−pull output, each output runs at one−half the frequency set at this pin.
7
Ramp Input
For voltage mode operation this pin is connected to CT. For current mode operation this pin is
connected through a filter to the current sensing element.
8
Soft−Start
A capacitor at this pin sets the Soft−Start time.
9
Current
Limit/Shutdown
This pin has two functions. First, it provides cycle−by−cycle current limiting. Second, if the current is
excessive, this pin will reinitiate a Soft−Start cycle.
10
Ground
This pin is the ground for the control circuitry.
11
Output A
This is a high current totem pole output.
12
Power Ground
This is a separate power ground return that is connected back to the power source. It is used to
reduce the effects of switching transient noise on the control circuitry.
13
VC
This is a separate power source connection for the outputs that is connected back to the power
source input. With a separate power source connection, it can reduce the effects of switching
transient noise on the control circuitry.
14
Output B
This is a high current totem pole output.
15
VCC
This pin is the positive supply of the control IC.
16
Vref
This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.
Description
4
4
5
5
Oscillator
Oscillator
6
CT
7
CT
From Current
Sense Element
1.25 V
7
3
1
Output Voltage
Feedback Input
Vref
6
1.25 V
3
1
Output Voltage
Feedback Input
2
In voltage mode operation, the control range on the output of
the Error Amplifier from 0% to 90% duty cycle is from 2.25 V
to 4.05 V.
Vref
2
In current mode control, an RC filter should be placed at the
ramp input to filter the leading edge spike caused by turn−on of
a power MOSFET.
Figure 22. Voltage Mode Operation
Figure 23. Current Mode Operation
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10
MC34025, MC33025
5.0 V
0V
Vref
4
RDT
4
5
RT
Oscillator
6
RT
Oscillator
6
5
CT
CT
Additional dead time can be added by the addition of a dead
time resistor from Vref to CT. See text on oscillator section for
more information.
The sync pulse fed into the clock pin must be at least 3.9 V. RT
and CT need to be set 10% slower than the sync frequency. This
circuit is also used in voltage mode operation for master/slave
operation. The clock signal would be coming from the master
which is set at the desired operating frequency, while the slave
is set 10% slower.
Figure 24. Dead Time Addition
Figure 25. External Clock Synchronization
9
ISense
The addition of an RC filter will eliminate instability caused by the
leading edge spike on the current waveform. This sense signal
can also be used at the ramp input pin for current mode control.
For ramp compensation it is necessary to know the gain of the
current feedback loop. If a transformer is used, the gain can be
calculated by:
A
i
+
R Sense
turns ratio
Figure 26. Resistive Current Sensing
9
9
Rw
ISense
Rw
Figure 27. Primary Side Current Sensing
0
ISense
Figure 28. Primary or Secondary Side
Current Sensing
The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also
be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback
loop. The gain can be calculated by:
Rw
A
i
+
turns ratio
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11
MC34025, MC33025
4
5
Oscillator
6
CT
Current Sense
Information
C1
R1
7
1.25 V
R2
3
This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator
signal is added to the current signal by a voltage divider consisting of resistors R1 and R2.
Figure 29A. Slope Compensation (Noise Sensitive)
Rw
Output
RM
CM
Ramp
Input
RM
Ramp
Input
Rf
7
Cf
Output
Figure 29. Keeps Fig numbering sequence correct
Current Sense
Transformer
7
CM
1.25 V
Current Sense
Resistor
3
Rf
1.25 V
3
Cf
When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and
capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you
can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset
pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by
RM = VCC/IM.
Figure 29B. Slope Compensation (Noise Immune)
4
4
Vref
5
Oscillator
6
5
6
CT
Oscillator
RT
Figure 30. Current Mode Master/Slave Operation Over Short Distances
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12
MC34025, MC33025
Synchronizes Both
Converters
to the Same Phase
10 k
Synchronizes Both Converters
to the Same Operating Frequency
4.7 k
20
+15 V
+15 V
4.7 k
1.0 k
3.0 k
MMBT3906
15
2
13
4700
16
4
2200
15
13
MMBT3904
430
3
2
10 k
11
3
MMBD914
FB
16
4
Output A
FB
14
1
1
11
MC34025
MC34025
Output B
Output A
14
22 k
6
470 pF
5
8
5
7
9
8
21
Output B
12
10
30 k
6
470 pF
680 pF
562
7
680 pF
562
100 k
From Curr
Sense
MMBT3904
100
MC34071
Provides Leading
Edge Blanking
3320
1.0 k
1.0 k
From Curr
Sense
Provides Current
Sense Amplification &
Eliminates Leading
Edge Spike
Figure 31. Synchronization Over Long Distances
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13
9
12
10
MC34025, MC33025
IB
1
+
2
+
R1
R2
VC
0
Vref
Base Charge
Removal
-
8
Vin
15
14
CSS
Q
T
Q
In voltage mode operation, the maximum duty cycle can be
clamped. By the addition of a PNP transistor to buffer the clamp
voltage, the Soft−Start current is not affected by R1.
The new equation for Soft−Start is
t[
V clamp ) 0.6
9.0 μA
11
12
ǒCSSǓ
In current mode operation, this circuit will limit the maximum
voltage allowed at the ramp input to end a cycle.
To Current
Sense Input
RS
The totem pole output can furnish negative base current for
enhanced transistor turn−off, with the addition of the capacitor in
series with the base.
Figure 32. Buffered Maximum Clamp Level
Figure 33. Bipolar Transistor Drive
VC
VC
15
15
Isolation
Boundary
14
14
Q
T
Q
T
Q
VC
Q
11
11
12
12
Figure 34. Isolated MOSFET Drive
Figure 35. Direct Transformer Drive
The totem pole output can easily drive pulse transformers. A Schottky diode is recommended when driving inductive loads at high
frequencies. The diode can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven
below ground.
VC
Vin
15
14
A series gate resistor may be needed to damp high frequency
parasitic oscillation caused by a MOSFET’s input capacitance
and any series wiring inductance in the gate−source circuit. The
series resistor will also decrease the MOSFET’s switching speed.
A Schottky diode can reduce the driver’s power dissipation due to
excessive ringing, by preventing the output pin from being driven
below ground. The Schottky diode also prevents substrate
injection when the output pin is driven below ground.
Q
T
Q
11
12
To Current
Sense Input
RS
Figure 36. MOSFET Parasitic Oscillations
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14
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15
8
0.01
47 k
2
1
Error
Amp
1.25 V
Oscillator
Q
S
R
9.0 μA
4.0 V
Q
10
0.5 V
PWM Latch
S
R
L2 − 7 turns #18 AWG, 1/2” diameter air core
Coilcraft P3271−A
L1 − 2 turns #48 AWG (1300 strands litz wire)
Core: Philips 3F3, part #EP10−3F3
Bobbin: Philips part #EP10PCB1−8
L = 1.8 μH
Coilcraft P3270−A
T
Q
Q
9.2 V
Shutdown
Current
Limit
9
50 mVp−p
71.2%
V in = 48 V, IO = 15 A
V in = 48 V, IO = 15 A
Output Ripple
Efficiency
54 mV = ± 1.0%
V in = 48 V, IO = 8.0 V to 15 A
Result
22 1500 pF
Load Regulation
1N5819
L1
10 μF 1
MBR2535CTL
1.8 μ H
14 mV = ± 0.275%
Condition
220 pF
100
0.3 Ω 2
IRF640
50
1600 pF
T1
22 1500 pF
100 1N5819
36 V to 56 V
V in = 40 V to 56 V, I O = 15 A
47
100
1N5819
4.7
1N5819
4.7
10
10
4.7
V in
Line Regulation
Test
1.4 V
1.0 V
12
11
14
13
15
1 − 10 (1.0 μ F) ceramic capacitors in parallel
2 − 5 (1.5 Ω ) resistors in parallel
3 − 2 (1.0 μ F) cearmic capacitors in parallel
Insulators − All power devices are insulated with Berquist Sil−Pad 1500
T1 − Primary: 16 turns center tapped #48 AWG (1300 strands litz wire)
Secondary: 4 turns center tapped 0.003” (2 layers) copper foil
Bootstrap: 1 turn added to each secondary output #36 AWG
Core: Philips 3F3, part #4312 020 4124
Bobbin: Philips part #4322 021 3525
Coilcraft P3269−A
0.015 μF
3
7
6
5
4
Reference
Regulator
Heatsinks − Power FET: AAVID Heatsink #533902B02554 with clip
Output Rectifiers: AAVID Heatsink #533402B02552 with clip
2.0 k
0.01
22 k
1000 pF
1.2 k
1.0
16
47
47 k
2.0 μF 3
L2
900 nH
VO
5.0 V
MC34025, MC33025
Figure 37. Application Circuit
MC34025, MC33025
4.7 μ H
MBR
2535CTI
1N5819
1N5819
1500 pF
1
+
4.0″
100 pF
100 pF
1N5819
+
10
1000 pF
0.01
1N5819
0.01
MBR
2535CTI
2200 pF
1500 pF
1
1
6.5″
(Top View)
Figure 38. PC Board With Components
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16
MC34025, MC33025
(Top View)
4.0″
6.5″
(Bottom View)
Figure 39. PC Board Without Components
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17
MC34025, MC33025
ORDERING INFORMATION
Package
Shipping†
MC33025DWG
SOIC−16WB
(Pb−Free)
47 Units / Rail
MC33025DWR2G
SOIC−16WB
(Pb−Free)
1000 Units / Tape & Reel
PDIP−16
(Pb−Free)
25 Units / Rail
MC34025DWG
SOIC−16WB
(Pb−Free)
47 Units / Rail
MC34025DWR2G
SOIC−16WB
(Pb−Free)
1000 Units / Tape & Reel
PDIP−16
(Pb−Free)
25 Units / Rail
Device
MC33025PG
MC34025PG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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18
MC34025, MC33025
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
H
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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19
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC34025, MC33025
PACKAGE DIMENSIONS
SOIC−16WB
DW SUFFIX
CASE 751G−03
ISSUE C
A
D
q
9
h X 45 _
E
0.25
H
8X
M
B
M
16
1
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
8
16X
M
14X
e
T A
S
B
S
A1
L
A
0.25
B
B
SEATING
PLANE
T
C
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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MC34025/D