40V Precision Single Supply Rail-Rail Output Low Power Operational Amplifiers ISL28108, ISL28208 Features The ISL28108 and ISL28208 are single and dual low power precision amplifiers optimized for single supply applications. These devices feature a common mode input voltage range extending to 0.5V below the V- rail, a rail-to-rail differential input voltage range for use as a comparator, and rail to rail output voltage swing, which make them ideal for single supply applications where input operation at ground is important. • Single or Dual Supply, Rail-to-Rail Output and Below Ground (V-) input capability Added features include low offset voltage, and low temperature drift making them the ideal choice for applications requiring high DC accuracy. The output stage is capable of driving large capacitive loads from rail to rail for excellent ADC driving performance. The devices can operate for single or dual supply from 3V (±1.5V) to 40V (±20V) and are fully characterized at ±5V and ±15V. The combination of precision, low power, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. • Rail-to-rail Input Differential Voltage Range for Comparator Applications • Single Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V • Low Current Consumption (VS = ±5V) . . . . . . . . . . . . . . 165µA • Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 15.8nV/√Hz • Low Noise Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 80fA/√Hz • Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 230µV • Superb Temperature Drift - Voltage Offset TC . . . . . . . . . . . . . . . . . . . . . . 0.1µV/°C, Typ • Low Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . -13nA Typ • Operating Temperature Range. . . . . . . . . . .-40°C to +125°C • No Phase Reversal Applications for these amplifiers include precision instrumentation, data acquisition, precision power supply control, and industrial control. Applications The ISL28108 single is offered in 8 Ld TDFN, SOIC and MSOP packages. The ISL28208 dual amplifier is offered in 8 Ld TDFN, MSOP, and SOIC packages. All devices are offered in standard pin configurations and operate over the extended temperature range to -40°C to +125°C. • Medical Instrumentation • Precision Instruments • Data Acquisition • Power Supply Control • Industrial Process Control RF 100kΩ RINRSENSE IN- 10kΩ RIN+ IN+ - 500 +3V to 40V GAIN = 10 RREF+ 100kΩ VS = ±15V 300 200 + 10kΩ 400 VOUT V+ ISL28108 V- VOS (µV) LOAD 100 -40°C +25°C +125°C 0 -100 -200 -300 VREF -400 -500 -16 SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER FIGURE 1. TYPICAL APPLICATION CIRCUIT March 17, 2011 FN6935.1 1 -15.5 -15 -14.5 -14 13 13.5 14 14.5 15 INPUT COMMON MODE VOLTAGE (V) FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28108, ISL28208 Pin Configurations Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) Coming Soon ISL28108FBZ 28108 FBZ -40 to +125 8 Ld SOIC M8.15E NC 1 Coming Soon ISL28108FRTZ 108Z -40 to +125 8 Ld TDFN L8.3x3A +IN 3 -IN 2 Coming Soon ISL28108FUZ 8108Z -40 to +125 8 Ld MSOP M8.118 ISL28208FBZ 28208 FBZ -40 to +125 8 Ld SOIC M8.15E ISL28208FRTZ 208Z -40 to +125 8 Ld TDFN L8.3x3A Coming Soon ISL28208FUZ 8208Z -40 to +125 8 Ld MSOP M8.118 - + V- 4 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. ISL28108 (8 LD MSOP, SOIC) TOP VIEW ISL28108 (8 LD TDFN) TOP VIEW PKG. DWG. # 8 NC NC 1 7 V+ -IN 2 6 VOUT +IN V- 5 NC 1 -IN_A 2 +IN_A 3 V- 4 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 8 V+ - + + - NC 7 V+ 3 6 VOUT 4 5 NC - + ISL28208 (8 LD SOIC, MSOP TOP VIEW ISL28208 (8 LD TDFN) TOP VIEW VOUT_A 8 VOUT _A 1 7 VOUT_B -IN_A 2 6 -IN_B +IN_A 3 5 +IN_B V- 4 8 V+ 7 VOUT_B - + + - 6 -IN_B 5 +IN_B 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28108, ISL28208. For more information on MSL please see techbrief TB363. Pin Descriptions ISL28108 ISL28108 ISL28208 ISL28208 (8 LD TDFN) (8 LD SOIC, MSOP) (8 LD TDFN) (8 LD SOIC, MSOP) PIN NAME EQUIVALENT CIRCUIT DESCRIPTION 3 3 +IN Circuit 1 Amplifier non-inverting input 2 2 -IN Circuit 1 Amplifier inverting input 3 3 +IN_A Circuit 1 Amplifier A non-inverting input 2 2 -IN_A Circuit 1 Amplifier A inverting input 6 6 1 1 VOUT_A Circuit 2 Amplifier A output 4 4 4 4 V- Circuit 3 Negative power supply 5 5 +IN_B Circuit 1 Amplifier B non-inverting input 6 6 -IN_B Circuit 1 Amplifier B inverting input 7 7 VOUT_B Circuit 2 Amplifier B output 8 8 V+ Circuit 3 Positive power supply NC - No internal connection PD - Thermal Pad. Pad has no internal connections and should be connected to a good AC ground. 7 7 1, 5, 8 1, 5, 8 PD V+ IN- V+ V+ CAPACITIVELY OUT IN+ TRIGGERED ESD V- V- CIRCUIT 1 CIRCUIT 2 2 VCIRCUIT 3 FN6935.1 March 17, 2011 ISL28108, ISL28208 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . Indefinite ESD Tolerance Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 6kV Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 400V Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld SOIC Package (108, 208, Notes 4, 6) . . 120 55 8 Ld TDFN Package (208, Notes 5, 6) . . . . . . 48 5.5 8 Ld MSOP Package (208, Notes 4, 6). . . . . . 150 45 Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . . -40°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V (±1.5V) to 40V (±20V) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. MIN PARAMETER VOS DESCRIPTION CONDITIONS Input Offset Voltage (Note 7) TYP MAX (Note 7) UNIT -230 25 230 µV 330 µV -330 TCVOS ΔVOS IB Input Offset Voltage Temperature Coefficient ISL28208 SOIC -40°C to +125°C 0.1 1.1 µV/°C ISL28208 TDFN -40°C to +125°C 0.2 1.4 µV/°C 5 300 µV 400 µV Input Offset Voltage Match (ISL28208 only) -300 Input Bias Current -43 -400 -13 nA -63 TCIB Input Bias Current Temperature Coefficient IOS Input Offset Current nA -3 0 -4 CMRR Common-Mode Rejection Ratio Common Mode Input Voltage Range 3 3 nA 4 nA VCM = V- -0.5V to V+ -1.8V 119 dB VCM = V- -0.2V to V+ -1.8V 123 dB 102 dB 105 123 dB 102 115 dB VCM = V- to V+ -1.8V VCMIR pA/°C 70 Guaranteed by CMRR test V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V FN6935.1 March 17, 2011 ISL28108, ISL28208 Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) MIN PARAMETER PSRR AVOL DESCRIPTION Power Supply Rejection Ratio Open-Loop Gain CONDITIONS VS = 3V to 40V, VCMIR = Valid Input Voltage VO = -13V to +13V, RL = 10kΩ to ground MAX (Note 7) (Note 7) TYP 110 128 dB 109 124 dB 117 126 dB 100 VOL VOH IS Output Voltage Low, VOUT to V- RL = 10kΩ Output Voltage High, V+ to VOUT RL = 10kΩ Supply Current/Amplifier RL = Open UNIT dB 52 85 mV 145 mV 110 mV 150 mV 185 250 µA 270 350 µA 70 ISC+ Output Short Circuit Source Current RL = 10Ω to V- 19 mA ISC- Output Short Circuit Sink Current RL = 10Ω to V+ 30 mA VSUPPLY Supply Voltage Range Guaranteed by PSRR 3 40 V AC SPECIFICATIONS GBWP Gain Bandwidth Product ACL = 101, VO = 100mVP-P, RL = 2kΩ 1.2 MHz enp-p Noise Voltage 0.1Hz to 10Hz; VS = +18V 580 nVP-P en Noise Voltage Density f = 10Hz; VS = +18V 18 nV/√Hz en Noise Voltage Density f = 100Hz; VS = +18V 16 nV/√Hz en Noise Voltage Density f = 1kHz; VS = +18V 15.8 nV/√Hz en Noise Voltage Density f = 10kHz; VS = +18V 15.8 nV/√Hz in Noise Current Density f = 10kHz; VS = +18V 80 fA/√Hz THD + N Total Harmonic Distortion + Noise 1kHz, AV = 1, VO = 3.5VRMS, RL =10kΩ 0.00042 % TRANSIENT RESPONSE SR Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩ, VO = 10VP-P 0.45 V/µs tr, tf, Small Signal Rise Time, VOUT 10% to 90% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 264 ns Fall Time, VOUT 90% to 10% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 254 ns Settling Time to 0.01% 10V Step; 10% to VOUT AV = -1, VOUT = 10VP-P, Rg = Rf =10k, RL = 2kΩ to VCM 27 µs ts 4 FN6935.1 March 17, 2011 ISL28108, ISL28208 Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. MIN PARAMETER VOS DESCRIPTION CONDITIONS Offset Voltage (Note 7) TYP MAX (Note 7) UNIT -230 25 230 µV 330 µV -330 TCVOS ΔVOS IB Input Offset Voltage Temperature Coefficient ISL28208 SOIC -40°C to +125°C 0.1 1.1 µV/°C ISL28208 TDFN -40°C to +125°C 0.2 1.4 µV/°C 3 300 µV 400 µV Input Offset Voltage Match (ISL28208 only) -300 Input Bias Current -43 -400 -15 nA -63 TCIB Input Bias Current Temperature Coefficient IOS Input Offset Current -40°C to +125°C nA -3 0 -4 CMRR Common-Mode Rejection Ratio PSRR AVOL nA nA 101 dB VCM = V- -0.2V to V+ -1.8V 123 dB 89 dB 105 123 dB 100 112 dB Common Mode Input Voltage Range Guaranteed by CMRR test Power Supply Rejection Ratio VS = 3V to 10V, VCMIR = Valid Input Voltage Open-Loop Gain 3 4 VCM = V- -0.5V to V+ -1.8V VCM = V- to V+ -1.8V VCMIR pA/°C -67 VO = -3V to +3V, RL = 10kΩ to ground V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V 110 126 dB 109 123 dB 117 124 dB 99 VOL VOH IS Output Voltage Low, VOUT to V- RL = 10kΩ Output Voltage High, V+ to VOUT RL = 10kΩ Supply Current/Amplifier RL = Open dB 23 38 mV 48 mV 65 mV 70 mV 165 250 µA 240 350 µA 30 ISC+ Output Short Circuit Source Current RL = 10Ω to V- 14 mA ISC- Output Short Circuit Sink Current RL = 10Ω to V+ 22 mA AC SPECIFICATIONS GBW Gain Bandwidth Product ACL = 101, VO = 100mVP-P, RL = 2kΩ 1.2 MHz enp-p Noise Voltage 0.1Hz to 10Hz 600 nVP-P en Noise Voltage Density f = 10Hz 18 nV/√Hz en Noise Voltage Density f = 100Hz 16 nV/√Hz en Noise Voltage Density f = 1kHz 15.8 nV/√Hz en Noise Voltage Density f = 10kHz 15.8 nV/√Hz in Noise Current Density f = 10kHz 90 fA/√Hz 5 FN6935.1 March 17, 2011 ISL28108, ISL28208 Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) MIN PARAMETER DESCRIPTION (Note 7) CONDITIONS TYP MAX (Note 7) UNIT TRANSIENT RESPONSE SR Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩ, VO = 4VP-P 0.4 V/µs tr, tf, Small Signal Rise Time, VOUT 10% to 90% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 264 ns Fall Time, VOUT 90% to 10% AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 254 ns Settling Time to 0.01% 4V Step; 10% to VOUT AV = -1, VOUT = 4VP-P, Rg = Rf =10k, RL = 2kΩ to VCM 14.4 µs ts NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. 300 300 VS = ±5V 200 150 100 50 0 250 200 150 100 50 0 VOS (µV) VOS (µV) FIGURE 4. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V VS = ±15V TCVOS (µV/C) FIGURE 5. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V 6 24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±5V -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS 24 22 20 18 16 14 12 10 8 6 4 2 0 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS FIGURE 3. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 NUMBER OF AMPLIFIERS 250 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 NUMBER OF AMPLIFIERS VS = ±15V TCVOS (µV/C) FIGURE 6. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V FN6935.1 March 17, 2011 ISL28108, ISL28208 24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±5V -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VS = ±15V NUMBER OF AMPLIFIERS 24 22 20 18 16 14 12 10 8 6 4 2 0 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 NUMBER OF AMPLIFIERS Typical Performance Curves TCVOS (µV/C) TCVOS (µV/C) FIGURE 7. ISL28208 TDFN TCVOS vs NUMBER OF AMPLIFIERS, VS = ±15V FIGURE 8. ISL28208 TDFN TCVOS vs NUMBER OF AMPLIFIERS, VS = ±5V 70 0 60 50 -5 40 30 20 10 0 VS = ±15V -10 -10 -15 -20 -30 -40 -50 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 500 100 -40°C +25°C 200 -100 -300 -400 -400 13.5 14 14.5 15 INPUT COMMON MODE VOLTAGE (V) FIGURE 11. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V 7 120 +25°C +125°C 0 -200 -14.5 -14 13 100 -100 -300 -15 -40°C 100 -200 -15.5 20 40 60 80 TEMPERATURE (°C) 300 +125°C 0 -500 -16 0 VS = ±5V 400 VOS (µV) VOS (µV) 200 -20 VS = ±1.5V FIGURE 10. IBIAS vs TEMPERATURE vs SUPPLY VS = ±15V 300 VS = ±2.25V -25 -40 120 FIGURE 9. VOS vs TEMPERATURE 400 VS = ±5V VS = ±20V -20 500 VS = ± 15V VS = ±5V IBIAS (nA) VOS (µV) VS = ±21V VS = ±2.25V -500 -6 -5.5 -5 -4.5 -4 3 3.5 4 4.5 5 INPUT COMMON MODE VOLTAGE (V) FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±5V FN6935.1 March 17, 2011 ISL28108, ISL28208 Typical Performance Curves 130 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 130 VS = ±15V CHANNEL-B 120 CHANNEL-A 115 110 105 120 CHANNEL-A 115 110 -20 0 20 40 60 80 TEMPERATURE (°C) 100 100 -40 120 FIGURE 13. CMRR vs TEMPERATURE, VS = ±15V 0 20 40 60 80 TEMPERATURE (°C) 100 120 120 110 100 90 PSRR+ 80 70 60 50 VS = ±5V, ±15V 40 AV = 1 30 CL = 4pF 20 RL = 10k PSRR10 VSOURCE = 1VP-P 0 10 100 1k 10k 100k FREQUENCY (Hz) 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 1M 10M FIGURE 16. PSRR vs FREQUENCY, VS = ±5V & ±15V FIGURE 15. CMRR vs FREQUENCY, VS = ±15V 140 140 VS = ±15V VS = ±5V 135 135 PSRR (dB) PSRR (dB) -20 FIGURE 14. CMRR vs TEMPERATURE, VS = ±5V PSRR (dB) 150 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 130 125 120 -40 CHANNEL-B 105 100 -40 CMRR (dB) VS = ±5V 125 CMRR (dB) CMRR (dB) 125 130 125 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 17. PSRR (DC) vs TEMPERATURE, VS = ±15V 8 120 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 18. PSRR (DC) vs TEMPERATURE, VS = ±5V FN6935.1 March 17, 2011 ISL28108, ISL28208 Typical Performance Curves 1 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 1 VS = ±5V and ±15V VS = ±5V and ±15V 125°C 125°C 0.1 VOL - V- (mV) V+ - VOH (mV) 0.1 +25°C 0.01 +25°C 0.01 -40°C 0.001 0.001 0.01 -40°C 0.1 LOAD CURRENT (µA) 1 10 FIGURE 19. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT, VS = ±5V and ±15V 0.001 0.001 5 13 125°C 12 10 +75°C 3 125°C 2 11 -40°C 10 -10 0°C -11 +25°C VS = ±15V AV = 2 RF = RG = 100k VIN = ±7.5V-DC -12 -13 -14 0 2 4 6 +75°C 8 -40°C 1 -1 VOL(V) VOL(V) 1 4 VOH(V) VOH(V) 14 10 12 14 16 18 20 22 -5 24 0°C -2 VS = ±5V A =2 -3 RV = R = 100k F G -4 VIN = ±2.5V-DC 0 2 4 6 I-FORCE (mA) 10 12 14 16 18 20 22 24 100 VS = ±15V 90 R = 10k L 80 VS = ±5V 90 R = 10k L 80 VOH AND VOL (mV) VOH (V+ TO VOUT) 70 60 50 40 VOL (VOUT TO V-) 30 60 50 40 30 20 10 10 0 20 40 60 80 TEMPERATURE (°C) FIGURE 23. VOUT HIGH & LOW vs TEMPERATURE, VS = ±15V, RL = 10k 9 100 120 VOH (V+ TO VOUT) 70 20 -20 8 FIGURE 22. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±5V 100 0 -40 +25°C I-FORCE (mA) FIGURE 21. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±15V VOH AND VOL (mV) 0.1 LOAD CURRENT (µA) FIGURE 20. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT, VS = ±5V and ±15V 15 -15 0.01 0 -40 VOL (VOUT TO V-) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 24. VOUT HIGH AND LOW vs TEMPERATURE, VS = ±5V, RL = 10k FN6935.1 March 17, 2011 ISL28108, ISL28208 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 50 50 VS = ±15V 45 R = 10k L 40 ISC-SINK 35 35 30 Isc (mA) Isc (mA) VS = ±5V 45 R = 10k L 40 25 20 15 25 20 15 10 10 ISC-SOURCE 5 0 -40 ISC-SINK 30 -20 0 20 40 5 60 80 100 ISC-SOURCE 0 -40 120 -20 0 20 TEMPERATURE (°C) 6 VS = ±15V AV = 1 100 120 4 INPUT 3 2 1 OUTPUT 0 -1 -2 -3 -4 -5 10k 100k FREQUENCY (Hz) -6 1M 120 VS = ±5V 110 -40 -20 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) FIGURE 29. AVOL vs TEMPERATURE 10 GAIN (dB), PHASE (°) VS = ± 15V 130 0 2 4 6 8 10 12 TIME (ms) 14 16 18 20 FIGURE 28. NO PHASE REVERSAL 140 AVOL (dB) 80 VS = ±5V VIN = ±5.9V 5 FIGURE 27. MAX OUTPUT VOLTAGE vs FREQUENCY 100 -60 60 FIGURE 26. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±5V INPUT AND OUTPUT (V) VOUT (VP-P) FIGURE 25. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±15V 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 1k 40 TEMPERATURE (°C) 200 180 160 140 120 100 80 60 40 20 0 GAIN -20 V = ±15V -40 S -60 RL = 1MΩ -80 SIMULATION -100 1 10 100 0.1 PHASE 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G FIGURE 30. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V FN6935.1 March 17, 2011 ISL28108, ISL28208 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 VSUPPLY (V) FIGURE 31. SUPPLY CURRENT vs SUPPLY VOLTAGE 70 60 RF = 10kΩ, RG = 100Ω 40 VS = ±5V, ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 101 30 20 ACL = 10 RF = 10kΩ, RG = 1.1kΩ 10 0 ACL = 1 -10 100 RF = 0, RG = ∞ 1k NORMALIZED GAIN (dB) 0 -1 -2 -3 RL = OPEN, 100k, 10k -4 RL = 1k -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 RL = 499 RL = 100 RL = 49.9 10k 100k 1M 10M -3 -4 RL = OPEN, 100k, 10k RL = 1k -5 -6 VS = ±5V -7 CL = 4pF AV = +1 -8 VOUT = 100mVp-p -9 1k 100 RL = 100 RL = 49.9 10k 100k 1M 10M FIGURE 34. GAIN vs FREQUENCY vs RL, VS = ±5V 1 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) RL = 499 FREQUENCY (Hz) FIGURE 33. GAIN vs FREQUENCY vs RL, VS = ±15V -2 -3 -4 VOUT = 10mVP-P -5 -9100 10M -2 FREQUENCY (Hz) -8 1M 1 -1 -7 100k FIGURE 32. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 0 -6 10k FREQUENCY (Hz) 1 NORMALIZED GAIN (dB) RF = 10kΩ, RG = 10Ω ACL = 1001 50 GAIN (dB) ISUPPLY PER AMPLIFIER (µA) Typical Performance Curves VS = ±5V VOUT = 50mVP-P CL = 4pF AV = +1 RL = INF VOUT = 100mVP-P 1k VOUT = 500mVP-P VOUT = 1VP-P 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 35. GAIN vs FREQUENCY vs OUTPUT VOLTAGE 11 -2 -3 VS = ±2.5V -4 VS = ±5V -5 -6 CL = 4pF R = 10k -7 L AV = +1 -8 VOUT = 100mVP-P -9 100 1k VS = ±15V VS = ±20V 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 36. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FN6935.1 March 17, 2011 ISL28108, ISL28208 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 100 100 VS = ±15V VS = ±5V G = 10 10 G = 10 10 G = 100 ZOUT (Ω) 1 0.10 0.01 0.10 G=1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10 INPUT NOISE VOLTAGE 1 1 INPUT NOISE CURRENT 0.1 0.1 0.01 0.1 1 10 100 1k 10k 100 0.01 100k 10M 100 10 10 INPUT NOISE VOLTAGE 1 1 INPUT NOISE CURRENT 0.1 0.01 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 0.01 100k 10k FIGURE 40. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±5V 1000 1000 VS = ±18V AV = 10k 800 600 INPUT NOISE VOLTAGE (nV) INPUT NOISE VOLTAGE (nV) 1M VS = ±5V FREQUENCY (Hz) FIGURE 39. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±18V 400 200 0 -200 -400 -600 -800 -1000 1k 10k 100k FREQUENCY (Hz) 100 INPUT NOISE VOLTAGE (nV/√Hz) 10 INPUT NOISE CURRENT (pA/√Hz) VS = ±18V 10 FIGURE 38. OUTPUT IMPEDANCE vs FREQUENCY, V S = ±5V 100 100 G=1 0.01 1 10M FIGURE 37. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V INPUT NOISE VOLTAGE (nV/√Hz) 1 INPUT NOISE CURRENT (pA/√Hz) ZOUT (Ω) G = 100 0 1 2 3 4 5 6 TIME (s) 7 8 9 10 FIGURE 41. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V 12 VS = ±5V AV = 10k 800 600 400 200 0 -200 -400 -600 -800 -1000 0 1 2 3 4 5 6 TIME (s) 7 8 9 10 FIGURE 42. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V FN6935.1 March 17, 2011 ISL28108, ISL28208 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 160 VS = ±15V CL = 4pF VTX = 1VP-P CROSSTALK (dB) 140 120 100 80 RL_TRANSMIT = ∞ RL_RECEIVE = 10k 60 40 RL_TRANSMIT = 2k 20 RL_RECEIVE = 10k 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 43. ISL28208 CHANNEL SEPARATION vs FREQUENCY, V S = ±5V, ±15V 16 -40 -4 -80 -8 12 OUTPUT 80 8 40 4 0 0 200 0 OUTPUT -120 -160 INPUT 20 40 60 80 100 120 TIME (µs) 140 160 180 INPUT (mV) 50 INPUT 40 30 3 OUTPUT 2 20 40 60 80 100 120 TIME (µs) 0 0 -1 -10 OUTPUT (V) 6 VS = ±5V AV = 100 5 RL = 10k VIN = 50mVP-P OVERDRIVE = 1V 4 60 20 -2 -20 OUTPUT -3 -30 -40 INPUT 1 -50 0 200 -60 10 0 0 20 40 60 80 100 120 TIME (µs) 140 160 180 FIGURE 46. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V 13 -12 VS = ±15V AV = 100 RL = 10k -16 VIN = 100mVP-P OVERDRIVE = 1V -20 140 160 180 200 FIGURE 45. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V FIGURE 44. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V INPUT (mV) 0 -200 0 OUTPUT (V) 120 0 0 20 40 60 80 100 120 TIME (µs) -4 VS = ±5V AV = 100 RL = 10k -5 VIN = 50mVP-P OVERDRIVE = 1V -6 140 160 180 200 OUTPUT (V) INPUT (mV) 160 20 INPUT (mV) VS = ±15V AV = 100 RL = 10k VIN = 100mVP-P OVERDRIVE = 1V INPUT OUTPUT (V) 200 FIGURE 47. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V FN6935.1 March 17, 2011 ISL28108, ISL28208 Typical Performance Curves OVERSHOOT (%) 50 60 VS = ±15V VOUT = 100mVP-P 50 OVERSHOOT (%) 60 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 40 AV = -1 30 AV = 1 AV = 10 20 40 30 AV = 10 20 0.010 0.100 1 10 0 0.001 100 0.010 LOAD CAPACITANCE (nF) 0.100 1 10 100 LOAD CAPACITANCE (nF) FIGURE 48. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V FIGURE 49. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V 2.4 6 VS = ±15V AV = 1 4 R = 2k L CL = 4pF 2 2.0 VS = ±5V AV = 1 1.6 RL = 2k 1.2 CL = 4pF 0.8 VOUT (V) VOUT (V) AV = -1 AV = 1 10 10 0 0.001 VS = ±5V VOUT = 100mVP-P 0 0.4 0 -0.4 -0.8 -2 -1.2 -1.6 -2.0 -2.4 -4 -6 0 100 200 TIME (µs) 300 400 FIGURE 50. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V 0 100 200 TIME (µs) 300 400 FIGURE 51. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V 100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 60 VOUT (mV) 40 20 0 -20 -40 -60 -80 -100 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 4.0 FIGURE 52. SMALL SIGNAL TRANSIENT RESPONSE VS = ±5V, ±15V 14 FN6935.1 March 17, 2011 ISL28108, ISL28208 Applications Information Functional Description The ISL28108 and ISL28208 are single and dual, 1.2MHz, single supply rail-to-rail output amplifiers with a common mode input voltage range extending to a range of 0.5V below the V- rail. Their input stages are optimized for precision sensing of ground referenced signals in low voltage, single supply applications. The input stage has the capability of handling large input differential voltages without phase inversion making them suitable for high voltage comparator applications. Their bipolar design features high open loop gain and excellent DC input and output temperature stability. These op amps feature low quiescent current of 165µA, and a maximum low temperature drift of only 1.1µV/°C for the SOIC package and 1.4µV/°C for the TDFN package (see Figures 7 and 8). Both devices are fabricated in a new precision 40V complementary bipolar DI process and immune from latch-up. Operating Voltage Range The devices are designed to operate over the 3V (±1.5V) to 40V (±20V) range and are fully characterized at ±5V and ±15V. Both DC and AC performance remain virtually unchanged over the ±5V to ±15V operating voltage range. Parameter variation with operating voltage is shown in the “Typical Performance Curves” beginning on page 6. Input Stage Performance The ISL28108 and ISL28208 PNP input stage has a common mode input range extending up to 0.5V below ground at +25°C (see Figures 11 and 12). Full amplifier performance is guaranteed down to ground (V-) over the -40°C to +125°C temperature range. For common mode voltages down to -0.5V the amplifiers are fully functional, but performance degrades slightly over the full temperature range. This feature provides excellent CMRR, AC performance and DC accuracy when amplifying low level ground referenced signals. The input stage has a maximum input differential voltage equal to a diode drop greater than the supply voltage (max 42V) and does not contain the back-to-back input protection diodes found on many similar amplifiers. This feature enables the device to function as a precision comparator by maintaining very high input impedance for high voltage differential input comparator voltages. The high differential input impedance also enables the device to operate reliably in large signal pulse applications without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. Thus, input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. V+ VINVIN+ RIN- - RIN+ + RG RF RL V- FIGURE 53. INPUT ESD DIODE CURRENT LIMITING Output Drive Capability The bipolar rail-to-rail output stage features low saturation levels that enable an output voltage swing to less than 10mV when the total output load (including feedback resistance) is held below 50µA (Figures 19 and 20). With ±15V supplies this can be achieved by using feedback resistor values >300kΩ. The low input bias and offset currents (-43nA and ±3nA +25°C max respectively) minimize DC offset errors at these high resistance values. For example, a balanced 4 resistor gain circuit (Figure 53) with 1MΩ feedback resistors (RF, RG) generates a worst case input offset error of only ±3mV. Furthermore, the low noise current reduces the added noise associated with high feedback resistance. The output stage can swing at moderate levels of output current (Figures 21 and 22) and the output stage is internally current limited. Output current limit over-temperature is shown in Figures 25 and 26. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long term reliability. The amplifiers perform well driving capacitive loads (Figures 48 and 49). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth, but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 30% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28108 and ISL28208 are immune to output phase reversal, out to 0.5V beyond the rail (VABS MAX) limit (see Figure 28). In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current limiting resistors may be needed at each input terminal (see Figure 53 RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA. 15 FN6935.1 March 17, 2011 ISL28108, ISL28208 Using Only One Channel ISL28108 and ISL28208 SPICE Model The ISL28208 is a dual op-amp. If the application only requires one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation, is to short the output to the inverting input and ground the positive input (as shown in Figure 54). Figure 56 shows the SPICE model schematic and Figure 57 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The DC parameters are IOS, total supply current and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” Table beginning on page 3. The AVOL is adjusted for 122dB with the dominant pole at 1Hz. The CMRR is set 128dB, f = 6kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25°C. + FIGURE 54. PREVENTING OSCILLATIONS IN UNUSED CHANNELS Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: (EQ. 1) T JMAX = T MAX + θ JA xPD MAXTOTAL where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × -----------------------R (EQ. 2) L where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier Figures 58 through 72 show the characterization vs simulation results for the Noise Voltage, Open Loop Gain Phase, Closed Loop Gain vs Frequency, Gain vs Frequency vs RL, CMRR, Large Signal 10V Step Response, Small Signal 0.05V Step and Output Voltage Swing ±15V supplies. LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macromodel, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macromodel to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance 16 FN6935.1 March 17, 2011 V++ V++ DX I1 D3 G1 + R5 13 GAIN = 0.477 12e-6 I2 6E-6 I3 6E-6 Vin- 9 Q7 7 DN D14 PNP_LATERAL 5 CinDif 1.21e-12 R1 5e11 2 + + - 1150 DN 17 0 R2 D13 Q8 PNP_input Q9 D2DBREAK PNP_input 8 IOS 3e-9 0 14 PNP_LATERAL 12 EOS ++ -E Vc Vmid GAIN = 1 11 R3 15 G2 6250 6 GAIN = 0.3 V-- 4.19e-12 DX Vmid GAIN = 261.74e-6 -6.74 V++ L1 L3 1.59E-08 1.59E-08 G5 G7 + + 18 21 GAIN = 0.6 R9 GAIN = 0.6 1e-3 R11 1e-3 19 C1 R7 2.31e-11 7.62e9 V3 Vg V++ R19 R13 3.183e3 3.183e3 G15 G9 + + GAIN = 314.15e-6 GAIN = 314.15e-6 28 Vc G13 D11 GAIN = 12.5e-3 D7 C3 DX 10e-12 C5 10e-12 D10 DX 16 V+ E2 ++ - GAIN = 1 1st Gain Stage DX G3 + - D5 D4 V-- Input Stage 0 1 24 -0.4 23 R15 80 V5 26 VOUT 27 Vmid L2 1.59E-08 GAIN = 0.6 V-- FN6935.1 March 17, 2011 Mid Supply ref V G10 C4 10e-12 GAIN = 314.15e-6 GAIN = 314.15e-6 L4 R14 1.59E-08 R20 3.183e3 3.183e3 G11 + D9 GAIN = 12.5e-3 -0.4 G12 + - D12 GAIN = 12.5e-3 V-V- 2nd Gain Stage V6 25 DY + DX 22 G8 GAIN = 0.6 G16 DY 20 G6 + - GAIN = 261.74e-6 C2 2.31e-11 R8 7.62e9 + - 17 R12 1e-3 + - Vmid R10 1e-3 + - G4 V4 D8 DX -6.76 C6 10e-12 E4 ++ -GAIN = 0.5 Common Mode Gain Stage with Zero E3 ++ -GAIN = 1 0 FIGURE 55. SPICE NET LIST Output Stage Correction CurrentSources G14 + - ISY 185e-6 GAIN = 12.5e-3 R16 80 ISL28108, ISL28208 4.19e-12 R6 GAIN = 0.477 Cin1 DX Cin2 V2 -6.76 R4 6250 Vin+ 10 + - V7 1 V1 -6.74 D1DBREAK Q6 + - 0.1 1 ISL28108, ISL28208 *ISL28108_208 Macromodel - covers following *products *ISL28108 *ISL28208 * *Revision History: * Revision A, LaFontaine March 5th 2011 * Model for Noise, supply currents, CMRR *128dB f=6kHz ,AVOL 122dB f=1Hz * SR = 0.45V/us, GBWP 1.2MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet "LICENSE STATEMENT" *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages. * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging source, *Load current reflected into the power supply *current. * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | .subckt ISL28108_208 Vin+ Vin-V+ V- VOUT * source ISL28118_218_subckt_check_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 R_R17 2 0 1150 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 12e-6 I_I2 V++ 7 DC 6E-6 I_I3 V++ 10 DC 6E-6 I_IOS 6 VIN- DC 3e-9 *D_D1 7 10 DBREAK *D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 6250 R_R4 V-- 11 6250 C_Cin1 V-- VIN- 4.19e-12 C_Cin2 V-- 6 4.19e-12 C_CinDif 6 VIN- 1.21E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.4779867 G_G2 V-- 14 8 11 0.4779867 V_V1 13 14 -6.74 V_V2 14 15 -6.76 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 261.748e-6 G_G4 V-- VG 14 VMID 261.748e-6 V_V3 16 VG -6.74 V_V4 VG 17 -6.76 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 7.62283e9 R_R8 V-- VG 7.62283e9 C_C1 VG V++ 2.31e-11 C_C2 V-- VG 2.31e-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 185E-6 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 0.6 G_G6 V-- 19 5 VMID 0.6 G_G7 V++ VC 19 VMID 0.6 G_G8 V-- VC 19 VMID 0.6 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 1.59159E-08 L_L2 20 V-- 1.59159E-08 L_L3 21 V++ 1.59159E-08 L_L4 22 V-- 1.59159E-08 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Satge G_G15 V++ 28 VG VMID 314.15e-6 G_G16 V-- 28 VG VMID 314.15e-6 R_R19 28 V++ 3.18319e3 R_R20 V-- 28 3.18319e3 C_C5 28 V++ 10e-12 C_C6 V-- 28 10e-12 * G_G9 V++ 23 28 VMID 314.15e-6 G_G10 V-- 23 28 VMID 314.15e-6 R_R13 23 V++ 3.18319e3 R_R14 V-- 23 3.18319e3 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28108_208 FIGURE 56. SPICE NET LIST 18 FN6935.1 March 17, 2011 ISL28108, ISL28208 Characterization vs Simulation Results 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 57. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 58. SIMULATED INPUT NOISE VOLTAGE 200 70 60 30 20 ACL = 10 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω 50 VS = ±5V, ±15V CL = 4pF RL = 2k VOUT = 100mVP-P 40 30 20 10 ACL = 1 -10 100 0.1 60 RF = 10kΩ, RG = 1.1kΩ 10 VS = ±15V RL = 1MΩ SIMULATION 70 VS = ±5V, ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 101 GAIN 0 FIGURE 60. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY RF = 10kΩ, RG = 100Ω 50 40 50 -100 10M 100M 1G RF = 10kΩ, RG = 10Ω ACL = 1001 100 -50 1k 10k 100k 1M FREQUENCY (Hz) PHASE 150 PHASE GAIN (dB), PHASE (°) 200 180 160 140 120 100 80 60 40 20 0 GAIN -20 V = ±15V -40 S -60 RL = 1MΩ -80 SIMULATION -100 0.1 1 10 100 FIGURE 59. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY GAIN (dB) 10 0.1 GAIN (dB) GAIN (dB), PHASE (°) 10 0.1 RF = 10kΩ, RG = 1.1kΩ 0 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 61. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY 19 -10 100 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 62. SIMULATED CLOSED LOOP GAIN vs FREQUENCY FN6935.1 March 17, 2011 ISL28108, ISL28208 Characterization vs Simulation Results (Continued) 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 -2 -3 -4 RL = OPEN, 100k, 10k RL = 1k -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 RL = 499 RL = 100 RL = 49.9 10k 100k 1M 10M -2 -3 RL = OPEN, 100k, 10k -4 RL = 1k -5 -6 VS = ±15V -7 CL = 4pF AV = +1 -8 VOUT = 100mVP-P -9 1k 100 FREQUENCY (Hz) CMRR (dB) CMRR (dB) 1M 10M 100 50 0 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 1m 0.01 0.1 6 2 0 0 -2 -2 -4 -4 300 400 FIGURE 67. CHARACTERIZED LARGE SIGNAL 10V STEP RESPONSE 20 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VS = ±15V AV = 1 RL = 2k CL = 4pF 4 200 TIME (µs) 1 FIGURE 66. SIMULATED CMRR vs FREQUENCY VOUT (V) VOUT (V) 100k VS = ±15V SIMULATION VS = ±15V AV = 1 4 R = 2k L CL = 4pF 2 100 10k 150 6 0 RL = 49.9 FIGURE 64. SIMULATED GAIN vs FREQUENCY vs RL FIGURE 65. CHARACTERIZED CMRR vs FREQUENCY -6 RL = 100 FREQUENCY (Hz) FIGURE 63. CHARACTERIZED GAIN vs FREQUENCY vs RL 150 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 RL = 499 -6 0 100 200 TIME (µs) 300 400 FIGURE 68. SIMULATED LARGE SIGNAL 10V STEP RESPONSE FN6935.1 March 17, 2011 ISL28108, ISL28208 Characterization vs Simulation Results (Continued) 100 100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 60 VOUT (mV) 40 20 60 40 0 -20 20 0 -20 -40 -40 -60 -60 -80 -80 -100 -100 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 VOUT (mV) 80 4.0 0 0.5 1.0 1.5 2.0 2.5 TIME (µs) 3.0 3.5 4.0 FIGURE 70. SIMULATED SMALL SIGNAL TRANSIENT RESPONSE FIGURE 69. CHARACTERIZED SMALL SIGNAL TRANSIENT RESPONSE OUTPUT VOLTAGE SWING (V) 20V VOH = 14.93V 10V 0V -10V VOL = -14.94V -20V 0 0.5 1.0 TIME (m s) 1.5 2.0 FIGURE 71. SIMULATED OUTPUT VOLTAGE SWING 21 FN6935.1 March 17, 2011 ISL28108, ISL28208 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 3/11/11 FN6935.1 On page 1, in the first paragraph - added the following after V-rail: "a rail-to-rail differential input voltage range for use as a comparator,…" On page 1 in “Features: Added bullet - “Rail-to-rail Input Differential Voltage Range for Comparator Applications” Changed Low Noise Current from "100fA/sq.root Hz" to "80fA/sq.root Hz" On page 2 in “Ordering Information” - Removed "coming soon" from ISL28208FRTZ part since it is releasing. On page 3, changed “ESD Tolerance” as follows: Human Body Model changed from "3kV" to "6kV" Machine Model changed from "300V" to "400V" Added JEDEC Test information for all ESD ratings On page 3 and page 5, added test conditions for SOIC TCVos specs. Added TCVos specs for TDFN. On page 4 changed “Noise Current Density” Typical from "100" to "80" On page 15, updated Applications Information Functional Description On page 15 Updated Input Stage Performance Section On page 15 Updated Output Drive Capability Section On page 16 Added ISL28108 AND ISL28208 SPICE MODEL and License Agreement section On page 17 Added SPICE NET LIST On page 19 Added Characterization vs Simulation Results curves 2/16/11 FN6935.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28108, ISL28208 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 FN6935.1 March 17, 2011 ISL28108, ISL28208 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 23 FN6935.1 March 17, 2011 ISL28108, ISL28208 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 ( 1.95) A B 3.00 ( 8X 0.50) 6 PIN 1 INDEX AREA (4X) (1.50) ( 2.90 ) 0.15 PIN 1 TOP VIEW (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL "X" 2X 1.950 PIN #1 INDEX AREA 0.10 C 0.75 ±0.05 6X 0.65 C 0.08 C 1 SIDE VIEW 6 1.50 ±0.10 8 8X 0.30 ±0.05 8X 0.30 ± 0.10 2.30 ±0.10 C 4 0.10 M C A B 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" BOTTOM VIEW NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. either a mold or mark feature. 24 FN6935.1 March 17, 2011 ISL28108, ISL28208 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 25 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. FN6935.1 March 17, 2011