HMU17/883 16 x 16-Bit CMOS Parallel Multiplier October 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HMU17/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier ideal for fast, real time digital signal processing applications. The 16-bit X and Y operands may be independently specified as either two’s complement or unsigned magnitude format, thereby allowing mixed mode multiplication operations. • 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product • High-Speed (45ns) Clocked Multiply Time • Low Power CMOS Operation - ICCSB = 500µA Maximum - ICCOP = 7.0mA Maximum at 1MHz • HMU17/883 is Compatible with the AM29517, LMU17, IDT7217, and the CY7C517 • Supports Two’s Complement, Unsigned Magnitude and Mixed Mode Multiplication • TTL Compatible Inputs/Outputs - Three-State Output Ordering Information PART NUMBER TEMP. RANGE (oC) HMU17GM-45/883 -55 to 125 68 Ld PGA HMU17GM-60/883 -55 to 125 68 Ld PGA PACKAGE PKG. NO. Additional inputs are provided to accommodate format adjustment and rounding of the 32-bit product. The Format Adjust control allows the user the option of selecting a 31-bit product with the sign bit replicated LSP. The Round control is provided to accommodate rounding of the most significant portion of the result. This is accomplished by adding one to the most significant bit of the LSP. Two 16-bit output registers (MSP and LSP) are provided to hold the most and least significant portions of the result, respectively. These registers may be made transparent for asynchronous operation through the use of the Feedthrough Control (FT). The two halves of the product may be routed to a single 16-bit threestate output port via the output multiplexer control, and in addition, the LSP is connected to the Y-input port through a separate three-state buffer. The HMU17/883 utilizes a single clock signal (CLK) along with three register enables (ENX, ENY, and ENP) to latch the input operands and the output product registers. The ENX and ENY inputs enable the X and Y input registers, while ENP enables both the LSP and MSP output registers. This configuration facilitates the use of the HMU17/883 for micro-programmed systems. All outputs of the HMU17/883 also offer three-state control for multiplexing onto multiuse system busses. Functional Block Diagram X0-15 TCX RND TCY Y0-15/P0-15 REGISTER REGISTER REGISTER OEL CLK ENX ENY MULTIPLIER ARRAY FA FT FORMAT ADJUST MSP REGISTER LSP REGISTER ENP MULTIPLEXER MSPSEL OEP P16-31/P0-15 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 3-36 File Number 2805.2 HMU17/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Input or Output Voltage Applied . . . . . . . . . GND 0.5V to VCC +0.5V ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Package Power Dissipation at 125 PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.17 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Die Characteristics Number of Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4,500 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Output HIGH Voltage VOH IOH = 400µA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 2.6 - V Output LOW Voltage VOL IOL = +4.0mA VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 - 0.4 V Input Leakage Current II VIN = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Output or I/O Leakage Current IO VOUT = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Standby Power Supply Current ICCSB VIN = VCC or GND, VCC = 5.5V, Outputs Open 1, 2, 3 -55 ≤ TA ≤ 125 - 500 µA Operating Power Supply Current ICCOP f = 1.0 MHz, VIN = VCC or GND VCC = 5.5V (Note 3) 1, 2, 3 -55 ≤ TA ≤ 125 - 7.0 mA 7, 8 -55 ≤ TA ≤ 125 - - Functional Test FT (Note 4) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 5mA/MHz. 4. Tested as follows: f = 1MHz, VIH (Clock Inputs) = 3.0, VIH (All other inputs) = 2.6, VIL = 0.4, VOH ≥ 1.5V, and VOL ≤ 1.5V. 3-37 HMU17/883 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTE 1) CONDITIONS GROUP A SUBGROUP S -45 -60 TEMPERATURE (oC) MIN MAX MIN MAX UNITS PARAMETER SYMBOL Unclocked Multiply Time t MUC 9, 10, 11 -55 ≤ TA ≤ 125 - 70 - 90 ns Clocked Multiply Time tMC 9, 10, 11 -55 ≤ TA ≤ 125 - 45 - 60 ns X, Y, RND Setup Time tS 9, 10, 11 -55 ≤ TA ≤ 125 18 - 20 - ns Clock HIGH Pulse Width tPWH 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns Clock LOW Pulse Width tPWL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns MSPSEL to Product Out tPDSEL 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Output Clock to P tPDP 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Output Clock to Y tPDY 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Three-State Enable Time tENA 9, 10, 11 -55 ≤ TA ≤ 125 - 25 - 30 ns Clock Enable Setup tSE 9, 10, 11 -55 ≤ TA ≤ 125 15 - 15 - ns (Note 6) NOTES: 5. AC Testing as follows: VCC = 4.5V and 5.5V. Input levels 0V and 3.0V; Timing reference levels = 1.5V; output load per test load circuit, with V1 = 2.4V, R1 = 500Ω and CL = 40pF. 6. Transition is measured at ±200mV from steady state voltage, output loading per test load circuit, with V1 = 1.5V, R1 = 500Ω and CL = 40pF. TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS -45 PARAMETER Input Capacitance Output Capacitance I/O Capacitance SYMBOL CIN COUT CI/O CONDITIONS VCC = Open, f = 1MHz All Measurements are referenced to device GND. -60 NOTES TEMPERATURE (oC) MIN MAX MIN MAX UNITS 7 TA = 25 - 15 - 15 pF 7 TA = 25 - 10 - 10 pF 7 TA = 25 - 10 - 10 pF X, Y, RND Hold Time tH 7, 8 -55 ≤ TA ≤ 125 3 - 3 - ns Three-State Disable Time tDIS 7, 8, 9 -55 ≤ TA ≤ 125 - 25 - 30 ns Clock Enable Hold Time tHE 7, 8, 9 -55 ≤ TA ≤ 125 3 - 3 - ns Output Rise Time tR From 0.8V to 2.0V 7, 8, 10 -55 ≤ TA ≤ 125 - 10 - 10 ns Output Fall Time tF From 2.0V to 0.8V 7, 8, 10 -55 ≤ TA ≤ 125 - 10 - 10 ns NOTES: 7. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 8. Guaranteed, but not 100% tested. 9. Transition is measured at ±200mV from steady state voltage; output loading per test load circuit; with V1 = 1.5V, R1 = 500Ω and CL = 40pF. 10. Loading is as specified in the test load circuit, with V1 = 2.4V, R1 = 500Ω and CL = 40pF. 3-38 HMU17/883 TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C & D 3-39 HMU17/883 Burn-In Circuit 11 N/C X13 X15 RND TCY VCC GND FT OEP X14 (ENX) TCX VCC GND MSP SEL FA (ENP) N/C 10 X11 X12 9 X9 X10 P30/ P14 P31/ P15 8 X7 X8 P28/ P12 P29/ P13 7 X5 X6 P26/ P10 P27/ P11 6 X3 X4 P24/ P8 P25/ P9 5 X1 X2 P22/ P6 P23/ P7 4 OEL X0 P20/ P4 P21/ P5 3 (ENY) CLK P18/ P2 P19/ P3 2 N/C Y0/P0 Y2/P2 Y4/P4 Y6/P6 Y8/P8 Y10/ P10 Y12/ P12 Y14/ P14 P16/ P0 P17/ P1 Y1/P1 Y3/P3 Y5/P5 Y7/P7 Y9/P9 Y11/ P11 Y13/ P13 Y15/ P15 N/C G H J K 68 LEAD PIN GRID ARRAY TOP VIEW 1 A B C D E F L PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL B6 X4 F6 F1 Y9/P9 F11 K7 P10/P26 VCC/2 E11 RND F1 A6 X3 F5 G2 Y10/P10 F12 L7 P11/P27 VCC/2 D10 ENX F0 B5 X2 F4 G1 Y11/P11 F13 K8 P12/P28 VCC/2 D11 X15 F3 A5 X1 F3 H2 Y12/P12 F14 L8 P13/P29 VCC/2 C10 X14 F2 B4 X0 F2 H1 Y13/P13 F15 K9 P14/P30 VCC/2 C11 X13 F15 A4 OEL VCC J2 Y14/P14 F4 L9 P15/P31 VCC/2 B10 X12 F14 B3 CLK F0 J1 Y15/P15 F5 K10 ENP F0 A10 X11 F13 A3 ENY F0 K2 P0/P16 VCC/2 K11 OEP F1 B9 X10 F12 B2 Y0/P0 F2 L2 P1/P17 VCC/2 J10 FA F14 A9 X9 F11 B1 Y1/P1 F3 K3 P2/P18 VCC/2 J11 FT F15 B8 X8 F10 C2 Y2/P2 F4 L3 P3/P19 VCC/2 H10 MSPSEL F14 A8 X7 F9 C1 Y3/P3 F5 K4 P4/P20 VCC/2 H11 GND GND B7 X6 F8 D2 Y4/P4 F6 L4 P5/P21 VCC/2 G10 GND GND A7 X5 F7 D1 Y5/P5 F7 K5 P6/P22 VCC/2 G11 VCC VCC A2 N.C. NONE E2 Y6/P6 F8 L5 P7/P23 VCC/2 F10 VCC VCC K1 N.C. NONE E1 Y7/P7 F9 K6 P8/P24 VCC/2 F11 TCY F15 L10 N.C. NONE F2 Y8/P8 F10 L6 P9/P25 VCC/2 E10 TCX F15 B11 N.C. NONE NOTES: 11. VCC = 5.0V +0.5V/-0.0V with 0.1µF decoupling capacitor to GND. 12. F0 = 100kHz, F1 = F0/2, F2 = F1/2, . . . . . . . . . 13. VIH = VCC 1V ±0.5V (Min), VIL = 0.8V (Max). 14. 47kΩ load resistors used on all pins except VCC and GND (Pin Grid identifiers F10, G10, G11 and H11). 3-40 HMU17/883 Die Characteristics DIE DIMENSIONS: GLASSIVATION: 179 mils x 169 mils x 19 ± 1 mil Type: Nitrox Thickness: 10kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: Si-Al or Si-Al-Cu Thickness: 8kÅ 1.2 x 105 A/cm2 Metallization Mask Layout (57) X12 (58) X11 (59) X10 (60) X9 (61) X8 (62) X7 (63) X6 (64) X5 (1) X4 (2) X3 (3) X (4) X1 (5) XO (6) OEL (8) CLKY (ENY) (7) CLKL (CLK) HMU17/883 (56) x 13 (55) x 14 (9) YO, P0 (54) x 15 (10) Y1, P1 (53) CLKX (ENX) (11) Y2, P2 (52) RND (12) Y3, P3 (51) TCX (13) Y4, P4 (50) TCY (14) Y5, P5 (15) Y6, P6 (49) VCC (16) Y7, P7 (48) VCC (17) Y8, P8 (18) Y9, P9 (47) GND (19) Y10, P10 (20) Y11, P11 (46) GND (21) Y12, P12 (45) MSPSEL (22) Y13, P13 (44) FT (23) Y14, P14 (43) FA (24) Y15, P15 (42) DEP (40) P15, P31 (39) P14, P30 (38) P13, P29 (37) P12, P28 (36) P11, P27 (35) P10, P26 (34) P9, P25 (33) P8, P24 (32) P7, P23 (31) P6, P22 (30) P5, P21 (29) P4, P20 (28) P3, P19 (27) P2, P18 (26) P1, P17 (25) P0, P16 (41) CLKM (END) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-41