T UCT PROD E PRODUC E T E T L U O IL S IT S T OB SUBS -888-INTER IBLE Sheet SData s1 S n o O i t P .com a FOR A ntral Applic pp@intersil a e call C email: cent or HSP48908/883 TM December 1999 FN2783.5 Two Dimensional Convolver Features The Intersil HSP48908/883 is a high speed Two Dimensional Convolver which provides a single chip implementation of a video data rate 3 x 3 kernel convolution on two dimensional data. It eliminates the need for external data storage through the use of the on-chip row buffers which are programmable for row lengths up to 1024 pixels. • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. There are internal register banks for storing two independent 3 x 3 filter kernels, thus, facilitating the implementation of adaptive filters and multiple filter operations on the same data. The pixel data path also includes an on-chip ALU for performing real-time arithmetic and logical pixel point operations. • DC to 27MHz Clock Rate Data is provided to the HSP48908/883 in a raster scan noninterlaced fashion, and is internally buffered on images up to 1024 pixels wide for the 3 x 3 convolution operation. Images with larger rows and convolution with larger kernel sizes can be accommodated by using external row buffers and/or multiple HSP48908/883s. Coefficient and pixel input data are 8-bit signed or unsigned integers, and the 20-bit convolver output guarantees no overflow for kernel sizes up to 4 x 4. Larger kernel sizes can be implemented however, since the filter coefficients will normally be less than their maximum 8-bit values. • 8-Bit Signed or Unsigned Input and Coefficient Data The HSP48908/883 is manufactured using an advanced CMOS process, and is a low power fully static design. The configuration of the device is controlled through a standard microprocessor interface and all inputs/outputs are TTL compatible. 1 • Single Chip 3 x 3 Kernel Convolution • Programmable On-Chip Row Buffers • Cascadable for Larger Kernels and Images • On-Chip 8-Bit ALU • Dual Coefficient Mask Registers, Switchable in a Single Clock Cycle • 20-Bit Extended Precision Output • Standard µP Interface Applications • Image Filtering • Edge Detection • Adaptive Filtering • Real Time Video Filter Ordering Information PART NUMBER TEMP. RANGE (oC) HSP48908GM-20/883 -55 to 125 84 Ld CPGA G84.A HSP48908GM-27/883 -55 to 125 84 Ld CPGA G84.A PACKAGE PKG. NO. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HSP48908/883 Pinout 84 PIN PGA TOP VIEW 11 CASO6 DOUT0 DOUT1 GND DOUT5 DOUT6 DOUT8 10 CASO4 CASO5 CASO7 DOUT2 DOUT4 DOUT9 GND 9 CASO3 GND DOUT3 DOUT7 VCC 8 CASO1 CASO2 7 OE GND VCC 6 DIN1 CASO0 5 DIN2 DIN3 4 DIN5 DIN6 3 DIN7 CIN1 2 CIN0 CIN3 CIN4 1 CIN2 CIN5 A B 2 DOUT10 DOUT12 DOUT13 DOUT15 DOUT11 DOUT14 GND DOUT17 DOUT16 DOUT18 DOUT19 GND CASI1 FRAME CASI0 DIN0 CASI2 VCC RESET DIN4 CASI5 CASI4 CASI3 CASI7 CASI6 CASI10 CASI8 CASI9 CIN9 HOLD LD CIN7 GND VCC A2 EALU CASI13 CASI11 CIN6 CIN8 CLK A1 CS A0 CASI15 CASI14 CASI12 C D E F G H J K L HSP48908/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V θJA (oC/W) θJC (oC/W) PGA Package . . . . . . . . . . . . . . . . . . 35.0 6.0 Maximum Package Power Dissipation at 125oC PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.45W Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Die Characteristics Number of Transistors or Gates . . . . . . . . . . . . 190,000 Transistors CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROU P TEMPERATURE (oC) MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Clock Input High VIHC VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 3.0 - V Clock Input Low VILC VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Output HIGH Voltage VOH IOH = 400mA, VCC = 4.75V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 2.6 - V Output LOW Voltage VOL IOL = +2.0mA, VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 - 0.4 V Input Leakage Current II VIN = VCC or GND, VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Output or I/O Leakage Current IO VOUT = VCC or GND VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 +10 µA Standby Power Supply Current ICCSB VIN = VCC or GND, VCC = 5.5V, Outputs Open (Note 5) 1, 2, 3 -55 ≤ TA ≤ 125 - 500 µA Operating Power Supply Current ICCOP f = 20.0MHz, VCC = 5.5V Outputs Open, (Note 3, 5) 1, 2, 3 -55 ≤ TA ≤ 125 - 160.0 mA 7, 8 -55 ≤ TA ≤ 125 - - - Functional Test FT (Notes 4, 5) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8.0mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH ≥ 1.5V, VOL ≤ 1.5V, VIHC = 3.4V, and VILC = 0.4V. 5. Loading is as specified in the test load circuit with CL = 40pF. 3 HSP48908/883 TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VCC = 5.0V ±10%, TA = -55oC to 125oC (Note 9) -27 (27MHz) -20 (20MHz) GROUP A SUBGROUP TEMP (oC) MIN MAX MIN MAX UNITS tCYCLE 9, 10, 11 -55 ≤ TA ≤ 125 37 - 50 - ns Clock Pulse Width High tPWH 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns Clock Pulse Width Low tPWL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns Data Input Setup Time tDS 9, 10, 11 -55 ≤ TA ≤ 125 16 - 17 - ns Data Input Hold Time tDH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns Clock to Data Out tOUT 9, 10, 11 -55 ≤ TA ≤ 125 - 19 - 28 ns Address Setup Time tAS 9, 10, 11 -55 ≤ TA ≤ 125 15 - 15 - ns Address Hold Time tAH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns Configuration Data Setup Time tCDS 9, 10, 11 -55 ≤ TA ≤ 125 17 - 20 - ns Configuration Data Hold Time tCDH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns LD Pulse Width tLPW 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns LD Setup Time tLCS 9, 10, 11 -55 ≤ TA ≤ 125 30 - 37 - ns CIN7-0 Setup to CLK tCS 9, 10, 11 -55 ≤ TA ≤ 125 17 - 20 - ns CIN7-0 Hold to CLK tCH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns CS Setup to LD tCSS 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns CS Setup to LD tCSH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns RESET Pulse Width tRPW 9, 10, 11 -55 ≤ TA ≤ 125 37 - 50 - ns 9, 10, 11 -55 ≤ TA ≤ 125 25 - 30 - ns tFPW 9, 10, 11 -55 ≤ TA ≤ 125 37 - 50 - ns EALU Setup Time tES 9, 10, 11 -55 ≤ TA ≤ 125 15 - 17 - ns EALU Hold Time tEH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns HOLD Setup Time tHS 9, 10, 11 -55 ≤ TA ≤ 125 13 - 14 - ns HOLD Hold Time tHH 9, 10, 11 -55 ≤ TA ≤ 125 2 - 2 - ns Output Enable Time tEN 9, 10, 11 -55 ≤ TA ≤ 125 - 19 - 28 ns PARAMETER Clock Period FRAME Setup to Clock FRAME Pulse Width SYMBOL NOTES Note 6 tFS Note 7 Note 8 NOTES: 6. This specification applies only to the case where the HSP48908/883 is being written to during an active convolution cycle. It must be met in order to achieve predictable results at the next rising clock edge. In most applications, the configuration data and coefficients are loaded asynchronously and the t LCS Specification may be disregarded. 7. While FRAME is an asynchronous signal, it must be deasserted a minimum of tFS ns prior to the rising clock edge which is to begin loading pixel data for a new frame. 8. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with CL = 40pF. 9. AC Testing is performed as follows: Input levels (CLK input) 4.0V and 0V, input levels (all other inputs) 0V and 3.0V, timing reference levels (CLK) = 2.0V, (others) = 1.5V. Output load per test load circuit with CL = 40pF. Output transition is measured at VOH ≥ 1.5V and VOL ≤ 1.5V. 4 HSP48908/883 TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETERS SYMBOL CONDITIONS -27 -20 NOTES TEMP (oC) MIN MAX MIN MAX UNITS Input Capacitance C IN VCC = Open f = 1MHz, all measurements are referenced to device GND 10 TA = 25 - 10 - 10 pF Output Capacitance CO VCC = Open f = 1MHz, all measurements are referenced to device GND 10 TA = 25 - 12 - 12 pF Output Disable Time t OZ 10, 11 -55 ≤ TA ≤ 125 - 35 - 40 ns Output Rise Time tr From 0.8V to 2.0V 10, 11 -55 ≤ TA ≤ 125 - 6 - 6 ns Output Fall Time tf From 2.0V to 0.8V 10, 11 -55 ≤ TA ≤ 125 - 6 - 6 ns NOTES: 10. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 11. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C and D Test Load Circuit S1 DUT (NOTE 12) CL IOH ± 1.5V EQUIVALENT CIRCUIT NOTES: 12. Includes stray and jig capacitance. 13. Switch S1 Open for ICCSB and ICCOP Tests. 5 IOL HSP48908/883 Burn-In Circuit GND DOUT5 DOUT6 DOUT8 DOUT10 DOUT12 DOUT13 DOUT15 11 CASO6 DOUT0 DOUT1 10 CASO4 CASO5 CASO7 DOUT2 DOUT4 DOUT9 GND 9 CASO3 8 CASO1 CASO2 DOUT3 DOUT7 GND DOUT11 DOUT14 GND DOUT17 DOUT16 DOUT18 VCC DOUT19 GND 7 OE GND VCC CASI1 FRAME CASI0 6 DIN1 CASOd DIN0 CASI2 5 DIN2 DIN3 DIN4 CASI6 CASI14 CASI13 4 DIN5 DIN6 3 DIN7 CIN1 2 CIN0 CIN3 CIN4 1 CIN2 CIN5 A B 6 VCC RESET CASI7 CASI16 CASI10 CASI18 CIN9 HOLD LD CIN7 GND VCC A2 EALU CIN6 CIN8 CLK A1 CS A0 C D E F G H CASI13 CASI11 CASI9 CASI15 CASI14 CASI12 J K L HSP48908/883 PGA BURN-IN SCHEMATIC PIN NAME PGA PIN BURN-IN SIGNAL PIN NAME PGA PIN BURN-IN SIGNAL PIN NAME PGA PIN BURN-IN SIGNAL F5 CIN2 A1 F13 POUT1 C11 VCC/2 CASI.13 J2 CIN0 A2 F12 CIN8 D1 F14 CASI.5 J5 F5 DIN7 A3 F7 CIN7 D2 F12 CASI.2 J6 F2 DIN5 A4 F5 POUT2 D10 VCC/2 CASI.1 J7 F1 DIN2 A5 F2 GND D11 GND POUT14 J10 VCC/2 DIN1 A6 F1 CLK E1 F0 POUT12 J11 VCC/2 OE A7 F10 GND E2 GND CASI.14 K1 F6 CASO.1 A8 VCC/2 CIN9 E3 F14 CASI.11 K2 F3 CASO.3 A9 VCC/2 POUT3 E9 VCC/2 CASI.10 K3 F2 CASO.4 A10 VCC/2 POUT4 E10 VCC/2 CASI.7 K4 F7 CASO.6 A11 VCC/2 POUT5 E11 VCC/2 CASI.4 K5 F4 CIN5 B1 F12 A1 F1 F13 VCC K6 VCC CIN3 B2 F13 VCC F2 VCC FRAME K7 F15 CIN1 B3 F12 HOLD F3 F14 POUT19 K8 VCC/2 DIN6 B4 F6 POUT7 F9 VCC/2 POUT16 K9 VCC/2 DIN3 B5 F3 POUT9 F10 VCC/2 GND K10 GND CASO.0 B6 VCC/2 POUT6 F11 VCC/2 POUT13 K11 VCC/2 GND B7 GND CS G1 F12 CASI.12 L1 F4 CASO.2 B8 VCC/2 A2 G2 F14 CASI.9 L2 F1 GND B9 GND LOAD G3 F11 CASI.8 L3 F0 CASO.5 B10 VCC/2 VCC G9 VCC CASI.6 L4 F6 POUT0 B11 VCC/2 GND G10 GND CASI.3 L5 F3 CIN6 C1 F13 POUT8 G11 VCC/2 RESET L6 F16 CIN4 C2 F13 A0 H1 F12 CASI.0 L7 F0 DIN4 C5 F4 EALU H2 F8 GND L8 GND DIN0 C6 F0 POUT11 H10 VCC/2 POUT18 L9 VCC/2 VCC C7 VCC POUT10 H11 VCC/2 POUT17 L10 VCC/2 CASO.7 C10 VCC/2 CASI.15 J1 F7 POUT15 L11 VCC/2 NOTES: 14. VCC/2 (2.7 ±10%) used for outputs only. 15. 47kΩ (±20%) resistor connected to all pins except VCC and GND. 16. VCC = 5.5 ±0.5V. 17. 0.1µF (minimum) capacitor between VCC and GND per position. 18. F0 = 100kHz ±10%, F1 - F0/2, F2 = F1/2...F11 = F10/2, 40 - 60% duty cycle. 19. Input Voltage Limits: VIL = 0.8V maximum, VIH = 4.5V ±10%. Die Characteristics DIE DIMENSIONS: 341 mils x 322 mils x 19 mils ±1 mil WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kÅ GLASSIVATION: Type: Nitrox Thickness: 10kÅ All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7