HS-6617RH Radiation Hardened 2K x 8 CMOS PROM August 1995 Features • • • • • • • • • • • • • • • Pinouts 5 Total Dose 1 x 10 RAD (Si) Latch-Up Free >1 x 1012 RAD (Si)/s Field Programmable Functionally Equivalent to HM-6617 Pin Compatible with Intel 2716 Low Standby Power 1.1mW Max Low Operating Power 137.5mW/MHz Max Fast Access Time 100ns Max TTL Compatible Inputs/Outputs Synchronous Operation On Chip Address Latches Three-State Outputs Nicrome Fuse Links Easy Microprocessor Interfacing Military Temperature Range -55oC to +125oC 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW Description The Intersil HS-6617RH is a radiation hardened 16K CMOS PROM, organized in a 2K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and is designed to be functionally equivalent to the HM-6617. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structure, such as the HS-80C85RH or HS-80C86RH. The output enable control (G) simplifies microprocessor system interfacing by allowing output data bus control, in addition to, the chip enable control. Synchronous operation of the HS-6617RH is ideal for high speed pipe-lined architecture systems and also in synchronous logic replacement functions. Applications for the HS-6617RH CMOS PROM include low power microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement. A7 1 24 VDD A6 2 23 A8 A5 3 22 A9 A4 4 21 P A3 5 20 G A2 6 19 A10 A1 7 18 E A0 8 17 Q7 Q0 9 16 Q6 Q1 10 15 Q5 Q2 11 14 Q4 GND 12 13 Q3 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW A7 1 24 VDD A6 2 23 A8 A5 3 A4 A3 4 5 22 21 20 A2 A1 6 7 19 18 A0 Q0 8 9 17 16 A9 P G A10 E Q7 Q6 Q1 Q2 10 11 15 14 Q5 Q4 GND 12 13 Q3 Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE PIN DESCRIPTION HS1-6617RH-Q -55oC +125oC 24 Lead SBDIP A Address Input HS1-6617RH-8 -55oC to +125oC 24 Lead SBDIP Q Data Output HS1-6617RH/SAMPLE 25oC 24 Lead SBDIP E Chip Enable HS1-6617RH/PROTO -55oC to +125oC 24 Lead SBDIP G Output Enable HS9-6617RH-Q -55oC to +125oC 24 Lead Flatpack P HS9-6617RH-8 -55oC 24 Lead Flatpack Program Enable (P Hardwired to VDD, except during programming) HS9-6617RH/PROTO to +125oC 25oC -55oC to +125oC 24 Lead Flatpack DB NA HS9-6617RH/Sample to 24 Lead Flatpack CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 Spec Number File Number 518742 3033.3 HS-6617RH Functional Diagram MSB A10 A9 A8 A7 A6 A5 A4 7 A LATCHED GATED ADDRESS ROW DECODER REGISTER 7 A 128 x 128 MATRIX 128 1 OF 8 LSB E E 16 16 16 16 16 16 16 GATE COLUMN 8 P 16 Q0 - Q7 8 DECODER PROGRAMMING, & DATA E OUTPUT CONTROL E A G E A 4 4 LATCHED ADDRESS REGISTER MSB LSB A3 A2 A1 A0 ADDRESS LATCHES & GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G P = HARDWIRED TO VDD EXCEPT DURING PROGRAMMING ALL LINES POSITIVE LOGIC: ACTIVE HIGH THREE STATE BUFFERS: OUTPUT ACTIVE A HIGH TRUTH TABLE E G MODE 0 0 Enabled 0 1 Output Disabled 1 X Disabled Spec Number 2 518742 Specifications HS-6617RH Absolute Maximum Ratings Reliability Information Supply Voltage ( All Voltages Reference to Device GND) . . . . +7.0V Input or Output Voltage Applied for All Grades. . . . . . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC Sidebraze DIP Package . . . . . . . . . . . . . 40oC/W 6oC/W Ceramic Flatpack Package . . . . . . . . . . . 60oC/W 4oC/W Maximum Package Power Dissipation at +125oC Sidebraze DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 1.251W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.83W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: Sidebraze DIP Package . . . . . . . . . . . . . . . . . . . . . . . .25.0mW/C Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .16.7mW/C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Supply Voltage Range (VDD) . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . +2.4V to VDD TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL GROUP A SUBGROUPS LIMITS TEMPERATURE ≤ TA ≤ MAX UNITS 2.4 - V High Level Output Voltage VOH1 VDD = 4.5V, IO = -2.0mA 1, 2, 3 Low Level Output Voltage VOL VDD = 4.5V, IO = 4.8mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V High Impedance Output Leakage Current IOZ VDD = 5.5V, G = 5.5V, VI/O = GND or VDD 1, 2, 3 -55oC ≤ TA ≤ +125oC -10.0 10.0 µA VDD = 5.5V, VI = GND or VDD, P Not Tested 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA Input Leakage Current II +125oC MIN -55oC Standby Supply Current IDDSB VDD = 5.5V, IO = 0mA, VI = VDD or GND 1, 2, 3 -55oC ≤ TA ≤ +125oC - 200 µA Operating Supply Current IDDOP VDD = 5.5V, G = GND, (Note 3), f = 1MHz, IO = 0mA, VI = VDD or GND 1, 2, 3 -55oC ≤ TA ≤ +125oC - 25 mA 7, 8A, 8B -55oC ≤ TA ≤ +125oC - - - Functional Test FT VDD = 4.5V (Note 4) NOTES: 1. All voltages referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. Typical derating = 20mA/MHz increase in IDDOP. 4. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. LIMITS PARAMETERS SYMBOL (NOTES 1, 2, 3) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Address Access Time TAVQV VDD = 4.5V and 5.5V (Note 4) 9, 10, 11 -55oC ≤ TA ≤ +125oC - 120 ns Output Enable Access Time TGLQV VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 50 ns Chip Enable Access Time TELQV VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 100 ns Address Setup Time TAVEL VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - ns Spec Number 3 518742 Specifications HS-6617RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Guaranteed and 100% Tested. LIMITS SYMBOL (NOTES 1, 2, 3) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Address Hold Time TELAX VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 25 - ns Chip Enable Low Width TELEH VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - ns Chip Enable High Width TEHEL VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - ns Read Cycle Time TELEL VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 160 - ns PARAMETERS NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1 TTL equivalent load and CL ≥ 50pF. 3. All tests performed with P hardwired to VDD. 4. TAVQV = TELQV + TAVEL. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS, AC AND DC LIMITS PARAMETERS SYMBOL (NOTE 2) CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Input Capacitance CIN VDD = Open, f = 1MHz 1, 3 TA = +25oC - 10 pF I/O Capacitance CI/O VDD = Open, f = 1MHz 1, 3 TA = +25oC - 12 pF Chip Enable Time TELQX VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC 5 - ns Output Enable Time TGLQX VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC 5 - ns Chip Disable Time TEHQZ VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC - 50 ns Output Disable Time TGHQZ VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC - 50 ns Output High Voltage VOH2 VDD = 4.5V, IO = 100µA 3 -55oC ≤ TA ≤ +125oC VDD0.5V - V NOTES: 1. All measurements referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after design or process changes which would affect these characteristics. TABLE 4. POST 100K RAD AC AND DC ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: All AC and DC parameters are tested at the +25oC pre-irradiation limits. Spec Number 4 518742 HS-6617RH TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER SYMBOL DELTA LIMITS IDDSB ±10µA IOZ ± 1µA II ±100nA Output Low Voltage VOL ± 60mV Output High Voltage VOH ± 400mV Standby Supply Current Input Leakage Current TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD TESTED FOR -Q RECORDED FOR -Q TESTED FOR -8 Initial Test 100% 5004 1, 7, 9 1 (Note 2) 1, 7, 9 Interim Test 100% 5004 1, 7, 9, ∆ 1, ∆ (Note 2) 1, 7, 9 PDA 100% 5004 1, 7, ∆ - 1, 7 Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 - 2, 3, 8A, 8B, 10, 11 Group A (Note 1) Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆ 1, 2, 3, ∆ (Note 2) - Subgroup B6 Sample 5005 1, 7, 9 - - Group C Sample 5005 - - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group D Sample 5005 1, 7, 9 - 1, 7, 9 Group E, Subgroup 2 Sample 5005 1, 7, 9 - 1, 7, 9 RECORDED FOR -8 NOTES: 1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only Spec Number 5 518742 HS-6617RH Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% PDA 1, Method 5004 (Note 2) 100% Delta Calculation (T0-T1) 100% Die Attach (Note 1) 100% Dynamic Burn-In, Condition D, 240 Hours, +125oC or Equivalent, Method 1015 100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2(T2) Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 2, Method 5004 (Note 2) 100% Internal Visual Inspection, Method 2010, Condition A 100% Final Electrical Test CSI and/or GSI Pre-Cap (Note 8) 100% Fine/Gross Leak, Method 1014 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Radiographic (X-Ray), Method 2012 (Note 3) 100% Constant Acceleration, Method 2001, Condition per Method 5004 Sample - Group A, Method 5005 (Note 4) 100% External Visual, Method 2009 Sample - Group B, Method 5005 (Notes 5 and 6) 100% PIND, Method 2020, Condition A Sample - Group D, Method 5005 (Notes 6 and 7) 100% External Visual 100% Data Package Generation (Note 9) 100% Serialization CSI and/or GSI Final (Note 8) 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 72 Hours Min, +125oC Min, Method 1015 NOTES: 1. Epoxy or Silver glass die attach shall be permitted. 2. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. QCI Subgroup B5 samples are programmed with a checkerboard pattern before life test and pattern tested after life test. Therefore, the Subgroup B5 samples must be considered destruct samples and cannot be shipped as flight quantity. 6. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group Samples, Group D Test and Group D Samples. 7. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 8. CSI and/or GSI inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for CSI PreCap inspection, CSI Final Inspection, GSI PreCap inspection, and/or GSI Final Inspection. 9. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • Group B and D attributes and/or Generic data is included when required by the P.O. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 6 518742 HS-6617RH Intersil Space Level Product Flow -8 GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or Equivalent, Method 1015 100% Die Attach (Note 1) 100% Interim Electrical Test Periodic- Wire Bond Pull Monitor, Method 2011 100% PDA, Method 5004 (Note 2) Periodic- Die Shear Monitor, Method 2019 or 2027 100% Final Electrical Test 100% Internal Visual Inspection, Method 2010, Condition B 100% Fine/Gross Leak, Method 1014 CSI and/or GSI Pre-Cap (Note 7) 100% External Visual, Method 2009 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles Sample - Group A, Method 5005 (Note 3) 100% Constant Acceleration, Method 2001, Condition per Method 5004 Sample - Group C, Method 5005 (Notes 4, 5 and 6) Sample - Group B, Method 5005 (Note 5) Sample - Group D, Method 5005 (Notes 5 and 6) 100% External Visual 100% Data Package Generation (Note 8) 100% Initial Electrical Test CSI and/or GSI Final (Note 7) NOTES: 1. Epoxy or Silver glass die attach shall be permitted. 2. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5%. 3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 4. QCI Group C samples are programmed with a checkerboard pattern before life test and pattern tested after life test. Therefore, the Group C samples must be considered destruct samples and cannot be shipped as flight quantity. 5. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples. 6. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 7. CSI and/or GSI inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for CSI PreCap inspection, CSI Final Inspection, GSI PreCap inspection, and/or GSI Final Inspection. 8. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Group B, C and D attributes and/or Generic data is included when required by the P.O. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 7 518742 HS-6617RH Timing Waveform TAVQV 3.0V 1.5V 1.5V VALID ADDRESS VALID ADDRESSES 0V ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V 1.5V 1.5V 1.5V E 0V TEHEL TELQV G TEHQZ TGLQV 3.0V 1.5V 1.5V 0V TGLQX DATA OUTPUT Q0 - Q7 TGHQZ TELQX VALID DATA TS FIGURE 1. READ CYCLE Spec Number 8 518742 HS-6617RH Burn-In Circuits HS-6617RH 24 LEAD SBDIP AND FLATPACK HS-6617RH 24 LEAD SBDIP AND FLATPACK C1 VDD A7 VDD A6 VDD A5 VDD A4 VDD VDD VDD VDD A3 A2 A1 A0 Q0 Q1 Y Q2 GND 1 24 2 23 VDD A8 A9 22 3 P 21 4 G 20 5 19 6 18 7 16 9 15 10 14 11 13 12 VDD F10 A7 VDD F9 A6 VDD F8 A5 F7 A4 VDD VDD A10 VDD E VDD A3 F6 A2 F5 A1 F4 Q7 17 8 C1 A0 F3 Q6 Q0 Q5 Q1 Y Y Q4 Q2 Q3 GND STATIC CONFIGURATION 24 2 23 22 3 21 4 20 5 19 6 18 7 8 17 9 16 10 15 11 14 12 13 VDD A8 A9 P VDD F11 F12 VDD G F1 A10 F13 E F0 Q7 Q6 Q5 Y Q4 Q3 DYNAMIC CONFIGURATION NOTES: 1. 2. 3. 4. 1 NOTES: VDD = 6.0V ± 0.5V C1 = 0.01µF (Min) All Resistors = 47kΩ ± 5% Y = 2.7V ± 10% 1. 2. 3. 4. 5. 6. 7. 8. VDD = 6.0V ± 0.5V VIH = 4.5V± 10% VIL = 0.8V (Max) C1 = 0.01µF (Min) All Resistors = 47kΩ ± 5% F0 = 100KHz ± 10%, 40 - 60% duty cycle F1 = F0/2 . . . F13 = F12/2 Y = 2.7V ± 10% Irradiation Circuit HS-6617RH 24 LEAD FLATPACK VDD 1 24 2 23 3 22 4 21 NC 5 20 NC 6 19 NC 7 18 8 17 LOAD LOAD 9 16 LOAD LOAD 10 15 LOAD LOAD 11 14 LOAD 12 13 LOAD TOGGLE (NOTE 3) VDD 47KΩ LOAD = 47KΩ VSS NOTES: 1. Power Supply: VDD = 5.5V 2. All Registors = 47KΩ 3. Pin 18 is toggled from VSS to VDD then back to VSS and held at VSS during irradiation. Spec Number 9 518742 HS-6617RH Metallization Topology DIE DIMENSIONS: 164 x 250 x 19 ±1mils METALLIZATION: Type: Silicon-Aluminum Thickness: 13kÅ ± 2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ WORST CASE CURRENT DENSITY: 1 x 105 A/cm2 SUBSTRATE POTENTIAL: VDD Metallization Mask Layout (21) P (22) A9 (23) A8 (24)VDD (1) A7 (2) A6 (3)A5 (4) A4 (5) A3 HS-6617RH (20) G A2 (6) (19) A10 A1 (7) (18) E Q7 (17) Q6 (16) Q5 (15) Q4 (14) Q3 (13) GND (12) Q2 (11) Q1 (10) Q0 (9) A0 (8) Spec Number 10 518742 HS-6617RH Semiconductor DESIGN INFORMATION 2K x 8 CMOS PROM July 1995 The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Background Information HS-6617RH Programming PROGRAMMING SPECIFICATIONS PARAMETER SYMBOL MIN TYP MAX UNITS Input "0" VIL 0.0 0.2 0.8 V Voltage "1" VIH VDD-2 VDD VDD+0.3 V 6 VDDPROG 10.0 10.0 10.0 V 2 Operating VDD VDD1 4.5 5.5 5.5 V Special Verify VDD2 4.0 - 6.0 V Delay Time td 1.0 1.0 - µs Rise Time tr 1.0 10.0 10.0 µs Fall Time tf 1.0 10.0 10.0 µs Chip Enable Pulse Width TEHEL 50 - - ns Address Valid to Chip Enable Low Time TAVEL 20 - - ns Chip Enable Low to Output Valid Time TELQV - - 120 ns Programming Pulse Width tpw 90 100 110 µs Input Leakage at VDD = VDDPROG tIP -10 +1.0 10 µA Data Output Current at VDD = VDDPROG IOP - -5.0 -10 mA Output Pull-Up Resistor Rn 5 10 15 kΩ Ambient Temperature TA - 25 - oC Programming VDD NOTES 3 4 5 NOTES: 1. All inputs must track VDD (pin 24) within these limits. 2. VDDPROG must be capable of supplying 500mA. VDDPROG Power Supply tolerence ±3% (Max.) 3. See Steps 22 through 29 of the Programming Algorithm. 4. See Step 11 of the Programming Algorithm. 5. All outputs should be pulled up to VDD through a resistor of value Rn. 6. Except during programming (See Programming Cycle Waveforms). Spec Number 11 518742 HS-6617RH DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Background Information Programming The HS-6617 CMOS PROM is manufactured with all bits containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. To accomplish this, a programmer can be built that meets the specifications shown, or use of an approved commercial programmer is recommended. 13. Apply a voltage of VIH to P (pin 21). Programming Sequence of Events Post-Programming Verification 14. After a delay of td, apply a voltage of VIL to G (pin 20). 15. After a delay of td, examine the outputs for correct data. If any location verifies incorrectly, it should be considered a programming reject. 16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM. 1. Apply a voltage of VDD1 to VDD of the PROM. 17. Place the PROM in the post-programming verification mode: E = VIH, G = VIL, P = VIH, VDD (pin 24) = VDD1. 2. Read all fuse locations to verify that the PROM is blank (output low). 3. Place the PROM in the initial state for programming: P = VIH, G = VIL. 18. Apply the correct binary address of the word to be verified to the PROM. E = VIH, 19. After a delay of td, apply a voltage of VIL to E (pin 18). 4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit. 20. After a delay of td, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 5. After a delay of td, apply voltage of VIL to E (pin 18) to access the addressed word. 21. Repeat steps 17 through 20 for all possible programming locations. 6. The address may be held through the cycle, but must be held valid at least for a time equal to td after the falling edge of E. None of the inputs should be allowed to float to an invalid logic level. Post-Programming Read 22. Apply a voltage of VDD2 = 4.0V to VDD (pin 24). 7. After a delay of td, disable the outputs by applying a voltage of VIH to G (pin 20). 23. After a delay of td, apply a voltage of VIH to E (pin 18). 8. After a delay of td, apply voltage of VIL to P (pin 21). 25. After a delay of TAVEL, apply a voltage of VIL to E (pin 18). 9. After delay of td, raise VDD (pin 24) to VDDPROG with a rise time of tr. All outputs at VIH should track VDD within VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resistors of value Rn. 26. After a delay of TELQV, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 24. Apply the correct binary address of the word to be read. 27. Repeat steps 23 through 26 for all address locations. 10. After a delay of td, pull the output which corresponds to the bit to be programmed to VIL. Only one bit should be programmed at a time. 28. Apply a voltage of VDD2 = 6.0V to VDD (pin 24). 29. Repeat steps 23 through 26 for all address locations. 11. After a delay of tpw, allow the output to be pulled to VIH through pull-up resistor Rn. 12. After a delay of td, reduce VDD (pin 24) to VDD1 with a fall time of tf. All outputs at VIH should track VDD with VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resis- tors of value Rn. Spec Number 12 518742 HS-6617RH DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. PROGRAMMING VERIFY VDDPROG VIH A VIL VALID VALID td TEHEL VIH E VIL td VDDPROG VIH G VIL td td VIH VIL P td VDDPROG VDD VDD GND tr td tpw td tf VDDPROG VIH/VOH Q READ DATA VIL/VOL FIGURE 2. HS-6617RH PROGRAMMING CYCLE A VIH VALID VIL TAVEL E TEHEL TEHEL VIH VIL TEHEL td td 6.0V 5.0V 4.0V VDD 0.0V TELQV Q VOH VOL TELQV TELQV READ READ READ FIGURE 3. HS-6617RH POST PROGRAMMING VERIFY CYCLE Spec Number 13 518742 HS-6617RH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. 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Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 14