HS-6617RH-T Data Sheet July 1999 File Number Radiation Hardened 2K x 8 CMOS PROM Features Intersil’s Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. • QML Class T, Per MIL-PRF-38535 The Intersil HS-6617RH-T is a radiation hardened 16k CMOS PROM, organized in a 2K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and is designed to be functionally equivalent to the HM-6617. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. • Field Programmable Nicrome Fuse Links 4608.1 • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - SEU LET 16MeV/mg/cm2 - SEL LET 100MeV/mg/cm2 • Low Standby Power 1.1mW Max • Low Operating Power 137.5mW/MHz Max • Fast Access Time 100ns Max • TTL Compatible Inputs/Outputs • Synchronous Operation On chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structure, such as the HS-80C86RH. The output enable control (G) simplifies microprocessor system interfacing by allowing output data bus control, in addition to, the chip enable control. Synchronous operation of the HS-6617RH-T is ideal for high speed pipe-lined architecture systems and also in synchronous logic replacement functions. • On Chip Address Latches, Three-State Outputs Pinouts HS1-6617RH-T (SBDIP), CDIP2-T24 TOP VIEW Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HS-6617RH-T are contained in SMD 5962-95708. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil’s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp Ordering Information A7 1 24 VDD A6 2 23 A8 A5 3 22 A9 A4 4 21 P A3 5 20 G A2 6 19 A10 A1 7 18 E A0 8 17 Q7 Q0 9 16 Q6 Q1 10 15 Q5 Q2 11 14 Q4 GND 12 13 Q3 HS9-6617RH-T (FLATPACK), CDFP4-F24 TOP VIEW A7 1 24 VDD A6 2 23 A8 A5 3 A4 A3 4 5 22 21 20 5962R9570801TJC HS1-6617RH-T -55 to 125 A2 A1 6 7 19 18 HS1-6617RH/Proto HS1-6617RH/Proto -55 to 125 A0 Q0 8 9 17 16 A9 P† G A10 E Q7 Q6 5962R9570801TXC HS9-6617RH-T -55 to 125 HS9-6617RH/Proto HS9-6617RH/Proto -55 to 125 Q1 Q2 10 11 15 14 Q5 Q4 GND 12 13 Q3 ORDERING NUMBER PART NUMBER TEMP. RANGE (oC) NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. † P must be hardwired at all times to VDD, except during programming. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation. HS-6617RH-T Functional Diagram MSB A10 A9 A8 A7 A6 A5 A4 7 A LATCHED GATED ADDRESS ROW DECODER REGISTER 7 A 128 x 128 MATRIX 128 1 OF 8 LSB E E 16 16 16 16 16 16 16 GATE COLUMN 8 P 16 Q0 - Q7 8 DECODER PROGRAMMING, AND DATA E OUTPUT CONTROL E A G E A 4 4 LATCHED ADDRESS REGISTER MSB LSB A3 A2 A1 A0 ADDRESS LATCHES & GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G P = HARDWIRED TO VDD EXCEPT DURING PROGRAMMING ALL LINES POSITIVE LOGIC: ACTIVE HIGH THREE STATE BUFFERS: OUTPUT ACTIVE A HIGH TRUTH TABLE E G MODE 0 0 Enabled 0 1 Output Disabled 1 X Disabled Timing Waveform TAVQV 3.0V 1.5V 1.5V VALID ADDRESS VALID ADDRESSES 0V ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V 1.5V 1.5V 1.5V E 0V TEHEL TELQV G TEHQZ TGLQV 3.0V 1.5V 1.5V 0V TGLQX TGHQZ TELQX DATA OUTPUT Q0 - Q7 VALID DATA FIGURE 1. READ CYCLE 2 TS HS-6617RH-T Die Characteristics DIE DIMENSIONS: BACKSIDE FINISH: (4166µm x 6350µm x 483µm ±25.4µm) Silicon 164 x 250 x 19mils ±1mil PASSIVATION: METALLIZATION: Type: Silox (SiO2) Thickness: 8.0kÅ ±1kÅ Type: Silicon - Aluminum Thickness: 13.0kÅ ±2kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 SUBSTRATE POTENTIAL: VDD PROCESS: SSAJIIV-RH Metallization Mask Layout (21) P (22) A9 (23) A8 (24)VDD (2) A6 (1) A7 (4) A4 (3)A5 (5) A3 HS-6617RH-T (20) G Q7 (17) Q6 (16) Q5 (15) Q3 (13) Q4 (14) (18) E GND (12) A1 (7) A0 (8) Q1 (10) Q2 (11) (19) A10 Q0 (9) A2 (6) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3