HS-6664RH Radiation Hardened 8K x 8 CMOS PROM September 1995 Features Pinouts • 1.2 Micron Radiation Hardened Bulk CMOS 28 LEAD CERAMIC SBDIP CASE OUTLINE D28.6 MIL-STD-1835, CDIP2-T28 TOP VIEW 5 • Total Dose 3 x 10 RAD (Si) • Transient Output Upset >5 x 108 RAD (Si)/s NC 1 28 VDD A12 2 27 P † A7 3 26 NC A6 4 25 A8 A5 5 24 A9 • Single Pulse 10V Field Programmable A4 6 23 A11 • Synchronous Operation A3 7 22 G A2 8 21 A10 A1 9 20 E • LET >100 MEV-cm2/mg • Fast Access Time - 35ns (Typical) • Single 5V Power Supply • On-Chip Address Latches • Three-State Outputs • NiCr Fuses • Low Standby Current <500µA (Pre-Rad) • Low Operating Current <15mA/MHz oC • Military Temperature Range -55 to A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 +125oC Description The Intersil HS-6664RH is a radiation hardened 64K CMOS PROM, organized in an 8K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and utilizes synchronous circuit design techniques to achieve high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with microprocessors that use a multiplexed address/data bus structure. The output enable control (G) simplifies system interfacing by allowing output data bus control in addition to the chip enable control (E). All bits are manufactured storing a logical “0” and can be selectively programmed for a logical “1” at any bit location. Applications for the HS-6664RH CMOS PROM include low power microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, and processor control storage. 28 LEAD FLATPACK CASE OUTLINE K28.A MIL-STD-1835, CDFP3-F28 TOP VIEW VDD NC 1 28 A12 2 27 P† A7 3 26 NC A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 G A2 8 21 A10 A1 9 20 A0 10 19 E DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 † P must be hardwired at all times to VDD, except during programming. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 840 Spec Number File Number 518741 3197.3 HS-6664RH Functional Diagram MSB A2 A3 A4 A5 A6 A7 A8 LSB A LATCHED ADDRESS REGISTER 8 A 256 256 X 256 MATRIX GATED ROW DECODER 1 OF 8 8 E E 32 32 32 32 32 32 32 32 †P GATED COLUMN DECODER PROGRAMMING, AND DATA OUTPUT CONTROL 8 Q0 - Q7 8 E E A A 5 5 G E LATCHED ADDRESS REGISTER MSB LSB A0 A1 A10 A9 A11 A12 † P must be hardwired at all times to VDD, except during programming. TRUTH TABLE E G MODE 0 0 Enabled 0 1 Output Disabled 1 X Disabled Spec Number 841 518741 Specifications HS-6664RH Absolute Maximum Ratings Reliability Information Supply Voltage (All Voltages Reference to Device GND). . . . . +7.0V Input or Output Voltage Applied for All Grades. . . . . . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC Braze Seal DIP Package . . . . . . . . . . . . . 40.0oC/W 4.0oC/W Braze Seal Flatpack Package . . . . . . . . . 53.4oC/W 6.0oC/W Maximum Package Power Dissipation at +125oC Braze Seal DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.75W Braze Seal Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 936mW Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26,817 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Supply Voltage Range (VDD) . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . +2.4V to VDD TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS High Level Output Voltage VOH1 VDD = 4.5V, IO = -2.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC 3.5 - V Output High Voltage VOH2 VDD = 4.5V, IO = 100µA 3 -55oC ≤ TA ≤ +125oC VDD -0.3V - V Low Level Output Voltage VOL VDD = 4.5V, IO = 4.8mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V High Impedance Output Leakage Current IOZ VDD = 5.5V, G = 5.5V, VI/O = GND or VDD 1, 2, 3 -55oC ≤ TA ≤ +125oC -10.0 10.0 µA VDD = 5.5V, VI = GND or VDD, P Not Tested 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA Input Leakage Current II Standby Supply Current IDDSB VDD = 5.5V, IO = 0mA, VI = VDD or GND 1, 2, 3 -55oC ≤ TA ≤ +125oC - 500 µA Operating Supply Current IDDOP VDD = 5.5V, G = VDD, (Note 3), f = 1MHz, IO = 0mA, VI = VDD or GND 1, 2, 3 -55oC ≤ TA ≤ +125oC - 15 mA 7, 8A, 8B -55oC ≤ TA ≤ +125oC - - - Functional Test FT VDD = 4.5V (Note 4) NOTES: 1. All voltages referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. Typical derating = 15mA/MHz increase in IDDOP. 4. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.45V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. LIMITS SYMBOL (NOTES 1, 2, 3) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Output Enable Access Time TGLQV VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 20 ns Chip Enable Access Time TELQV VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 60 ns Address Setup Time TAVEL VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 5 - ns Address Hold Time TELAX VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 12 - ns PARAMETER Spec Number 842 518741 Specifications HS-6664RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Guaranteed and 100% Tested. LIMITS SYMBOL (NOTES 1, 2, 3) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Chip Enable Low Width TELEH VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 60 - ns Chip Enable High Width TEHEL VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - ns Read Cycle Time TELEL VDD = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 80 - ns PARAMETER NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1 TTL equivalent load and CL ≥ 50pF. 3. All tests performed with P hardwired to VDD. 4. Address Access Time (TAVQV) = TELQV + TAVEL = 65ns (maximum). TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS, AC AND DC PARAMETER LIMITS (NOTE 2) CONDITIONS SYMBOL NOTES TEMPERATURE MIN MAX UNITS Input Capacitance CIN VDD = Open, f = 1MHz 1, 3 TA = +25oC - 15 pF I/O Capacitance CI/O VDD = Open, f = 1MHz 1, 3 TA = +25oC - 12 pF Chip Enable Time TELQX VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC 5 - ns Output Enable Time TGLQX VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC 5 - ns Chip Disable Time TEHQZ VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC - 15 ns Output Disable Time TGHQZ VDD = 4.5V and 5.5V 3 -55oC ≤ TA ≤ +125oC - 15 ns NOTES: 1. All measurements referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after design or process changes which would affect these characteristics. TABLE 4. POST 100K RAD AC AND DC ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: All AC and DC parameters are tested at the +25oC pre-irradiation limits. TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER SYMBOL DELTA LIMITS IDDSB ±50µA IOZ ±1µA II ±100nA Output Low Voltage VOL ±60mV Output High Voltage VOH ±400mV Standby Supply Current Input Leakage Current Spec Number 843 518741 Specifications HS-6664RH TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD -Q SUBGROUPS -8 SUBGROUPS Initial Test 100%/5004 1, 7, 9 1, 7, 9 Interim Test 100%/5004 1, 7, 9 1, 7, 9 PDA 1 and 2 100%/5004 1, 7, ∆ 1, 7 Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 2, 3, 8A, 8B, 10, 11 Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 B5 Samples/5005 1, 2, 3, 7, 8A, 8B N/A Others Samples/5005 1, 7,9 N/A Group C (Optional) Samples/5005 N/A 1, 7, 9 Group D (Optional) Samples/5005 1, 7, 9 1, 7, 9 Group E, Subgroup 2 (Note 1) Samples/5005 1, 7, 9 1, 7, 9 Group A Group B (*Optional) NOTE: 1. Intersil may exercise its option to perform to a small lot sampling plan of 5 units per lot. Timing Waveform READ CYCLE TAVQV 3.0V 1.5V 1.5V VALID ADDRESS VALID ADDRESSES 0V ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V 1.5V 1.5V 1.5V E 0V TEHEL TELQV G TEHQZ TGLQV 3.0V 1.5V 1.5V 0V TGLQX DATA OUTPUT Q0 - Q7 TGHQZ TELQX VALID DATA TS Spec Number 844 518741 HS-6664RH Burn-In Circuits HS1-6664RH 28 LEAD (8K x 8 PROM DIP) HS9-6664RH 28 LEAD (8K x 8 PROM FLATPACK) HS1-6664RH 28 LEAD (8K x 8 PROM DIP) HS9-6664RH 28 LEAD (8K x 8 PROM FLATPACK) VDD NC NC A12 A7 A6 A5 A4 A3 A2 A1 A0 NC NC NC DQ0 DQ1 DQ2 VSS 1 28 27 2 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VDD VDD A12 F13 NC NC NC P A7 F8 NC A8 A6 F7 A9 A5 F6 A11 A4 F5 G A3 F4 A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 A0 F1 NC NC LOAD NC LOAD NC LOAD DQ0 DQ1 DQ2 VSS NC 2 27 3 26 4 25 5 24 6 23 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 A1 F2 28 7 A2 F3 1 OUT STATIC CONFIGURATION NOTES: 1. Power Supply: VDD = 5.5V (Min) 2. Resistors = 10kΩ ± 10% P NC NC A8 F9 A9 F10 A11 F12 G F0 A10 F11 E1 F0 DQ7 DQ6 DQ5 DQ4 DQ3 LOAD LOAD LOAD LOAD LOAD LOAD: 10KΩ VSS = GND VSS = GND VDD VDD/2 DYNAMIC CONFIGURATION NOTES: 1. Power Supply: VDD = 5.5V (Min) 2. VIH = VDD to VDD-1.0V 3. VIL = 0.0V to 0.8V 4. Resistors = 10KΩ ± 10% 5. F0 = 100KHz ± 10%, 50% Duty Cycle 6. F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2; F5 = F4/2; . . . F13 = F12/2 Irradiation Circuit HS1-6664RH 28 LEAD (8K x 8 PROM DIP) VDD NC NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VDD P NC NC A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VDD = GND NOTES: 1. Power Supply: VDD = 5.5V 2. All Resistors = 47KΩ ± 10% ±0.5V Spec Number 845 518741 HS-6664RH Intersil - Space Level (-Q) Product Flow (Note 1) SEM - Traceable to Diffusion Method 2018 Wafer Lot Acceptance Method 5007 Internal Visual Inspection Method 2010, Condition A Gamma Radiation Assurance Tests Method 1019 Nondestructive Bond Pull Method 2023 Customer Pre-Cap Visual Inspection (Note 2) Temperature Cycling Method 1010, Condition C Constant Acceleration Method 2001, Condition E Min, Y1 Particle Impact Noise Detection Method 2020, Condition A Electrical Tests (Intersil’ Option) Serialization X-Ray Inspection Method 2012 Electrical Tests - Subgroup 1; Read and Record (T0) Static Burn-In Method 1015, Condition B, 72 Hrs, +125oC Min. Interim 1 Electrical Tests - Subgroup 1; Read and Record (T1) Burn-In Delta Calculation (T0 -T1) PDA Calculation 3% Subgroup 7 5% Subgroups 1, 7, ∆ Dynamic Burn-In Method 1015, Condition D, 240 Hrs, +125oC (Note 3) Interim 2 Electrical Tests - Subgroup 1; Read and Record (T2) Alternate Group A - Subgroups 1, 7, 9; Method 5005; Para 3.5.1.1 Burn-In Delta Calculation (T0 - T2) PDA Calculation 3% Subgroup 7 5% Subgroups 1, 7, ∆ Electrical Tests - Subgroup 3; Read and Record Alternate Group A - Subgroups 3, 8B, 11; Method 5005; Para 3.5.1.1 Marking Electrical Tests - Subgroup 2; Read and Record Alternate Group A - Subgroups 2, 8A, 10; Method 5005; Para 3.5.1.1 Gross Leak Tests Method 1014, 100% Fine Leak Tests Method 1014, 100% Customer Source Inspection (Note 2) Group B Inspection Method 5005 (Note 2) End-Point Electrical Parameters: B-5 - Subgroups 1, 2, 3, 7, 8A, 8B, 9, 10, 11; B-6 - Subgroups 1, 7, 9 Group D Inspection Method 5005 (Notes 2, 4) End-Point Electrical Parameters: Subgroups 1, 7, 9 External Visual Inspection Method 2009 Data Package Generation (Note 4) NOTES: 1. The notes of Method 5004, Table 1 shall apply; Unless Otherwise Specified. 2. These steps are optional, and should be listed on the individual purchase order(s), when required. 3. Intersil reserves the right of performing burn-in time temperature regression as defined by Table 1 of Method 1015. 4. Data package contains: Assembly Attributes (post seal) Test Attributes (includes Group A) Shippable Serial Number List Radiation Testing Certificate of Conformance Wafer Lot Acceptance Report (Including SEM Report) X-Ray Report and Film Test Variables Data Intersil -8 Product Flow Internal Visual Inspection Method 2010 Condition B Alternate Gamma Radiation Assurance Tests Method 1019 Customer Pre-Cap Visual Inspection (Note 1) Temperature Cycling Method 1010, Condition C Fine and Gross Leak Tests Method 1014 Constant Acceleration Method 2001 Y1 30KG Initial Electrical Tests Dynamic Burn-In Method 1015, Condition D, 160 Hrs, +125oC +25oC Electrical Tests - Subgroups 1, 7, 9 PDA Calculation 5% Subgroups 1, 7 Electrical Tests +125oC, -55oC Group A Inspection Method 5005. 5% PDA (Note 3) Brand Customer Source Inspection (Note 1) Group B Inspection Method 5005 (Notes 1, 2) Group C Inspection Method 5005 (Notes 1, 2) Group D Inspection Method 5005 (Notes 1, 2) External Visual Inspection Method 2009 Data Package Generation (Note 4) NOTES: 1. These steps are optional, and must be negotiated as part of order. 2. Group B, C and D data package contains Attributes Data. 3. Intersil reserves the right to perform Alternate Group A. The 5% PDA is still applicable. 4. ‘-8’ Data package contains: Assembly Attributes (post seal) Test Attributes (includes Group A) Radiation Testing Certificate of Conformance Certificate of Conformance (as found on shipper) Spec Number 846 518741 HS-6664RH Metallization Topology DIE DIMENSIONS: 271 x 307 x 19 ±1mils WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 METALLIZATION: M1: 6kÅ ±1kÅ Si/Al/Cu 2kÅ ±500Å TiW M2: 10kÅ ± 2kÅSi/Al/Cu SUBSTRATE POTENTIAL: VDD TRANSISTOR COUNT: 110, 874 GATE COUNT: 27, 719 (Based on 2-Input NAND) GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ Metallization Mask Layout VDD VSS (22) G A10 (21) (23) A11 E (20) (24) A9 DQ7 (19) (26) NC (25) A8 DQ6 (18) DQ5 (17) (27) P (28) VDD DQ4 (16) DQ3 (15) GND (14) (3) A7 (2) A12 DQ2 (13) DQ1 (12) (4) A6 (5) A5 DQ0 (11) (6) A4 A0 (10) A1 (9) A2 (8) VDD VSS (7) A3 HS-6664RH Spec Number 847 518741 HS-6664RH Packaging -A- D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C) LEAD FINISH c1 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE -DBASE METAL E b1 M (b) M -Bbbb S C A - B S INCHES (c) SECTION A-A D S D BASE PLANE S2 Q -C- SEATING PLANE A L S1 eA A A b2 b e ccc M C A - B S D S eA/2 c aaa M C A - B S D S SYMBOL MIN MAX MIN MAX NOTES A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 E 0.500 0.610 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 12.70 37.85 - 15.49 - e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 NOTES: MILLIMETERS 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. M - 0.0015 - 0.038 2 N 28 28 8 Rev. 0 5/18/94 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. Spec Number 848 518741 HS-6664RH Packaging (Continued) K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B) 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A e A INCHES PIN NO. 1 ID AREA -A- D -B- S1 b MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - E1 0.004 M H A-B S D S 0.036 M H A-B S D S C Q E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 (c) b1 M M - 0.740 E 0.460 0.520 E1 - 0.550 - E2 0.180 - 4.57 - - E3 0.030 - 0.76 - 7 e LEAD FINISH BASE METAL D SECTION A-A 0.050 BSC 18.80 3 13.21 - 13.97 3 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.00 - 0.00 - 6 M - 0.0015 - 0.04 - N (b) 11.68 28 28 Rev. 0 5/18/94 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Spec Number 849 518741 HS-6664RH Semiconductor DESIGN INFORMATION 8K x 8 CMOS PROM September 1995 The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Background Information HS-6664RH Programming PROGRAMMING SPECIFICATIONS PARAMETER SYMBOL MIN TYP MAX UNITS Input “0” VIL 0.0 0.2 0.8 V Voltage “1” VIH VDD-2 VDD VDD+0.3 V 6 VDDPROG 9.0 9.0 9.0 V 2 Operating VDD VDD1 4.5 5.5 5.5 V Special Verify VDD2 4.0 - 6.0 V Delay Time td 1.0 1.0 - µs Rise Time tr 1.0 10.0 10.0 µs Fall Time tf 1.0 10.0 10.0 µs Chip Enable Pulse Width TEHEL 20 - - ns Address Valid to Chip Enable Low Time TAVEL 0 - - ns Chip Enable Low to Output Valid Time TELQV - - 60 ns Programming Pulse Width tpw 90 100 110 µs Input Leakage at VDD = VDDPROG tIP -10 +1.0 10 µA Data Output Current at VDD = VDDPROG IOP - -5.0 -10 mA Output Pull-Up Resistor Rn 5 10 15 kΩ Ambient Temperature TA - 25 - oC Programming VDD NOTES 3 4 5 NOTES: 1. All inputs must track VDD (pin 28) within these limits. 2. VDDPROG must be capable of supplying 500mA. VDDPROG Power Supply tolerance ±3% (Max.) 3. See Steps 22 through 29 of the Programming Algorithm. 4. See Step 11 of the Programming Algorithm. 5. All outputs should be pulled up to VDD through a resistor of value Rn. 6. Except during programming (See Programming Cycle Waveforms). Spec Number 850 518741 HS-6664RH DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Background Information Programming The HS-6664 CMOS PROM is manufactured with all bits containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. To accomplish this, a programmer can be built that meets the specifications shown, or use of an approved commercial programmer is recommended. 15. After a delay of td, examine the outputs for correct data. If any location verifies incorrectly, it should be considered a programming reject. 16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM. Post-Programming Verification 1. Apply a voltage of VDD1 to VDD of the PROM. 17. Place the PROM in the post-programming verification mode: E = VIH, G = VIL, P = VIH, VDD (pin 28) = VDD1. 2. Read all fuse locations to verify that the PROM is blank (output low). 18. Apply the correct binary address of the word to be verified to the PROM. 3. Place the PROM in the initial state for programming: E = VIH, P = VIH, G = VIL. 19. After a delay of td, apply a voltage of VIL to E (pin 20). Programming Sequence of Events 4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit. 20. After a delay of td, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 5. After a delay of td, apply voltage of VIL to E (pin 20) to access the addressed word. 21. Repeat steps 17 through 20 for all possible programming locations. 6. The address may be held through the cycle, but must be held valid at least for a time equal to td after the falling edge of E. None of the inputs should be allowed to float to an invalid logic level. Post-Programming Read 7. After a delay of td, disable the outputs by applying a voltage of VIH to G (pin 22). 24. Apply the correct binary address of the word to be read. 8. After a delay of td, apply voltage of VIL to P (pin 27). 9. After delay of td, raise VDD (pin 28) to VDDPROG with a rise time of tr. All outputs at VIH should track VDD within VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resistors of value Rn. 10. After a delay of td, pull the output which corresponds to the bit to be programmed to VIL. Only one bit should be programmed at a time. 22. Apply a voltage of VDD2 = 4.0V to VDD (pin 28). 23. After a delay of td, apply a voltage of VIH to E (pin 20). 25. After a delay of TAVEL, apply a voltage of VIL to E (pin 20). 26. After a delay of TELQV, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 27. Repeat steps 23 through 26 for all address locations. 28. Apply a voltage of VDD2 = 6.0V to VDD (pin 28). 29. Repeat steps 23 through 26 for all address locations. 11. After a delay of tpw, allow the output to be pulled to VIH through pull-up resistor Rn. 12. After a delay of td, reduce VDD (pin 28) to VDD1 with a fall time of tf. All outputs at VIH should track VDD with VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resistors of value Rn. 13. Apply a voltage of VIH to P (pin 27). 14. After a delay of td, apply a voltage of VIL to G (pin 22). Spec Number 851 518741 HS-6664RH DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. HS-6664RH PROGRAMMING CYCLE PROGRAMMING VERIFY VDDPROG VIH A VALID VALID VIL TEHEL td VIH E VIL td td VDDPROG VIH G VIL td VIH VIL P td VDDPROG VDD VDD GND tr td tpw td tf VDDPROG VIH/VOH Q READ DATA VIL/VOL HS-6664RH POST PROGRAMMING VERIFY CYCLE A VIH VALID VIL TAVEL E TEHEL TEHEL VIH VIL TEHEL td td 6.0V 5.0V 4.0V VDD 0.0V TELQV Q VOH VOL TELQV TELQV READ READ READ Spec Number 852 518741 HS-6664RH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 853