74LVC126A D

74LVC126A
Low-Voltage CMOS
Quad Buffer
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The 74LVC126A is a high performance, non−inverting quad buffer
operating from a 1.2 to 3.6 V supply. High impedance TTL compatible
inputs significantly reduce current loading to input drivers while TTL
compatible outputs offer improved switching noise performance. A VI
specification of 5.5 V allows 74LVC126A inputs to be safely driven
from 5.0 V devices. The 74LVC126A is suitable for memory address
driving and all TTL level bus oriented transceiver applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OEn) inputs, when HIGH, disable the outputs by placing them in a
HIGH Z condition.
MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
14
1
LVC126AG
AWLYWW
1
Features
•
•
•
•
•
•
•
•
Designed for 1.2 to 3.6 V VCC Operation
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
24 mA Output Sink and Source Capability
Near Zero Static Supply Current in all Three Logic States (10 mA)
Substantially Reduces System Power Requirements
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
A
L, WL
Y, YY
W, WW
G or G
1
LVC
126A
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 0
1
Publication Order Number:
74LVC126A/D
74LVC126A
VCC
OE3
D3
O3
OE2
D2
O2
14
13
12
11
10
9
8
OE0
D0
OE1
1
2
3
4
5
6
7
OE0
D0
O0
OE1
D1
O1
GND
D1
1
OE2
2
3
O0 D2
4
OE3
5
6
Figure 1. Pinout: 14−Lead (Top View)
O1 D3
10
9
8
O2
13
12
11
O3
Figure 2. Logic Diagram
PIN NAMES
TRUTH TABLE
Pins
Function
OEn
Output Enable Inputs
OEn
Dn
On
Dn
Data Inputs
H
L
L
On
3−State Outputs
H
H
H
L
X
Z
INPUTS
OUTPUTS
H
= High Voltage Level
L
= Low Voltage Level
Z
= High Impedance State
X
= High or Low Voltage Level and Transitions Are
Acceptable; for ICC reasons, DO NOT FLOAT Inputs
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2
74LVC126A
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
DC Supply Voltage
Condition
Unit
−0.5 to +6.5
V
V
VI
DC Input Voltage
−0.5 ≤ VI ≤ +6.5
VO
DC Output Voltage
−0.5 ≤ VO ≤ +6.5
Output in 3−State
V
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State
(Note 1)
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for
10 Seconds
TL = 260
°C
TJ
Junction Temperature Under Bias
TJ = 135
°C
qJA
Thermal Resistance (Note 2)
SOIC = 85
TSSOP = 100
°C/W
MSL
Moisture Sensitivity
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Supply Voltage
Operating
Functional
Typ
Max
V
1.65
1.2
3.6
3.6
VI
Input Voltage
0
5.5
VO
Output Voltage
HIGH or LOW State
3−State
0
0
VCC
5.5
IOH
IOL
Units
V
V
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
−24
−12
mA
LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
24
12
mA
TA
Operating Free−Air Temperature
−40
+125
Dt/DV
Input Transition Rise or Fall Rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
0
20
10
°C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
74LVC126A
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
VIH
VIL
VOH
VOL
−405C to +1255C
Parameter
Conditions
Min
Typ
(Note 3)
Max
Min
Typ
(Note 3)
Max
Unit
HIGH−level input
voltage
VCC = 1.2 V
1.08
−
−
1.08
−
−
V
VCC = 1.65 V to 1.95 V
0.65 x
VCC
−
−
0.65 x
VCC
−
−
VCC = 2.3 V to 2.7 V
1.7
−
−
1.7
−
−
VCC = 2.7 V to 3.6 V
2.0
−
−
2.0
−
−
VCC = 1.2 V
−
−
0.12
−
−
0.12
VCC = 1.65 V to 1.95 V
−
−
0.35 x
VCC
−
−
0.35 x
VCC
VCC = 2.3 V to 2.7 V
−
−
0.7
−
−
0.7
VCC = 2.7 V to 3.6 V
−
−
0.8
−
−
0.8
LOW−level input
voltage
HIGH−level output
voltage
LOW−level output
voltage
V
V
VI = VIH or VIL
IO = −100 mA;
VCC = 1.65 V to 3.6 V
VCC −
0.2
−
−
VCC −
0.3
−
−
IO = −4 mA; VCC = 1.65 V
1.2
−
−
1.05
−
−
IO = −8 mA; VCC = 2.3 V
1.8
−
−
1.65
−
−
IO = −12 mA; VCC = 2.7 V
2.2
−
−
2.05
−
−
IO = −18 mA; VCC = 3.0 V
2.4
−
−
2.25
−
−
IO = −24 mA; VCC = 3.0 V
2.2
−
−
2.0
−
−
V
VI = VIH or VIL
IO = 100 mA;
VCC = 1.65 V to 3.6 V
−
−
0.2
−
−
0.3
IO = 4 mA; VCC = 1.65 V
−
−
0.45
−
−
0.65
IO = 8 mA; VCC = 2.3 V
−
−
0.6
−
−
0.8
IO = 12 mA; VCC = 2.7 V
−
−
0.4
−
−
0.6
IO = 24 mA; VCC = 3.0 V
−
−
0.55
−
−
0.8
VI = 5.5V or GND VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOZ
OFF−state output
current
VI = VIH or VIL;
VO = 5.5 V or GND; VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOFF
Power−off leakage
current
VI or VO = 5.5 V; VCC = 0.0 V
−
±0.1
±10
−
±0.1
±20
mA
ICC
Supply current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
−
0.1
10
−
0.1
40
mA
Additional supply
current
per input pin;
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.7 V to 3.6 V
−
5
500
−
5
5000
mA
II
DICC
Input leakage current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. All typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
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74LVC126A
AC ELECTRICAL CHARACTERISTICS (tR = tF = 2.5 ns)
−405C to +855C
Symbol
tpd
ten
tdis
tsk(0)
Parameter
Propagation Delay (Note 5)
Dn to On
Enable Time (Note 6)
OEn to On
Disable Time (Note 7)
OEn to On
−405C to +1255C
Conditions
Min
Typ1
Max
Unit
VCC = 1.2 V
−
12.0
−
−
−
−
ns
VCC = 1.65 V to 1.95 V
1.5
5.4
11.0
1.5
−
12.8
VCC = 2.3 V to 2.7 V
1.0
2.9
5.7
1.0
−
6.7
VCC = 2.7 V
1.5
2.8
5.5
1.5
−
7.0
VCC = 3.0 V to 3.6 V
1.0
2.5
4.8
1.0
−
6.0
VCC = 1.2 V
−
16.0
−
−
−
−
VCC = 1.65 V to 1.95 V
1.0
5.0
12.2
1.0
−
14.2
VCC = 2.3 V to 2.7 V
0.5
2.9
6.8
0.5
−
7.9
VCC = 2.7 V
1.5
3.1
6.6
1.5
−
8.5
VCC = 3.0 V to 3.6 V
1.0
2.3
5.4
1.0
−
7.0
VCC = 1.2 V
−
7.0
−
−
−
−
VCC = 1.65 V to 1.95 V
2.2
4.6
7.5
2.2
−
8.7
VCC = 2.3 V to 2.7 V
0.5
2.6
4.2
0.5
−
5.0
VCC = 2.7 V
1.5
3.1
5.0
1.5
−
6.5
VCC = 3.0 V to 3.6 V
1.0
3.2
4.6
1.0
−
6.0
−
−
1
−
−
1.5
Output Skew Time (Note 8)
Max
Min
Typ1
ns
ns
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
5. tpd is the same as tPLH and tPHL.
6. ten is the same as tPZL and tPZH.
7. tdis is the same as tPLZ and tPHZ.
8. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage (Note 9)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
VOLV
Dynamic LOW Valley Voltage (Note 9)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
9. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
CIN
COUT
CPD
Parameter
Condition
Typical
Unit
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
4.0
pF
Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
5.0
pF
Power Dissipation Capacitance
(Note 10)
pF
Per input; VI = GND or VCC
VCC = 1.65 V to 1.95 V
6.0
VCC = 2.3 V to 2.7 V
9.4
VCC = 3.0 V to 3.6 V
12.4
10. CPD is used to determine the dynamic power dissipation (PD in mW).
PD = CPD x VCC2 x fi x N + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF VCC = supply voltage in Volts
N = number of outputs switching
S(CL x VCC2 x fo) = sum of the outputs.
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5
74LVC126A
VCC
Vmi
Dn
Vmi
0V
tPLH
tPHL
VOH
Vmo
On
Vmo
VOL
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
OEn
VCC
Vmi
GND
tPZL
On
tPLZ
HIGH
IMPEDANCE
Vmo
tPZH
VOL + 0.3V
tPHZ
VOH - 0.3V
On
Vmo
HIGH
IMPEDANCE
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC Waveforms
VCC
Symbol
3.3 V ± 0.3 V
2.7 V
Vmi
1.5 V
1.5 V
VCC/2
Vmo
1.5 V
1.5 V
VCC/2
VCC < 2.7 V
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 015 V
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6
74LVC126A
VCC
VI
VO
PULSE
GENERATOR
R1
DUT
RT
CL
VEXT
OPEN
GND
RL
CL includes jig and probe capacitance
RT = ZOUT of pulse generator (typically 50 W)
R1 = RL
Supply Voltage
Input
Load
VEXT
VCC (V)
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
1.65 − 1.95
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
2.3 − 2.7
VCC
≤ 2 ns
30 pF
500 W
Open
2 x VCC
GND
2.7
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
3 − 3.6
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
Figure 4. Test Circuit
ORDERING INFORMATION
Package
Shipping†
74LVC126ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
74LVC126ADTR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
74LVC126A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
74LVC126A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
e
DETAIL A
h
A
X 45 _
M
A1
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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9
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74LVC126A/D