MC74LVX125 D

MC74LVX125
Quad Bus Buffer
With 5 V−Tolerant Inputs
The MC74LVX125 is an advanced high speed CMOS quad bus
buffer. The inputs tolerate voltages up to 7.0 V, allowing the interface
of 5.0 V systems to 3.0 V systems.
The MC74LVX125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
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Features
•
•
•
•
•
•
•
•
•
High Speed: tPD = 4.4 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.5 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
Human Body Model > 2000 V
Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
VCC OE3 D3
O3 OE2 D2
14
11
13
12
10
9
O2
8
ESD Performance:
1
OE0
OE2
2
D0
3
O0
D2
4
OE1
OE3
5
D1
6
O1
D3
1
2
OE0 D0
10
9
6
7
O1 GND
14−Lead (Top View)
8
O2
13
12
3
4
5
O0 OE1 D1
11
MARKING DIAGRAMS
14
O3
LVX125G
AWLYWW
Figure 1. Logic Diagram
1
SOIC−14 NB
PIN NAMES
Pins
Function
OEn
Dn
On
Output Enable Inputs
Data Inputs
3−State Outputs
14
LVX
125
ALYWG
G
1
FUNCTION TABLE
TSSOP−14
INPUTS
OUTPUTS
OEn
Dn
On
L
L
H
L
H
X
L
H
Z
LVX125
A
WL, L
Y
WW, W
G or G
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are
Acceptable, for ICC reasons, DO NOT FLOAT Inputs
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 4
1
Publication Order Number:
MC74LVX125/D
MC74LVX125
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation
180
mW
Tstg
Storage Temperature
–65 to +150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
3.6
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
−40
+85
_C
0
100
ns/V
TA
Dt/DV
Operating Temperature, All Package Types
Input Rise and Fall Time
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
1.5
2.0
2.4
VIH
High−Level Input
Voltage
2.0
3.0
3.6
VIL
Low−Level Input Voltage
2.0
3.0
3.6
VOH
High−Level Output
Voltage
(Vin = VIH or VIL)
IOH = −50mA
IOH = −50mA
IOH = −4mA
2.0
3.0
3.0
VOL
Low−Level Output
Voltage
(Vin = VIH or VIL)
IOL = 50mA
IOL = 50mA
IOL = 4mA
2.0
3.0
3.0
Iin
Input Leakage Current
Vin = 5.5V or GND
IOZ
Maximum Three−State
Leakage Current
ICC
Quiescent Supply
Current
Typ
TA = −40 to 85°C
Max
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.58
Max
2.0
3.0
0.0
0.0
Unit
V
0.5
0.8
0.8
1.9
2.9
2.48
V
V
0.1
0.1
0.36
0.1
0.1
0.44
V
3.6
±0.1
±1.0
mA
Vin = VIL or VIH
Vout = VCC or GND
3.6
±0.25
±2.5
mA
Vin = VCC or GND
3.6
4.0
40.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
MC74LVX125
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSHL
tOSLH
Parameter
Test Conditions
Propagation Delay
Input to Output
Output Enable Time
OE to O
Output Disable Time
OE to O
Output−to−Output Skew
(Note 1)
Min
TA = −40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 2.7V
CL = 15pF
CL = 50pF
5.8
8.3
10.1
13.6
1.0
1.0
13.5
17.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
4.4
6.9
6.2
9.7
1.0
1.0
8.5
12.0
VCC = 2.7V
RL =1kW
CL = 15pF
CL = 50pF
5.3
7.8
9.3
12.8
1.0
1.0
12.5
16.0
VCC = 3.3 ± 0.3V
RL =1kW
CL = 15pF
CL = 50pF
4.0
6.5
5.6
9.1
1.0
1.0
7.5
11.0
VCC = 2.7V
RL =1kW
CL = 50pF
10.0
15.7
1.0
19.0
VCC = 3.3 ± 0.3V
RL =1kW
CL = 50pF
8.3
11.2
1.0
13.0
VCC = 2.7V
VCC = 3.3 ± 0.3V
CL = 50pF
CL = 50pF
1.5
1.5
1.5
1.5
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
Symbol
Min
Parameter
TA = −40 to 85°C
Typ
Max
4
10
Min
Max
Unit
10
pF
Cin
Input Capacitance
Cout
Maximum Three−State Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2)
14
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.5
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.3
−0.5
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
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3
MC74LVX125
SWITCHING WAVEFORMS
VCC
VCC
D
OE
50%
50%
GND
GND
tPLH
O
tPZL
tPHL
O
50% VCC
HIGH
IMPEDANCE
50% VCC
tPZH
O
tPLZ
VOL +0.3V
tPHZ
VOH -0.3V
50% VCC
Figure 2.
HIGH
IMPEDANCE
Figure 3.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 4. Propagation Delay Test Circuit
Figure 5. Three−State Test Circuit
ORDERING INFORMATION
Package
Shipping†
MC74LVX125DG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
MC74LVX125DR2G
SOIC−14 NB
(Pb−Free)
2500 Tape & Reel
MC74LVX125DTG
TSSOP−14
(Pb−Free)
96 Units / Rail
MC74LVX125DTR2G
TSSOP−14
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74LVX125
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74LVX125
PACKAGE DIMENSIONS
D
SOIC−14 NB
CASE 751A−03
ISSUE K
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
e
DETAIL A
h
A
X 45 _
M
A1
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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MC74LVX125/D