FST3126 Product Preview 4-Bit Bus Switch The ON Semiconductor FST3126 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. The device consists of four independent 1−bit switches with separate Output/Enable (OE) pins. Port A is connected to Port B when OE is high. If OE is low, the switch is high Z. http://onsemi.com MARKING DIAGRAMS FST3126G AWLYWW 1 Features • • • • • • • • 14 14 SOIC−14 D SUFFIX CASE 751A RON t 4 W Typical Less Than 0.25 ns−Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin−For−Pin Compatible With QS3126, FST3126, CBT3126 All Popular Packages: SOIC−14 & TSSOP−14 These are Pb−Free Devices OE1 1A 1B OE2 2A 2B GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1 14 14 FST 3126 ALYWG G 1 TSSOP−14 DT SUFFIX CASE 948G VCC OE4 4A 4B OE3 3A 3B A WL, L Y WW, W G or G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN NAMES Figure 1. Pin Assignment for SOIC and TSSOP Pin OE1, OE2, OE3, OE4 Description Bus Switch Enables 1A, 2A, 3A, 4A Bus A 1B, 2B, 3B, 4B Bus B NC Not Connected ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2013 July, 2013 − Rev. P1 1 Publication Order Number: FST3126/D FST3126 OE1 1A OE2 2A OE3 3A OE4 4A 1 2 3 1B 4 5 6 2B 10 9 8 3B 13 12 11 4B Figure 2. Logic Diagram TRUTH TABLE Inputs Outputs OE A, B L Z H A=B ORDERING INFORMATION Package Shipping† FST3126DR2G SOIC−14 (Pb−Free) 2500 Units / Tape & Reel FST3126DTR2G TSSOP−14 (Pb−Free) 2500 Units / Tape & Reel Device Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 FST3126 MAXIMUM RATINGS Symbol Value Unit DC Supply Voltage *0.5 to )7.0 V VI DC Input Voltage *0.5 to )7.0 V VO DC Output Voltage *0.5 to )7.0 V VI t GND *50 mA VO t GND *50 mA 128 mA VCC Parameter IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Sink Current ICC DC Supply Current per Supply Pin $100 mA IGND DC Ground Current per Ground Pin $100 mA TSTG Storage Temperature Range *65 to )150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance (Note 1) MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup SOIC TSSOP _C _C 125 170 _C/W Level 1 Oxygen Index: 28 to 34 ESD Withstand Voltage Latchup Performance 260 )150 UL 94 V−0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model u4000 u300 u2000 V Above VCC and Below GND at 85_C (Note 4) $500 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate Min Max Unit 4.0 5.5 V (Note 5) 0 5.5 V (HIGH or LOW State) 0 5.5 V −55 +125 _C 0 0 5 DC ns/V Operating, Data Retention Only Switch Control Input Switch I/O 5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level. http://onsemi.com 3 FST3126 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIK Clamp Diode Resistance VIH High−Level Input Voltage VIL Low−Level Input Voltage Conditions IIN = *18mA VCC TA = −55_C to +125_C (V) Min Typ* 4.5 4.0 to 5.5 Max Unit *1.2 V 2.0 V 4.0 to 5.5 0.8 V Input Leakage Current 0 v VIN v 5.5 V 5.5 $1.0 mA IOZ OFF−STATE Leakage Current 0 v A, B v VCC 5.5 $1.0 mA RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 W VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.4 V, IIN = 15 mA 4.5 8 15 11 20 II VIN = 2.4 V, IIN = 15 mA 4.0 ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 mA DICC Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA *Typical values are at VCC = 5.0 V and TA = 25_C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. AC ELECTRICAL CHARACTERISTICS Limits TA = −55_C to +125_C VCC = 4.5 to 5.5 V Symbol Parameter Conditions Figures Min Max VCC = 4.0 V Min Max Unit 0.25 0.25 ns tPHL, tPLH Prop Delay Bus to Bus (Note 7) VI = OPEN 3 and 4 tPZH, tPZL Output Enable Time VI = 7 V for tPZL VI = OPEN for tPZH 3 and 4 1.0 4.5 5.0 ns tPHZ, tPLZ Output Disable Time VI = 7 V for tPLZ VI = OPEN for tPHZ 3 and 4 1.5 5.7 6.2 ns 7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Unit CIN Control Pin Input Capacitance VCC = 5.0 V 3 pF CI/O Input/Output Capacitance VCC = 5.0 V, OE = 0 V 5 pF 8. TA = )25_C, f = 1 MHz, Capacitance is characterized but not tested. http://onsemi.com 4 FST3126 AC Loading and Waveforms VI 500 W FROM OUTPUT UNDER TEST CL * 500 W NOTES: 1. Input driven by 50 W source terminated in 50 W. 2. CL includes load and stray capacitance. *CL = 50 pF Figure 3. AC Test Circuit tf = 2.5 nS 90 % SWITCH INPUT tf = 2.5 nS 90 % 1.5 V 3.0 V 1.5 V 10 % 10 % tPLH GND tPLH VOH 1.5 V OUTPUT 1.5 V VOL Figure 4. Propagation Delays tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 90 % 1.5 V 1.5 V 10 % 10 % GND tPZL tPZL OUTPUT 3.0 V 1.5 V tPZH VOL + 0.3 V VOL tPHZL VOH 1.5 V OUTPUT Figure 5. Enable/Disable Delays http://onsemi.com 5 VOH − 0.3 V FST3126 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE K D A B 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 C A M S B S DETAIL A h A X 45 _ M A1 e DIM A A1 A3 b D E e H h L M C SEATING PLANE SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ FST3126 PACKAGE DIMENSIONS TSSOP−14 DT SUFFIX CASE 948G ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U 0.25 (0.010) 8 S DETAIL E K A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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